lab234
TRANSCRIPT
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LAB2
module part1(SW,HEX0,HEX1,HEX2,HEX3);
input [15:0] SW;
output [6:0] HEX0,HEX1,HEX2,HEX3;
led myled3(SW[15:12],HEX3);
led myled2(SW[11:8],HEX2);
led myled1(SW[7:4],HEX1);
led myled0(SW[3:0],HEX0);
endmodule
module led(S,HEX7);
input [3:0] S;
output reg [6:0] HEX7;
always @(S)
case(S)
4'b0000: HEX7=7'b1000000;
4'b0001: HEX7=7'b1111001;
4'b0010: HEX7=7'b0100100;
4'b0011: HEX7=7'b0110000;
4'b0100: HEX7=7'b0011001;
4'b0101: HEX7=7'b0010010;
4'b0110: HEX7=7'b0000011;
4'b0111: HEX7=7'b1111000;
4'b1000: HEX7=7'b0000000;
4'b1001: HEX7=7'b0010000;
default: HEX7=7'b1111111;
endcase
endmodule
------------------------------------------------------------------------------------
module part2(SW,HEX1,HEX0);
input [3:0] SW;
output [6:0] HEX1,HEX0;
reg [6:0] HEX1,HEX0;
always @(SW[3:0])
begin
if ({SW[3],SW[2],SW[1],SW[0]}>4'b1001)
begin
HEX1=7'b1111001;
case (SW[3:0])
4'b1010: HEX0=7'b1000000;
4'b1011: HEX0=7'b1111001;
4'b1100: HEX0=7'b0100100;
4'b1101: HEX0=7'b0110000;
4'b1110: HEX0=7'b0011001;
4'b1111: HEX0=7'b0010010;
default: HEX0=7'b1111111;
endcase
end
else
begin
HEX1=7'b1000000;
case (SW[3:0])
4'b0000: HEX0=7'b1000000;
4'b0001: HEX0=7'b1111001;
4'b0010: HEX0=7'b0100100;
4'b0011: HEX0=7'b0110000;
4'b0100: HEX0=7'b0011001;
4'b0101: HEX0=7'b0010010;
4'b0110: HEX0=7'b0000011;
4'b0111: HEX0=7'b1111000;
4'b1000: HEX0=7'b0000000;
Std.Name : Dang Quang Hien
Std.Number : 0520016
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4'b1001: HEX0=7'b0010000;
default: HEX0=7'b1111111;
endcase
end
end
endmodule
------------------------------------------------------------------------------------
module part3(a,b,cin,sum,cout,co);
input [3:0] a,b;
input cin;
output [3:0] sum;
output [3:1] cout;
output co;
FA fa0(a[0],b[0],cin,sum[0],cout[1]);
FA fa1(a[1],b[1],cout[1],sum[1],cout[2]);
FA fa2(a[2],b[2],cout[2],sum[2],cout[3]);
FA fa3(a[3],b[3],cout[3],sum[3],co);
endmodule
module FA(a,b,cin,sum,cout);
input a,b,cin;
output sum,cout;
wire s1,s2,c1;
xor (s1,a,b);
and (c1,a,b);
xor (sum,s1,cin);
and (s2,s1,cin);
xor (cout,s2,c1);
endmodule
------------------------------------------------------------------------------------
module part4(A,B,ci,s,HEX6,HEX4,HEX1,HEX0);
input [3:0] A,B;
input ci;
output [3:0] s;
output [6:0] HEX6,HEX4,HEX1,HEX0;
wire [3:1] cout;
part3 my(A,B,ci,sum,cout,co);
assign s=sum;
check mycheck(co,s,HEX1,HEX0);
part2 my3(s,HEX1,HEX0);
part2 my4(A,HEX7,HEX6);
part2 my5(B,HEX5,HEX4);
endmodule
module check(cco,ss,HEX1,HEX0);
input cco;
input [3:0] ss;
output reg [6:0] HEX1,HEX0;
always @(cco or ss)
if (cco==1)
begin
HEX1=7'b1111001;
case(ss)
4'b0000: HEX0=7'b0000011;
4'b0001: HEX0=7'b1111000;
4'b0010: HEX0=7'b0000000;
4'b0011: HEX0=7'b0010000;
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default: HEX0=7'b1111111;
endcase
end
endmodule
------------------------------------------------------------------------------------
module part7(SW,HEX1,HEX0);
input [5:0] SW;
output [6:0] HEX1,HEX0;
integer s,temp,i,j,chuc,donvi;
reg [6:0] HEX1,HEX0;
always @(SW[5:0])
begin
s=0;
for (i=0;i
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part2 master(inv_Clk,D,Qm);
part2 slave(Clk,Qm,Qa);
assign Q=Qa;
endmodule
-----------------------------------------------------------------------------------
-
module part4(Clk,D,Qa,Qb,Qc);
input Clk,D;
output reg Qa,Qb,Qc;
always @(D,Clk)
if (Clk)
Qa
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4'b0110: hexa=7'b0000011;
4'b0111: hexa=7'b1111000;
4'b1000: hexa=7'b0000000;
4'b1001: hexa=7'b0010000;
4'b1010: hexa=7'b0001000;
4'b1011: hexa=7'b0000011;
4'b1100: hexa=7'b1000110;
4'b1101: hexa=7'b0100001;
4'b1110: hexa=7'b0000110;
4'b1111: hexa=7'b0001110;
endcase
endfunction
endmodule
LAB4module part1(aClk,aEn,aReset,aQ,HEX0,HEX1,HEX2,HEX3);
input aClk,aEn,aReset;
output [15:0] aQ;
output [6:0] HEX0,HEX1,HEX2,HEX3;
FF_D FFT0(aClk,aEn,aReset,aQ[3:0]);
led myled0(aQ[3:0],HEX0);
FF_D FFT1(aClk,aEn,aReset,aQ[7:4]);
led myled1(aQ[7:4],HEX1);
FF_D FFT2(aClk,aEn,aReset,aQ[11:8]);
led myled2(aQ[11:8],HEX2);
FF_D FFT3(aClk,aEn,aReset,aQ[15:12]);
led myled3(aQ[15:12],HEX3);
endmodule
module FF_D(Clk,En,Reset,Q);
input Clk,En,Reset;
output [3:0] Q;
reg R,Sg,Rg,Qa,Qb;
reg [4:0] Counter;
integer i;
always @(posedge Clk or negedge Reset)
if (!Reset)
Counter
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4'b0011: HEX7=7'b0110000;
4'b0100: HEX7=7'b0011001;
4'b0101: HEX7=7'b0010010;
4'b0110: HEX7=7'b0000011;
4'b0111: HEX7=7'b1111000;
4'b1000: HEX7=7'b0000000;
4'b1001: HEX7=7'b0010000;
4'b1010: HEX7=7'b0001000;
4'b1011: HEX7=7'b0000011;
4'b1100: HEX7=7'b1000110;
4'b1101: HEX7=7'b0100001;
4'b1110: HEX7=7'b0000110;
4'b1111: HEX7=7'b0001110;
endcase
endmodule
------------------------------------------------------------------------------------
module part2(aClk,aEn,aReset,aQ,HEX0,HEX1,HEX2,HEX3);
input aClk,aEn,aReset;
inout [15:0] aQ;
output [6:0] HEX0,HEX1,HEX2,HEX3;
FF_T my0(aClk,aEn,aReset,aQ[3:0]);
led myled0(aQ[3:0],HEX0);
FF_T my1(aClk,aEn,aReset,aQ[7:4]);
led myled1(aQ[7:4],HEX1);
FF_T my2(aClk,aEn,aReset,aQ[11:8]);
led myled2(aQ[11:8],HEX2);
FF_T my3(aClk,aEn,aReset,aQ[15:12]);
led myled3(aQ[15:12],HEX3);
endmodule
module FF_T(Clk,En,Reset,Q);
input Clk,En,Reset;
output [3:0] Q;
reg [3:0] Counter;
always @(posedge Clk or negedge Reset)
if (!Reset)
Counter
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lpm_counter lpm_counter_component (
.clk_en (clk_en),
.aclr (aclr),
.clock (clock),
.cnt_en (cnt_en),
.q (sub_wire0),
.aload (1'b0),
.aset (1'b0),
.cin (1'b1),
.cout (),
.data ({16{1'b0}}),
.eq (),
.sclr (1'b0),
.sload (1'b0),
.sset (1'b0),
.updown (1'b1));
defparam
lpm_counter_component.lpm_direction = "UP",
lpm_counter_component.lpm_port_updown =
"PORT_UNUSED",
lpm_counter_component.lpm_type ="LPM_COUNTER",
lpm_counter_component.lpm_width = 16;
endmodule
------------------------------------------------------------------------------------module part4(aClk,aReset,aQ,HEX0);
input aClk,aReset;
output [3:0] aQ;
output reg [6:0] HEX0;
wire T;
divClk myClk(aClk,T);
change mychange(T,aReset,aQ);
always @(aQ)
case (aQ)
4'b0000: HEX0=7'b1000000;
4'b0001: HEX0=7'b1111001;
4'b0010: HEX0=7'b0100100;
4'b0011: HEX0=7'b0110000;
4'b0100: HEX0=7'b0011001;
4'b0101: HEX0=7'b0010010;
4'b0110: HEX0=7'b0000011;
4'b0111: HEX0=7'b1111000;
4'b1000: HEX0=7'b0000000;
4'b1001: HEX0=7'b0010000;
default: HEX0=7'b1111111;
endcase
endmodule
module divClk(Clk,delay1s);
input Clk;
output delay1s;
reg [25:0] tg;
always @(posedge Clk)
if (tg==49999999)
tg=26'd0;
else
tg=tg+26'd1;
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assign delay1s=(tg
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3'b001: begin
HEX7 = `BLANK; HEX6 = `BLANK; HEX5 = `H; HEX0 =`BLANK;
HEX4 = `E; HEX3 = `L; HEX2 = `L; HEX1 = `O;
end
3'b010: begin
HEX7 = `BLANK; HEX6 = `H; HEX1 = `BLANK; HEX0 =`BLANK;
HEX5 = `E; HEX4 = `L; HEX3 = `L; HEX2 = `O;
end
3'b011: begin
HEX7 = `H; HEX2 = `BLANK; HEX1 = `BLANK; HEX0 =`BLANK;
HEX6 = `E; HEX5 = `L; HEX4 = `L; HEX3 = `O;
end
3'b100: begin
HEX3 = `BLANK; HEX2 = `BLANK; HEX1 = `BLANK; HEX0 =`H;
HEX7 = `E; HEX6 = `L; HEX5 = `L; HEX4 = `O;
end
3'b101: begin
HEX4 = `BLANK; HEX3 = `BLANK; HEX2 = `BLANK; HEX1 =`H;
HEX0 = `E; HEX7 = `L; HEX6 = `L; HEX5 = `O;
end
3'b110: begin
HEX5 = `BLANK; HEX4 = `BLANK; HEX3 = `BLANK; HEX2 =`H;
HEX1 = `E; HEX0 = `L; HEX7 = `L; HEX6 = `O;
End
3'b111: begin
HEX6 = `BLANK; HEX5 = `BLANK; HEX4 = `BLANK; HEX3 =`H;
HEX2 = `E; HEX1 = `L; HEX0 = `L; HEX7 = `O;
end
endcase
endmodule