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MOSFET(metal-oxide-semiconductor

field effect transistor)

May 8, 2023

Dr. Radu Florescu Dr. Vladislav Shteeman

Advanced Laboratory for Characterization of Semiconductor Devices - 31820

Department of Electrical & Electronic Engineering Braude College of Engineering

Department of Electrical and Electronic Engineering ORT Braude College of Engineering

Advanced Laboratory for Characterization of Devices – 31820

The goal.The goal of the laboratory is to investigate the operation of a real long-channel MOSFET

device. You will measure and estimate the following characteristics of the transistor:

1. Output characteristics : I DS (V DS ,V GS )

1.1. Channel conductance gd in the linear region.

1.2. Threshold voltage V T .

1.3. Effective carrier mobility μeff (as a function of V GS−V T ).

1.4. Channel-length modulation parameter (λ ) in the saturation region.

1.5. Effective channel length Leff (as a function of V DS ).

2. Transfer characteristics: I DS (V GS ) and transconductance gm (V GS ) in the linear region.

2.1. Threshold voltage V T .

2.2. Effective carrier field effect mobility μeff .

3. Optoelectronic characteristics (optional):

3.1. Output characteristics familyI DS (V DS ,V GS )

3.2. Threshold voltage V T (from the transconductancegm (V GS) ) for 3 different lightening

conditions: darkness, moderate lightening and strong lightening.

Dr. Radu Florescu Dr. Vladislav Shteeman 2



Short theoretical background.

MOSFET [1](metal-oxide-semiconductor field-effect transistor) is a three-terminal device, which enables

to use one electrical signal to control (amplify) another signal. This device belongs to the class of field-effect

transistors. Depending of the conductivity type (electrons or holes) and corresponding conductive channel,

there are 2 kinds of MOSFETs: nMOSFET and pMOSFET.

Figure 1. Sketch of MOSFET transistor (after [1]).

nMOSFET transistor consists of two regions (Figure 1): the source and the drain of n-type conductivity

silicon, embedded in a body of the p-type conductivity Si. The space between the source and the drain is

covered by a thin layer of silicon dioxide (SiO2, silica) formed by heating the silicon in an oxidizing

atmosphere. A third part of the device, the gate, is a thin layer of polysilicon (playing a role of metal),

deposited on the silicon dioxide.

The source of nMOSFET is generally used as the voltage reference and is grounded (Figure 2). When no

voltage is applied to the gate, the source-to-drain electrodes correspond to two p-n junctions connected




back to back. The only current that can flow from source to drain is a small leakage current. When a high

positive bias is applied to the gate, a large number of electrons will be attracted to the semiconductor

surface and form a conductive layer just underneath the oxide. The n+ source and n+ drain are now

connected by a conducting surface n layer (or channel) through which a large current can flow. The

conductance of this channel can be modulated by varying the gate voltages; the conductance also can be

changed by the substrate bias.

Figure 2. nMOSFET transistor sketch (after [1]).

MOSFET was invented in 1959 by D. Kahng and M. Atalla at Bell Labs (USA). Currently, MOSFET is the most

important device for very-large-scale integrated circuits.

There are 3 main reasons why the MOSFET has surpassed the bipolar transistor and become the dominant

device for very-large-scale integrated circuits are:

1. MOSFET can be easily scaled down to smaller dimensions;

2. MOSFET consumes much less power than its bipolar counterpart;

3. MOSFET has relatively simple processing steps. This results in a high manufacturing yield (i.e. high

ratio of good devices to the total number of manufactured transistors).




1. MOSFET operation modes [ 2 ].

Figure 3. Family of nMOSFET output I-V characteristics (after [25]).

[1] Cutoff mode (sub-threshold or weak-inversion mode).

Figure 4. Cutoff mode of nMOSFET transistor (after [2]).

WhenV GS<V T ,(Figure 4) transistor is turned off, and there is no conduction between the drain and the source. In the reality, the Boltzmann distribution of electron energies allows some of the more energetic electrons at the source to enter the channel and flow to the drain, resulting in a sub-threshold current that is an exponential function of gate–source voltage. While the current between drain and source should ideally be zero when the transistor is being used as a turned-off switch, there is a weak-inversion current, sometimes called sub-threshold leakage.


Drain-to-source voltage VDS [V]

Dra

in c

urre

nt I D

S [μA

]

VGS > VT

VDS << (VGS-VT)

VGS > VT

VDS > (VGS-VT)

VGS > VT

VDS = (VGS-VT)



[2] Linear mode (triode or ohmic mode).

Figure 5. Linear mode of nMOSFET transistor (after [2]).

When V GS>V T and V DS<(V GS−V T ) (Figure 5), transistor is turned on, and the channel is created. The

MOSFET operates like a resistor controlled by the gate voltage relative to both the source and drain voltages (Figure 6):

0.0 0.1 0.2 0.3 0.4 0.50.0E+00

5.0E-06

1.0E-05

1.5E-05

2.0E-05

2.5E-05

3.0E-05

3.5E-05

4.0E-05

IDS - VDS characteristics for nMOSFETin the linear region: VDS < 0.5 [V].

Vgs = 3 [V]

Vgs = 4 [V]

Vgs = 5 [V]

Vgs = 6 [V]

Vgs = 7 [V]

Vgs = 8 [V]

Drain - Source voltage VDS [V]

Drai

n - S

ourc

e cu

rren

t ID

S [A

]

Figure 6. Example of I-V characteristics of nMOSFET in the linear region (VGS < 0.5 [V]).

In the linear region, for which holds V DS<(V GS−V T ) ), the drain-source current IDS can be written as:

I DS=WL μeff C 'OX ((V GS−V T ) V DS−

V DS2

2 ) (linear , V DS< (V GS−V T ))(1)

where μeff is a surface mobility (holes for pMOS and electrons for nMOS), W ∧ Lare width and length of

the channel and C ' OX is an oxide layer capacitance per unit area (see List of symbols in Appendix 1).




Furthermore, if V DS << (V GS−V T ) , the

V DS2

2 in the equation above can be neglected, thus I DS becomes a

linear function ofV DS :

I DS=WL

μeff C 'OX (V GS−V T ) V DS (linear , V DS << (V GS−V T ))(2)

[3] Saturation mode (active mode).

Figure 7. Saturation mode of nMOSFET transistor (after [2]).

When V GS>V T and V DS>(V GS−V T ) (Figure 7), transistor enters into the saturation mode.

Figure 8. Example of I-V characteristics of nMOSFET in the saturation region: VGS ≥ (VDS - VT).


0 1 2 3 4 5 6 7 80.0E+002.0E-054.0E-056.0E-058.0E-051.0E-041.2E-041.4E-041.6E-04

IDS - VDS characteristics for nMOSFETin the saturation region: VDS ≥ (VGS - VT).

Vgs = 3 [V]Vgs = 4 [V]Vgs = 5 [V]Vgs = 6 [V]Vgs = 7 [V]Vgs = 8 [V]

Drain - Source voltage VDS [V]

Drai

n - S

ourc

e cu

rren

t ID

S [A

]



In this case (Figure 8)

IDS=± W2 L

μeff C 'OX (V GS−V T )2 (saturation , V DS≥(V GS−V T )) (+ for nMOS, - for pMOS) (3)

Note, that because of so-called “body effect” (see explanation below and Appendix 1), the threshold voltage V T in our measurements is large than expected for the grounded device (V T≈1.81 [ V ] ) and I DS (V DS ,V GS ) characteristics family is “lower” than that expected for grounded transistor.

0 1 2 3 4 5 6 7 80.0E+002.0E-054.0E-056.0E-058.0E-051.0E-041.2E-041.4E-041.6E-04

IDS,sat - VDS,sat characteristics of nMOSFET

Vgs = 3 [V]Vgs = 4 [V]Vgs = 5 [V]Vgs = 6 [V]Vgs = 7 [V]Vgs = 8 [V]I sat - V sat

Drain - Source voltage VDS [V]Dra

in -

Sour

ce c

urre

nt I

DS

[A]

Figure 9. Body effect influence on the IDS,sat - VDS,sat characteristics of nMOSFET transistor.




2. Body effect [ 5 ] . (see also List of definitions in Appendix 1)

Normally, the MOSFET body is connected to the lowest voltage potential of the circuit (usually the source) (Figure 10).

Figure 10. nMOSFET with grounded body (no body effect) (after [5]).

Nevertheless, if the body is left unconnected, it affects the threshold voltage V T and I DS (V DS ,V GS ) characteristics of the device, biased in linear and saturation regimes.

Specifically, channel voltage V channel ( y ) depends on position y along the channel (Figure 11).

Figure 11. Channel voltage V channel ( y ) dependence on position y along the channel (after [5]).

In this case, threshold voltage V T ( y ) also becomes y-dependent (namely, it increases along y).




Figure 12. In case of Body effect, threshold voltage increases along the channel (after [5]).

Dependence of V T ( y ) further debiases transistor: I DS becomes lower than ideal and V DS, sat becomes

lower than ideal (Figure 13).

Figure 13. Body effect influence on the family of characteristics I DS (V DS ,V GS ) (after [5]).

Three noticeable features:

1. for all values of V GS and V DS , body effect reduces I DS

2. for given V GS , body effect reduces V DS, sat3. body effect goes away as transistor is turned off


I DS (

arbi

trary

uni

ts)



3. Channel length modulation effect [ 10 ] . (see also List of definitions in Appendix 1)

Above the “pinch-off” voltage (i.e. for V DS>V DS, sat (where V DS, sat=V GS−V T )) the physical channel length

L is reduced by a value ΔL (Figure 14).

Figure 14. Channel length L and effective channel length Leff in saturation region for V DS>V DS, sat (after [10]).

In this case, the expression for I DS (for V DS≥V DS , sat ) (without body effect) becomes [10]:

IDS=± W2L

μeff C 'OX (V GS−V T )2 (1+λV DS)=± W2Leff

μeff C 'OX (V GS−V T )2

(+ for nMOS, - for pMOS) (4)

Accounting for body effect (specifically, for V DS, sat≠V GS−V T ) results in the following correction to Eq. (4):

IDS=± W2 L

μeff C 'OX V DS , sat2 (1+ λV DS )=± W

2 Leffμeff C ' OX V DS , sat

2

(+ for nMOS, - for pMOS) (5)

(This is the relevant expression for I DS in our case)

In Eqs. (4)-(5), effective channel length Leff relays to physical length L and channel length modulation parameter, λ , as follows:




Leff =L

1−λV DS<L

(6)

The fact, that Leff < L , results in a small increase of I DS with increasing of V DS in saturation region (Figure

15). Channel length modulation parameter ,λ , corresponds to the point of intersection of the tangent to

the I DS (V DS )curve in saturation region with the V DS axis.

Figure 15. Graphical illustration to definition of channel length modulation parameter λ .

λ can be calculated (separately for each gate V GS ) from the I−V characteristics of MOSFET in saturation

region (Figure 16). Namely, for each gate V GS , one should find (using trendline) the linear equation of the I DS (V DS ) curve in saturation region. If a free term and a slope of the linear equation are known,

λ= slopefree term .




Figure 16. Illustration to calculation of λ from I−V characteristics of nMOSFET in saturation region.

If λ is known - Leff can be found (separately for each gate V GS ) from Eq. (6).

4. Effective mobility [ 12 ] . (see also List of definitions in Appendix 1)

Figure 17. nMOSFET structure and coordinate orientation, assumed in the quantitative analysis of effective mobility (after [12]).




In the semiconductor bulk, i.e. at a point far removed from the semiconductor surface, the carrier mobilities

(namely, bulk mobilities μhole and μe ) are determined by the amount of lattice scattering and ionized impurity scattering, taking place inside the material. For a given temperature and doping, those bulk

mobilities, μhole and μe , are well-defined.

Carrier motion in MOSFET, however, takes place in an inversion layer at the interface between Si and SiO2 . Due to additional lattice defects, associated with the Si−SiO2 interface, and due to the quantum confinement of the carriers in the triangular quantum well of MOS structure, carriers mobility in the channel differs significantly from that of bulk. Note that the channel is located under the gate, where the gate-induced electric field acts so as to accelerate the carriers towards the surface. The inversion layer

carriers therefore experience motion impending collisions with the Si interface in addition to surface and impurity scattering (see Figure 18). This lowers the mobility of the carriers, with the carriers constrained

nearest the Si surface experiencing the greatest reduction in mobility. The resulting average mobility of

the inversion layer is called the effective mobility μeff . Obviously, μeff <μhole( e )always holds.

Figure 18. Visualization of surface scattering at the Si−SiO2 interface (after [12]).

Relative to the dependence of μeff on the gate voltage V GS , increased inversion biasing increases the x-

direction electric field acting on the carriers closer to the Si−SiO2 interface. Surface scattering is

enhanced and μeff therefore decreases. Usually (at least for long-channel devices) the dependence of μeff

vs V GS can be described by the following empirical expression:

μeff =μ0

1+θ (V GS−V T ) (7)

where μ0 (called surface carrier’ mobility) and θ (called mobility degradation factor) are constant.




Figure 19. Experimental curve of μeff vs V GS−V T for nMOSFET N1 (see Appendix 2 for details).

5. Optoelectronic effects in MOSFETs.

Parasitic currents can be generated in transistors by external lighting. The origin of this current is the carriers, excited by light at the p-n junctions, which are the essential part of the MOSFET technology. Those currents may affect performances of MOSFET and should be avoided. The best way to do this – is to black out the device.

In our chip, the transistor most greatly affected by light induced currents is N4. This occurs when pin 11 is

the source and pin 6 is the grain (see Appendix 2 for the chip details). A current of ~ 200 μA may be

produced. Light induced currents of ~ 20 μA may affect also the transistors P2 and P3. The only effective cure is blackout.

See Appendix 5 for the expected results of the light influence on the n-MOSFET performances.




Experimental set-up.The experimental setup includes:

[1] Test fixture Probe station with dual in-line package (18 pins), connected (by the triax cables No

9,10,11,12) to the Keithley matrix.

[2] External voltage supply device. This supply must be connected to the pins 8 (external ground, V=0)

and 16 (Vcc = +10 V) of the chip in order to “tell” him the range of the voltage variation. (See also

“Information on usage” in the Additional details of Appendix 2).

Figure 21. External voltage supply device.

See Appendix 6 for pin connections scheme for the N1 transistor.


Figure 20.Test fixture Probe station with dual in-line package (18 pins)



[3] Keithley program .




Assignments and analysis.Note: after executing the room temperature measurements (Parts I and II below) and before

processing the acquired data, save this Excel template on your computer (double click on the

Excel icon File Save as … ). Then close the Excel template and open the Excel file, saved recently.

Copy the results of the measurements (located in the measurements folder of Keithley in the

subdirectory “tests/data”), namely, data from the files “vds-id#[email protected]” and “vgs-id#[email protected]” to the

Excel template, saved on your computer.

Part I. Output characteristics IDS ( V DS ,V GS ) (at the room temperature)

Measurements:

Acquire the family of the output characteristicsIDS (V DS ,V GS ) for the nMOS transistor N1 for 15

different values of V GS , namely:

V GS voltage must vary in the range from 3 to 10 V (step 0.5 V);

for each of the V GS voltages, V DS voltage must vary from 0 to 9 V (step 0.05 V) (see Appendix 3 for

the ranges of V DS and V GS values).


linear domain VDS < 0.5 [V]



Data processing and analysis:

After finishing all the measurements, transfer the acquired data (file “vds-id#[email protected]”, located in the

measurements folder of Keithley in the subdirectory “tests/data”) to the Excel template.

[1]Compute C 'OX gate oxide capacitance per unit area according to the formula

C 'OX=ε0 εox

tox[ Fcm2 or F

m2 ] (see C 'OX

definition in the List of symbols in Appendix 1).

[2]Plot the family of output characteristicsIDS (V DS ,V GS ) .

[3]Estimate the conductancegd . Using the linear fit (linear trend-line) for the linear parts of the graphs

I DS (V DS ,V GS ) (0≤V DS≤0 . 5 ) and find the conductance gd=

∂ I DS ,lin

∂ V DS for each of the V GS values.

Note that according to the model, gd is a linear function of the V GS :

gd=WL

μeff C 'OX (V GS−V T )

[4]Plot gd as a function ofV GS . Is the graph looks linear as expected from the long channel model? (explain).

[5]Find the threshold voltageV T . To do this, from the same linear fit gd vs V GS , extract the value of V T ,

being an intersection of the fitting line with the V GS axis.

[6]Return to the graph of family of output characteristicsI DS (V DS ,V GS ) . From the graphs

I DS (V DS ) , measure the

I DS, sat value corresponding to the V DS, sat

=V GS−V T for the different V GS values and fill in the calc table. Add this graph to the plot.

[7]Evaluate the effective mobilityμeff . To do this:

Fill in the calc table with the V GS−V T values.

Evaluate the effective mobility μeff for each of the gd and (V GS−V T ) pairs using the formula:

gd=WL

μeff C 'OX (V GS−V T ) . Fill in the column μeff (experimental).

Plot graph gd vs (V GS−V T ) . Add linear trendline to the graph and find its slope. This slope is

nothing but

WL

μeff C 'OX. (Note that according to the model, gd is a linear function of (V GS−V T )




without free term. Practically, the trendline does contain free term. Thus, there is a clear discrepancy between the model and the experimental results. We’ll correct it (apply more accurate model) in the next item.)

In the calc table, fill in the cell corresponding to a single, average value of μeff :

μeff =trendline ' slope

WL

C ' OX

[8]In order to explain the experimental results, showing that the connection gd vs (V GS−V T ) includes free

term , one can assume that μeff =

μ0

1+θ (V GS−V T ) (where μ0 is a surface carriers’ mobility in Si at 300

K) and θ is the degradation factor (see List of symbols in Appendix 1); both μ0 and θ are constant).

Determine the μ0 and θ . To do this:

In the calc table, fill in the column

1μeff .

Plot graph (V GS−V T ) vs

1μeff . Add linear trendline to the graph and find its slope and free

term.

If, according to the model, μeff =

μ0

1+θ (V GS−V T )

1μeff should be a linear function of the

V GS−V th parameter:V GS−V T=

μ0

θ1

μeff−1

θ . From the slope and the free term of the trendline

of

1μeff vs.(V GS−V th ) , find the values of μ0 andθ . Explain why the surface mobility is different

from the bulk mobility.

[9]Estimate the effective channel length Leff . From the saturation regions of the family ofI DS=f (V DS ,V GS ) graphs, one can calculate (using Eq. 3) the effective channel’ length Leff . Make a

plot Leff (V GS ) .

[10]Determine channel length modulation parameter, λ , for different gates V GS . To do this, make a plot I DS−V DS in the saturation region (say, between the points V DS=5 V and V DS=10 V ) for each of

the V GS values. Then add a linear trendline (and its equation) to each of the curves. λ is a point of

intersection between the trendline and the x-axis. Put λ values in the calc table. Make a plot λ (V GS ) .




Final report must include the following graphs (appearing in the Excel template) with explanations :

[1] Family of I DS (V DS ) for different V GS

[2] gd vs V GS

[3]μeff vs (V GS−V T )

[4] (V GS−V T ) vs 1 /μeff

[5] Leff vs V GS

[6] λ vs V GS




Part II. Transfer characteristics I DS (V GS ) (at the room temperature)

Measurements:

Acquire the transfer characteristicsI DS (V GS ) and transconductance

gm (V GS ) (for constant

V DS=0. 1 [ V ] ) for the nMOS transistor N1 (see Appendix 3 for the measurement settings).

Data processing and analysis:

[1] Explain why the transconductance,gm , has maximum in the linear region.

[2] Consider Eq. 1, giving I DS as a function of V DS and V GS in the linear region. Find the

differential

∂ I DS

∂V GS (i.e. find transconductance gm (see List of symbols in Appendix 1)) and show

that :

V GS ,i=V GS ,max−IDS ,max

gm ,max

I DS ,max=±WL

μeff (Cox ) (V GS ,max−V T−V DS/2 )V DS




where I DS ,max and V GS ,max are the current and the voltage corresponding to thegm ,max , and

V GS ,i gate-source voltage (expected) intersection with the x-axis (“Gate voltage”) on the graph

IDS= f (V GS ) (i.e. V GS expected value forI DS=0 )

[3] Show that the extrapolated (measured) value of the intersection voltage V GS ,i equals to the

V T+V DS/2 .

[4] Estimate the V T from theV GS ,i .

After finishing all the measurements, transfer the acquired data (file “vgs-id#[email protected]”, located in the

measurements folder of Keithley in the subdirectory “tests/data”) to the Excel template.

[5] Fill the calc table with thegm and (V GS−V T ) values.

[6] Calculate μFE=μeff in the calc table from the gm value using the following definition:

μFE=μeff =Lgm

WC 'OX V DS . Plot a graphμeff vs (V GS−V T ) .


V GS ,i



[7] Fill the calc table with the 1/ μeff values. Plot a graph (V GS−V T ) vs 1/ μeff (only the part,

corresponding to the monotonic decreasing section of μeff vs (V GS−V T ) , i.e. to the range of

voltages 1≤(V GS−V T )≤6 ).

[8] Assume that μFE=μeff =

μ0

1+θ (V GS−V T ) . Use the linear regression fit to the graph above to

find the parameters μ0 and the degradation factor θ .

[9] Extract the surface mobility of carriers, μ0 , and the degradation factor, θ , for high V GS values.

[10] Compare to values obtained for μ0 in the Part I and explain the difference.

Final report must include the following graph (appearing in the Excel template) with explanations :

[1]I DS (V GS ) and

gm (V GS ) (a single plot)

[2]μeff vs (V GS−V T )

[3] (V GS−V T ) vs 1 /μeff

Part III. Output characteristics IDS ( V DS ,V GS ) (under heating conditions)

Acquire the families of the output characteristicsI DS (T )= f (V DS (T ) , V GS (T ) ) of the nMOS transistor

N1 in the temperature range from 25∘C to 75∘C (with the steps of approximately 10∘C ). Similarly

to the assignment of the Part I, for each of the temperatures acquire the family of IDS=f (V DS ,V GS )

characteristics for 15 different values of V GS , namely:

V GS voltage should vary in range from 3 to 10 V (step 0.5 V);

for each of the V GS voltages, V DS voltage should vary in range from 0 to 10 V (step 0.05 V);




Important: execute the 1st measurement (under room temperature) using the green button , and all the rest of the measurements (under heating conditions, for 4-6 different temperatures) using the yellow-greed

button (“append”). DO NOT use the green button for the measurements under heating conditions: it will override all your previous measurements.) After each measurement save the data in the Keithley program.

After finishing the measurements, you should process the data using a Matlab program. To do this:

1. Double-click on the zip-file icon

2. In the dialog window press “open”.

3. In the newly opened window, the folder named “MOSFET heating processing” will appear.

4. Drag this folder to the Desktop of your computer.




5. In the Keithley measurements folder (subfolder tests/data) find the files vds-id#[email protected] (I DS (V DS ,V GS ) data) & vgs-id#[email protected] (I DS (V GS ) data)

6. Copy the files vds-id#[email protected] & vgs-id#[email protected] to the folder “MOSFET heating processing”:

7. Double-click on the file processed_data_MOSFET_sf.m in the directory “MOSFET heating processing”. This will start Matlab. Wait for 1-2 minutes to allow Matlab start.

8. Go to the Matlab Editor window and run the file rocessed_data_MOSFET_sf.m (press F5 or Debug Run on the Editor menu bar).




9. The program will ask you to input the temperatures, at which you measured the transistor. Input the temperatures in the square parentheses with the spaces between the different values, e.g. [25 35 45 55 65 75]. Press Enter to continue.

10. Wait for 1-2 minutes until the program will finish the processing of the measured data.

11. The results of the computations (Excel file processed_data.xls, Matlab files and figures) are located in the subfolder Results.




Final report must include the following graphs with explanations :

[1] The graph of the saturation current as a function of the temperature,

I DS ,sat (T ) for each of the 15 different V GS values. (Single figure, 15 different curves, each curve should contain 6 points (according to the number of different temperature values)).

[2] The graph of the conductance as a function of the temperature gd (T )

for each of the values V GS . (Single figure, 15 different curves, each curve should contain 6 points, corresponding to the 6 different temperatures).

[3] The graph of the threshold voltage as a function of the temperature, V T (T ) .

[4] The graph of the max transconductance value as a function of the temperature,

gm(max) (T ) .




[5] The graph of the drain current as a function of the pinch-off voltage I DS (V DS=(V GS−V T )) (where pinch-off voltage is a V DS voltage, for which

holds V DS=(V GS−V T ) ) for all the temperature values. (Single figure, 6 different curves for 6 different temperatures, each curve should contain 15

points (according to the number of the different V GS values)).




AcknowledgementElectrical Engineering Department of Braude College would thank to Mr. David Furman for his extensive help and support in preparation of this laboratory work.

Some parts of this guide were adapted from the MOSFET guide of the Advanced Semiconductor Devices Lab (83-435) of School of Engineering of Bar-Ilan University. We would like to thank Dr. Abraham Chelly for the granted manual.




Appendix 1 : List of symbols and definitions

List of symbols

μhole ( e ) - bulk mobility of carriers (holes in pMOS and electrons in nMOS) (for Si,

μhole=471 [ cm2

V⋅sec ],

μe=1350 [ cm2

V⋅sec ] )

μeff - effective (acquired from the experimental measurements) mobility of carriers in the channel; μeff <μhole( e )always holds. μeff is influenced both by the fact, that the channel located at the interface

between Si and SiO2 (with associated lattice defects) and by the quantum confinement of the carriers in the triangular quantum well of MOS structure.

W, L – channel width and length. For our transistors: L=100 [ μm ] , W varies from transistor to

transistor (see Appendix 2 for details)

Leff - effective channel length modulated by VDS.

λ - channel length modulation parameter (0< λ<1 )

t ox - oxide layer’ thickness. For our transistors tox=100 [ nm ] (see Appendix 2 for details)

ε ox - oxide layer’ (relative) dielectric constant. ε ox=3.9 (see Appendix 2 for details)

ε 0 - permittivity of vacuum. ε 0=8 .85×10−14 [F

cm]=8 . 85×10−12 [F m]

C ' ox - gate oxide capacitance (per unit area): C ' ox=

ε0 εox

t ox[ F

cm2 or Fm2 ]

.

V GS ,V DS - gate-source and drain-source voltage

V GS , i gate-source voltage (expected) intersection with the “Gate voltage” axe (V GS ) (x-axe) on

the graph IDS=f (V GS ) (i.e. expected V GS

value forI DS=0 )

V T - threshold voltage (the gate-source voltage at which a transistor starts to conduct)

V T ( y ) - position-inside-channel dependent threshold voltage (as the result of Body effect)

V T 0≡V T (0 ) - threshold voltage at the beginning of the channel (for position-inside-channel dependent

threshold voltage V T ( y ) )

V DS, sat saturated drain-source voltage V DS, sat=V GS−V T

V channel ( y ) MOSFET channel voltage (position-dependent because of Body effect)

gm - transconductance of the channel (depends on V GS ):




gm=|∂ IDS

∂ V GS|V DS=const

=¿ {WL

⋅μeff ¿C 'ox ¿V DS ( linear region )¿ {¿¿¿¿.

μFE=μeff field effect mobility: μFE=μeff =

Lgm

WCox V DS>0

gd - channel conductance in the linear region: gd=

∂ IDS ,lin

∂V DS=−W

Lμeff C ' ox (V GS−V T )>0

μeff - effective mobility of carriers in the channel (holes in pMOS and electrons in nMOS). According to

the empirical model, for sufficiently small V DS values (namely,

V DS

2<< (V GS−V T )) holds:

μeff =Lgd

WQhole( e )=

μ0

1+θ (V GS−V T ) . Here, θ and μ0 are the mobility degradation factor (see below)

and the surface carrier’ mobility in Si at 300 K (see also below). In the short channel device, μeff is a

function of V GS , while in the long channel devices, examined here, it is assumed to be a constant.

Qhole (e ) mobile dominant carrier’ (hole for pMOS or electron for nMOS) channel charge density [C/cm 2

or C/m2 ]: Qhole (e )=−C ' ox (V GS−V T−

V DS

2 )g

μ0 surface mobility of carriers (holes in pMOS and electrons in nMOS) in Si at 300 K (e.g. for holes

μ0 ~160 [ cm2

Volt⋅sec ])

θ - mobility degradation factor [Volt-1] (θ>0 for nMOSFET, θ<0 for p-MOSFET)1. Theory predicts,

that θ ~ 1

0. 42×tox[ nm ]

V GS ,i - gate-source voltage (expected) intersection with the x-axis (“Gate voltage”) on the graph of IDS=f (V GS ) (transfer characteristics)

List of definitions

Threshold voltage V T - the gate-source voltage at which a transistor starts to conduct.

1 See ref. 11 p.455-456 to get a theoretical value.




Bulk (body)- back contact of a MOSFET also referred to as the substrate contact.

Body effect – normally, the MOSFET body is connected to the lowest voltage potential of the circuit (usually

the source). However if is left unconnected, it affects the threshold voltage V T and I DS (V DS ,V GS ) characteristics of the device. Namely,

V T increases with increasing bulk voltage

for all values of V GS and V DS , body effect reduces I DS

for given V GS , body effect reduces V DS, sat

n + (n - ) semiconductor n-type semiconductor with high donor density (N D≥1019 [cm−3 ] ) and with low

donor density (N D≤1016 [cm−3] ) correspondingly. Here,N D is a donor density.

p + (p - ) semiconductor p-type semiconductor with high acceptor density (N A≥1019 [ cm−3 ] ) and with low

acceptor density (N A≤1016 [cm−3 ] ) correspondingly. Here, N A is an acceptor density.

Mobility - the ratio of the carrier velocity to the applied electric field.

Inversion - change of carrier type in a semiconductor obtained by applying an external voltage. In a MOSFET, inversion creates the free carriers, which cause the drain current. Inversion layer - the layer of free carriers of opposite type at the semiconductor-oxide interface of a MOSFET.

Depletion - removal of free carriers in a semiconductor

Channel length modulation - variation of the channel due to an increase of the depletion region when increasing the drain voltage. A reduction of the channel yields a higher current.

Transfer characteristic - output current of a device plotted as a function of the input voltage.

Transconductance is a ratio of output current variation to the input voltage. Transconductance variation of MOSFET defines its gain. It is proportional to hole (electron) mobility (depend on the device type, pMOS or nMOS), at least for low drain voltages. As MOSFET size is reduced, the fields in the channel increase and the dopant impurity levels increase. Both changes reduce the carrier mobility, and hence the transconductance. As channel lengths are reduced without proportional reduction in drain voltage, raising the electric field in the channel, the result is velocity saturation of the carriers, limiting the current and the transconductance.




Appendix 2 : Teaching chip № 2 details. Chip layout Chip appearance

Photomicrograph of the chip.




Additional details:




Appendix 3 : Kite settings for nMOSFET.

Output characteristics:

Connect pins:

ITM module:


GSDSDS VVI ,



Expected results:

Transfer characteristics: IDS=f(VGS) and Transconductance gm= f(VGS) in the linear region.

ITM module:




Expected results:


Formulas for automatic

differentiation

∂ IDS , lin

∂V GS and

finding V GS ,i



Appendix 4 : Kite settings for pMOSFET.

Output characteristics:

Connect pins:

ITM settings

CAUTION: Do not set values exceeding the assigned values!


GSDSDS VVI ,



Expected results

Transfer characteristics: IDS=f(VGS) and Transconductance gm= f(VGS) in the linear region.




CAUTION: Do not set values exceeding the assigned values!

Expected results




Appendix 5 : expected results of the light influence on the n-MOSFET performances.

Darkness

Moderate lightening

Strong lightening


I DS=40.3003 μAV T=1. 80788 V

I DS=40. 2978×10−6 μAV T=1. 81243 V

I DS=39 .3075 μAV T=2. 41915 V

GND (V=0) of the external source

1817161514131211

chip’ pinssocket’ contacts

Vcc=+10 V from the external source

Keithley SMU 1 (source)

Source

Drain

Gate

Keithley SMU 2 (drain)

Keithley SMU 3 (gate)



Appendix 6 : Pin connections for N1 transistor. Note: Our chip has 16 pins, while the socket of the Test fixture – 18 contacts. Thus, 1-8 pins of the chip correspond to 1-8 contacts of the socket, while 9-16 pins of the chip correspond to 11-18 contacts of the socket.




Bibliography and internet links1. MOSFET at Britannica:

http://www.britannica.com/EBchecked/topic/533976/semiconductor-device/34333/Metal-oxide-semiconductor-field-effect-transistors#ref71251

2. MOSFET at wikipedia: http://en.wikipedia.org/wiki/MOSFET

3. B. Van Zeghbroeck, “Principles of semiconductor devices”, Lectures – Colorado University, 2004.

4. A. Chelly, “MOS – field effect transistor”, Lab manual - Advanced Semiconductor Devices Lab (83-435), School of Engineering of Bar-Ilan University.

5. A. del Alamo. “Integrated microelectronic devices” course (6.720J / 3.43J), lecture 27: “The ”Long” Metal-Oxide-Semiconductor Field-Effect Transistor”, MIT, 2002.

6. B. Streetman, S. Banerjee, “Solid state electronic devices” (6th edition), Prentice Hall, 2005.

7. J. Singh, “Semiconductor devices: basic principles”, Whiley, 2001.

8. MOSFET Simulation using Java Applet:

http://jas2.eng.buffalo.edu/applets/education/mos/mosfet/mosfet.html

9. Gate Dielectric Capacitance-Voltage. Characterization Using the Model 4200: www.keithley.com/data?asset=3580

10. Alan Doolittle. Lectures on course Semiconductor devices: http://users.ece.gatech.edu/~alan/ECE3040/Lectures/Lecture25-MOSTransQuantitativeId-Vd-Vg.pdf

11. D.K. Schroder, "Semiconductor material and device characterization", Chapter 7; Wiley, 1998. Library code: 621.38152 SCHR (advanced level).

12. R. Pierret. Semiconductor Device Fundamentals, Addison-Wesley, 1996


http://users.ece.gatech.edu/~alan/ECE3040/Lectures/Lecture25-MOSTransQuantitativeId-Vd-Vg.pdf

http://users.ece.gatech.edu/~alan/ECE3040/Lectures/Lecture25-MOSTransQuantitativeId-Vd-Vg.pdf

http://jas2.eng.buffalo.edu/applets/education/mos/mosfet/mosfet.html

http://en.wikipedia.org/wiki/MOSFET





Preparation Questions

1. Explain (in short) what is MOSFET transistor and its principles of work.

2. What is the family of the output characteristics I DS= f (V DS ,V GS ) ?3. How can you measure

channel conductance gd in the linear region.

threshold voltage V T .

effective mobility μeff as a function of V GS−V T .

on the basis of the family of the output characteristics I DS= f (V DS ,V GS ) ?

4. What is the transfer characteristics IDS=f (V GS ) and transconductance gm= f (V GS ) ?5. How can you measure

threshold voltage V T

effective mobility μeff .

on the basis of IDS= f (V GS ) and gm= f (V GS ) ?6. Explain (in short), what is the reason for light influence on MOSFET performances.


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