lab manual soen 228

7/25/2019 lab Manual soen 228

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SOEN 228/298 Lab Manual

Author:

Rick Fenster

Last Revision: June 1, 2015

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Contents

1 Introduction 11.1 Representing Binary . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 Commonly Used Parts in the Lab . . . . . . . . . . . . . . . . . . 1

1.2.1 Breadboard . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2.2 Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.2.3 Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.2.4 Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . 31.2.5 LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.2.6 Integrated Circuits . . . . . . . . . . . . . . . . . . . . . . 51.2.7 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . 61.2.8 Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.3 Basic Logic Functions . . . . . . . . . . . . . . . . . . . . . . . . 71.3.1 NOT Function . . . . . . . . . . . . . . . . . . . . . . . . 7

1.3.2 OR Function . . . . . . . . . . . . . . . . . . . . . . . . . 81.3.3 AND Function . . . . . . . . . . . . . . . . . . . . . . . . 9

2 Lab Experiment 0: Introduction to the Breadboard and Elec-

tronic Circuits 10

2.1 Introduction to Lab Experiment 0 . . . . . . . . . . . . . . . . . 102.2 Using the Power Supply . . . . . . . . . . . . . . . . . . . . . . . 102.3 Wiring Switches for Inputs . . . . . . . . . . . . . . . . . . . . . 102.4 The 7404, 7408 and 7432 Integrated Circuits . . . . . . . . . . . 102.5 Step 0: Wiring the Breadboard . . . . . . . . . . . . . . . . . . . 112.6 Step 1: Controlling an LED By a Switch . . . . . . . . . . . . . . 122.7 Step 2: Testing the 7404, 7408 and 7432 . . . . . . . . . . . . . . 12

3 Lab Experiment 1: The Half Adder 133.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133.2 The Half Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133.3 Step 0: Simplify the Function . . . . . . . . . . . . . . . . . . . . 133.4 Step 1: Implement the Circuit . . . . . . . . . . . . . . . . . . . . 13

4 Lab Experiment 2: Latches and Flip-Flops 14

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144.2 The S-R Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144.3 The D Flip-Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . 144.4 Step 0: Assemble the S-R Latch . . . . . . . . . . . . . . . . . . . 154.5 Step 1: Assemble the D Flip-Flop . . . . . . . . . . . . . . . . . . 164.6 *Step 2: Build A Positive-Edge Triggered D Flip-Flop . . . . . . 16

5 Project Experiment 0: The Timing Signal Generator 17

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175.2 Duty Cycle and Frequency . . . . . . . . . . . . . . . . . . . . . . 175.3 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

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5.4 A Review on Orders of Magnitude . . . . . . . . . . . . . . . . . 175.5 The 555 Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.6 The 74LS164 SIPO Shift Register . . . . . . . . . . . . . . . . . . 195.7 Feedback For the Timing Signal Generator . . . . . . . . . . . . 205.8 Assembling the Timing Signal Generator . . . . . . . . . . . . . . 215.9 Some Pro ject Tips . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6 Project Experiment 1: The Bus, Arithmetic Unit and Program

Counter 23

6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236.2 The Data Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236.3 The Program Counter . . . . . . . . . . . . . . . . . . . . . . . . 236.4 The Arithmetic Unit . . . . . . . . . . . . . . . . . . . . . . . . . 246.5 74LS283 4-Bit Adder . . . . . . . . . . . . . . . . . . . . . . . . . 246.6 74LS395 4-Bit Shift Register . . . . . . . . . . . . . . . . . . . . 25

6.7 A Brief Overview on the Program Counter and Incrementer System 266.8 Assembling the Circuit . . . . . . . . . . . . . . . . . . . . . . . . 26

7 Project Experiment 2: Data Registers and the Memory Ad-

dress Register 30

7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307.2 Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307.3 Putting It All Together . . . . . . . . . . . . . . . . . . . . . . . 30

8 Project Experiment 3: Program Memory 32

8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328.2 A Brief Overview on Memory . . . . . . . . . . . . . . . . . . . . 328.3 Decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

8.4 SCM21C14E-4 1K x 4 RAM . . . . . . . . . . . . . . . . . . . . . 338.5 7442 Binary Coded Decimal to Decimal Decoder . . . . . . . . . 348.6 74LS157 Quad Multiplexer . . . . . . . . . . . . . . . . . . . . . 348.7 74LS126 Tri-State Buffer . . . . . . . . . . . . . . . . . . . . . . . 358.8 The Experiment . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

8.8.1 Building the Circuit . . . . . . . . . . . . . . . . . . . . . 368.8.2 Programming the RAM . . . . . . . . . . . . . . . . . . . 368.8.3 Displaying the Contents of the RAM . . . . . . . . . . . . 378.8.4 Demonstrating Your Work . . . . . . . . . . . . . . . . . . 38

9 Project Experiment 4: The Control Signal General 40

9.1 The IncB Instruction . . . . . . . . . . . . . . . . . . . . . . . . . 409.2 The MovAB Instruction . . . . . . . . . . . . . . . . . . . . . . . 40

9.3 The MovBA Instruction . . . . . . . . . . . . . . . . . . . . . . . 419.4 The IncA Instruction . . . . . . . . . . . . . . . . . . . . . . . . . 419.5 Implementing the Signal Generator . . . . . . . . . . . . . . . . . 41

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10 A Note on Circuit Schematics 43

10.1 B lock Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

10.2 Electrical Schematics . . . . . . . . . . . . . . . . . . . . . . . . . 4310.2.1 Using the Right Symbol and Showing Supply Connections 4310.2.2 Part Names and References: Why Do They Matter? . . . 44

11 Using the 74LS173 As a Replacement for the 74LS395 46

List of Figures

1 Breadboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Switch Schematic Symbol . . . . . . . . . . . . . . . . . . . . . . 23 DIP Switch Pack . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Resistor Schematic Symbols . . . . . . . . . . . . . . . . . . . . . 3

5 Resistor Pack Equivalent Circuit . . . . . . . . . . . . . . . . . . 36 Bussed Resistor Pack and Individual Resistor . . . . . . . . . . . 37 Capacitor Schematic Symbols . . . . . . . . . . . . . . . . . . . . 48 Ceramic and Electrolytic Capacitors . . . . . . . . . . . . . . . . 49 LED Schematic Symbol . . . . . . . . . . . . . . . . . . . . . . . 410 LED Pack and Single LED . . . . . . . . . . . . . . . . . . . . . 511 Anode side of LED Pack . . . . . . . . . . . . . . . . . . . . . . . 512 Typical Integrated Circuit . . . . . . . . . . . . . . . . . . . . . . 613 Power Supply Schematic Symbols . . . . . . . . . . . . . . . . . . 614 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615 Lab Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716 NOT Gate Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . 717 OR Gate Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

18 AND Gate Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . 919 Switch with a Pull Down Resistor . . . . . . . . . . . . . . . . . . 1020 7404 Pin-Out Diagram . . . . . . . . . . . . . . . . . . . . . . . . 1121 7408 Pin-Out Diagram . . . . . . . . . . . . . . . . . . . . . . . . 1122 7432 Pin-Out Diagram . . . . . . . . . . . . . . . . . . . . . . . . 1123 Schematic for a Switch Controlled LED . . . . . . . . . . . . . . 1224 NAND S-R Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . 1425 D Flip-Flop Block Diagrams . . . . . . . . . . . . . . . . . . . . . 1526 Level-Triggered D Flip-Flop Implementation . . . . . . . . . . . . 1527 Implementation of a NAND Gate . . . . . . . . . . . . . . . . . . 1628 Implementation of a Positive-Edge Triggered D Flip-Flop . . . . 1629 Sample Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . 1730 555 Timer Pin-Out Diagram . . . . . . . . . . . . . . . . . . . . . 18

31 555 Timer Astable Circuit . . . . . . . . . . . . . . . . . . . . . . 1932 Shift Register Behavior . . . . . . . . . . . . . . . . . . . . . . . 1933 74LS164 Pin-Out Diagram . . . . . . . . . . . . . . . . . . . . . . 2034 7420 Pin-Out Diagram . . . . . . . . . . . . . . . . . . . . . . . . 2035 4 Bit Bus Example . . . . . . . . . . . . . . . . . . . . . . . . . . 24

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36 74LS283 Pin-Out Diagram . . . . . . . . . . . . . . . . . . . . . . 2537 74LS395 Pin-Out Diagram . . . . . . . . . . . . . . . . . . . . . . 25

38 Program Counter Register Schematic . . . . . . . . . . . . . . . . 2739 4-Bit Adder Schematic . . . . . . . . . . . . . . . . . . . . . . . . 2840 Sum Register Schematic . . . . . . . . . . . . . . . . . . . . . . . 2841 Mirror Register Schematic . . . . . . . . . . . . . . . . . . . . . . 2942 Data Register Schematic . . . . . . . . . . . . . . . . . . . . . . . 3143 Memory Address Register Schematic . . . . . . . . . . . . . . . . 3144 SCM21C14E-4 Pin-Out Diagram . . . . . . . . . . . . . . . . . . 3345 7442 Pin-Out Diagram . . . . . . . . . . . . . . . . . . . . . . . . 3546 74LS157 Pin-Out Diagram . . . . . . . . . . . . . . . . . . . . . . 3547 74LS126 Pin-Out Diagram . . . . . . . . . . . . . . . . . . . . . . 3648 RAM Circuit Diagram . . . . . . . . . . . . . . . . . . . . . . . . 3949 Control Signal Generator Logic . . . . . . . . . . . . . . . . . . . 4250 Typical Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 4351 Typical Electrical Schematic . . . . . . . . . . . . . . . . . . . . . 4452 Schematic With Multiple References . . . . . . . . . . . . . . . . 4553 74LS173 Circuit for Replacing The 74LS395 . . . . . . . . . . . . 46

List of Tables

1 Truth Table for the NOT Function . . . . . . . . . . . . . . . . . 82 Truth Table for the OR Function . . . . . . . . . . . . . . . . . . 83 Truth Table for the AND Function . . . . . . . . . . . . . . . . . 94 Truth Table for the Half Adder . . . . . . . . . . . . . . . . . . . 135 Truth Table for the S-R Latch . . . . . . . . . . . . . . . . . . . 146 Truth Table for the D Flip-Flop . . . . . . . . . . . . . . . . . . . 15

7 Orders of Magnitude . . . . . . . . . . . . . . . . . . . . . . . . . 188 Sample Layout of a 32 X 1B Memory . . . . . . . . . . . . . . . . 329 Truth Table for 2 bit Active High and Active Low Decoders . . . 3310 Behavior of SCM21C14E-4 . . . . . . . . . . . . . . . . . . . . . 3411 Truth Table for 7442 Decoder . . . . . . . . . . . . . . . . . . . . 34

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1 Introduction

The purpose of this laboratory is to introduce students to digital logic andcomputer architecture at a physical level. Students will prototype and testcircuits that will form a basic, toy computer capable of executing a few selectedinstructions by using TTL integrated circuits. In particular, this lab makes useof the 7400 logic family.

The first set of lab experiments serve to provide some familiarization andexploration with digital logic. Once a comfortable working knowledge of digitallogic has been established, a simple computer is built through 5 experiments.This computer contains the majority of the basics needed for a computer: aprogram counter, memory, registers, a data bus and a control signal generator.

This lab experiment computer has the following specifications: a clock ofapproximately 3.25 Hz, two 4-bit general purpose data registers, an incrementer,16 X 4 bit instruction memory and three instructions.

1.1 Representing Binary

Binary systems have two values of concern: Logic 0 and Logic 1. Since thislaboratory uses TTL technologies, a Logic 0 is considered to be 0 Volts (Groundor GND) and a Logic 1 is considered to be 5 Volts.

1.2 Commonly Used Parts in the Lab

1.2.1 Breadboard

The breadboard is a tool used to prototype and assemble digital circuits. It isdesigned to intentionally slot integrated circuits with ease. Please see Figure 1

below. In the center, the gap is used to isolate the columns. For every column,there is a metal plate running down. These metal plates stop at the gap inthe breadboard. Because of this, each connector in a particular column forms aparallel connection. The only exceptions to this are the two sets of rows on thetop and bottom of a breadboard. Each one of these rows has all of its socketsconnected together and called rails. This characteristic makes these two rowsideal for +5 Volts and Ground.

Figure 1: Breadboard

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1.2.2 Switches

The switches used in these labs are single-pole, single throw switches (SPST).When the switch isclosed, it forms a connection and when open, the connectionis broken. In the lab, switches come in packs of 8, 10 or 12 and are placed inthe gaps of the breadboards. A 12 pack switch is shown in Figure 3. The circuitsymbol for a SPST is shown in Figure 2.

Figure 2: Switch Schematic Symbol

Figure 3: DIP Switch Pack

1.2.3 Resistors

A resistor is a basic component for any electrical circuit. It simply resistselectrical current. The resistance of a resistor is measured in Ohms ( ).In these experiments, a resistor is used for two purposes. The first is to actas a pull-down resistor for inputs and data lines, meaning that the resistor isconnected to Ground. The other reason is to limit the flow of current for LEDs

so that the LEDs do not burn out. Two common resistor symbols are shown inFigure 4.There are two packages available for use in the SOEN 228/289 labs. The first

type is an individual resistor, used primarily in the Timing Signal Generator.The other type is a resistor pack, which contains multiple resistors in one unit.The resistor packs used in the lab are all tied to a common pin which makes these

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Figure 4: Resistor Schematic Symbols

resistors ideal for use with switch or LED packs since only one wire is necessaryto tie them to VCC or Ground. Common pins are usually an outermost pindenoted by a strip or a dot on one end of the resistor pack to show which sidethe pin is on. A typical resistor pack of 4 resistors is equivalent to the circuitshown in Figure 5. Actual resistors are shown in Figure 6. A bussed resistorpack is shown on the left with its common pin emphasized and a single resistoris shown on the right.

Figure 5: Resistor Pack Equivalent Circuit

Figure 6: Bussed Resistor Pack and Individual Resistor

1.2.4 Capacitors

A capacitor is a device that stores electrical charges then discharges them. Inthis lab, capacitors are only used during the Timing Signal Generator experi-ment. There are two types of capacitors presented to students. The first type

is a ceramic capacitor which is a capacitor that can be placed in any direction.On the other hand, electrolytic capacitors are polarized and must be pluggedin with the longer leg being a positive side. Its unit is the Farad (F). Figure 7shows the circuit schematic symbol for the capacitor.

In Figure 8, a ceramic capacitor is shown on the left and an electrolyticcapacitor on the right. Take note of the longer leg on the electrolytic capacitor.

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This is due to the fact that it is polarized and must be connected to the positiveside.

Figure 7: Capacitor Schematic Symbols

Figure 8: Ceramic and Electrolytic Capacitors

1.2.5 LEDs

A light emitting diode is a a device that emits light when a current is passedthrough. The brightness of the device is proportional to the amount of current.Because of this, an LED must be wired in series with a resistor to ensure thatthe LED will not burn out. The position in which the LED is plugged in doesmatter. The positive end, also known as the anode must be connected to agreater voltage than the negative part called a cathode. In Figure 9, the circuitschematic symbol for an LED is shown. Pin 1 designates the anode, while pin2 designates the cathode.

Figure 9: LED Schematic Symbol

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In this lab, two types of LEDs are available. The first type is a LED packwhich has multiple LEDs in one package that is designed to conveniently fit

the breadboard. The other is a standard hole-through package. The anodeis marked on the LED pack by having text (see Figure 11, while the hole-through LED has its anode designated by the longer leg. Typically, the packagetype is used in the lab experiments due to convenience. The cathode is usuallyconnected to a resistor and then to ground. Figure 10 presents the two types ofLEDs available. An LED pack is on the left side and individual LED is on theright.

Figure 10: LED Pack and Single LED

Figure 11: Anode side of LED Pack

1.2.6 Integrated Circuits

An integrated circuit (IC or informally, chip) is a device that provides somefunctionality. These devices come in many shapes and forms. In these labexperiments, the dual inline package (DIP) format is used since these devicesconveniently fit onto the breadboard. Every IC must have its supply pins con-nected to power the device. In these labs, VCC (5 Volts) and Ground must beconnected to the device at the designated pins. A typical 14 pin IC is presentedin Figure 12. There is usually a plastic indent to visualize the alignment of theintegrated circuit and should be referenced when placing the integrated circuitonto the breadboard.

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Figure 12: Typical Integrated Circuit

1.2.7 Power Supply

A power supply provides the power needed for the circuit. The red connectordenotes VCC (5 Volts) and Ground (0 Volts) is denoted by the black connector.This colour scheme is a typical method of colour-coding wires and is suggestedfor use during the labs. The power supplies available in the lab are shown inFigure 14. In this case, the dedicated 5 Volt and Ground channel on the farright is used. The symbols for VCC and Ground are shown in Figure 13. Notethat there are different symbols for showing VCC.

Figure 13: Power Supply Schematic Symbols

Figure 14: Power Supply

1.2.8 Tools

In the lab, there are two tools that will be used. The first is a wire cutter andstripper. It is used to cut wire and strip the plastic insulation around the wireto expose the metal for inserting into the breadboard. The other tool is an IC

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Puller, which is used for the extraction and removal of integrated circuits whenplaced on the breadboard. These tools are shown in Figure 15.

Figure 15: Lab Tools

1.3 Basic Logic Functions

In a digital system, any digital logic function can be expressed by using threefundamental functions. These functions are AND, NOT and OR and corre-spond with their equivalent functions in a discrete mathematics course. Eachof these functions have multiple inputs but only one output. Their behavioursare described intruth tableswhich contain every possible combination of inputsand their respective outputs. If a logic function has n inputs, it will have 2n

possible combinations.

1.3.1 NOT Function

The NOT function is the simplest basic logic function. It has a single input andsimply inverts it. This function can be described by the following equation:

F =X

The behaviour of the function is shown in Table 1. In the SOEN 228/298 labs,the7404 IC is used to provide inverters that perform this function. The symbolfor the NOT Gate is shown in Figure 16. The wire cutter/stripper is on theright and the IC puller is on the left.

Figure 16: NOT Gate Symbol

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X F

0 11 0

Table 1: Truth Table for the NOT Function

1.3.2 OR Function

The OR function can be described as if any of the inputs are equal to a Logic1, the output will also be a Logic 1. It can be written as the equation

F =A + B

The OR function is provided by the7432IC. The truth table for the OR function

is shown in Table 2. The symbol for the OR gate is shown in Figure 17.

A B F

0 0 00 1 11 0 11 1 1

Table 2: Truth Table for the OR Function

Figure 17: OR Gate Symbol

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1.3.3 AND Function

The AND function behaves in such a way that the output is equal to a Logic1 if and only if, all the inputs are equal to a Logic 1. The OR function can bedescribed as if any of the inputs are equal to a Logic 1, the output will also bea Logic 1. It can be written as the equations F=A B or F =AB

The AND gate symbol is shown in Figure 18 and the truth table for theAND function is shown in Table 3. In the SOEN 228/298 lab experiments, theAND function is provided by the7408 integrated circuit.

A B F

0 0 00 1 01 0 0

1 1 1

Table 3: Truth Table for the AND Function

Figure 18: AND Gate Symbol

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2 Lab Experiment 0: Introduction to the Bread-

board and Electronic Circuits2.1 Introduction to Lab Experiment 0

The goal of this lab experiment is to become familiar with using the breadboard,integrated circuits, LEDs, power supplies, resistors and switches.

2.2 Using the Power Supply

To supply power to the breadboard, use the dedicated 5V channel and Groundon the far right of the power supply. When modifying a circuit, it is importantto not perform modifications on your circuit while the power supply is on!

2.3 Wiring Switches for InputsTo safely provide proper inputs, we must ensure that the input pin of a devicegets a steady Logic 0 or Logic 1. This is done by wiring a switch in a mannerthat uses a pull down resistor. A pull down resistor serves as a method tocontrol the current flowing through a device. This is the reason why LEDsrequire resistors in series. If the switch is open, the input pin has a resistorand Ground connected which leads to 0 Volts. When the switch is closed, aconnection to VCC is formed so that the input pin can receive 5 Volts withouta short circuit. The implementation of this is shown in Figure 19.

Figure 19: Switch with a Pull Down Resistor

2.4 The 7404, 7408 and 7432 Integrated Circuits

In this lab experiment, the student must verify the truth tables of the three basicdigital logic functions. These logic functions are performed by gates contained

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on integrated circuits. The 7404 is an integrated circuit that provides 6 NOTgates, 4 AND gates are provided on the 7408 and lastly, 4 OR gates are built

into the 7432. Each integrated circuit has its own layout of what pins servewhat function. To know what each pin does, a pin-out diagram provides thelayout of the integrated circuit in question. The pin-out diagrams for the 7404,7408 and 7432 are shown in Figures 20, 21 and 22.

Figure 20: 7404 Pin-Out Diagram



2.5 Step 0: Wiring the Breadboard

Before any circuit can be constructed, the breadboard must first be wired prop-erly to ensure that all the rails are powered. Wire each red rail to VCCand eachblue rail to Ground.

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2.6 Step 1: Controlling an LED By a Switch

The first portion of the lab experiment is to wire an LED controlled by a switch.When the switch is closed, the LED should be powered. The circuit is providedin Figure 23. Take special notice of how the LED is wired in the schematic.Make sure the anode is wired to VCCand the needed resistor is placed in thecircuit.

Figure 23: Schematic for a Switch Controlled LED

2.7 Step 2: Testing the 7404, 7408 and 7432

In this portion of the lab experiment, the truth tables for NOT, AND and ORfunctions are to be checked. Outputs are to be driven by LEDs so that when theoutput is a Logic 1, the LED is on and offwhen the output is a Logic 0. Remem-ber to wire VCC and Ground correctly! Ask your lab demonstrator to verifybefore powering on the circuit. Note: For more information on drawing logicdiagrams and schematics, please see the section A Note on Circuit Schematics.

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3 Lab Experiment 1: The Half Adder

3.1 Introduction

In this lab experiment, a simple combinational circuit is to be designed andassembled from the basic three gates. A combinational circuit is a circuit thathas an output affected by inputs. If a combinational circuit has n inputs, thenit has up to 2n possible scenarios to provide outputs. There is no memory inthese circuits to use when producing the output.

3.2 The Half Adder

The circuit in question is a half adder, a simple circuit that can add up to two.It has two inputs, A and B, and two outputs, sum and carry out. The truthtable for a half adder is shown in Table 4.

A B Carry Out Sum

0 0 0 00 1 0 11 0 0 11 1 1 0

Table 4: Truth Table for the Half Adder

3.3 Step 0: Simplify the Function

The first step of this experiment is to simplify the circuit in such a manner thatit can be implemented by using only the 7404, 7408 and 7432. This circuit onlyrequires one IC of each type.

3.4 Step 1: Implement the Circuit

This portion of the lab experiment is to build the actual circuit. Show yourlab demonstrator your functioning circuit. The inputs must be controlled byswitches and outputs must drive LEDs.

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4 Lab Experiment 2: Latches and Flip-Flops

4.1 Introduction

This lab experiment is about sequential circuits. A sequential circuit differsfrom a combinational circuit since it has memory. The two primitive types ofmemory elements are to be built: a latch and a flip-fop. A latch immediatelyresponds to its inputs, while a flip-flop requires an enable of sorts.

4.2 The S-R Latch

The S-R Latch is the most basic form of memory element possible. It can bebuilt multiple ways but in this lab, the NAND implementation is chosen andshown in Figure 24. The output Q is the data output of the memory. Thebehavior of this S-R Latch is shown in Table 5. When Sand R are both equal

to a Logic 0, the latch enters an undesirable, indeterminate state.

Figure 24: NAND S-R Latch

S R Q Q

0 0 Invalid State0 1 1 01 0 0 11 1 No Change

Table 5: Truth Table for the S-R Latch

4.3 The D Flip-Flop

The S-R Latch can be improved upon. By adding a few components, a D Flip

Flop can be formed. The advantages of the D Flip-Flop is that it is easier tohandle with only one data input and it does not allow for the flip-flop to enterthe indeterminate state. Additionally, an enable input is also placed onto theflip-flop. The behaviour is detailed in Table 6.

There are two ways a Flip-flop can respond to the enable input. The firstway is called level triggered. When the enable signal is asserted, the data can

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D E Q Q

X 0 No Change0 1 0 11 1 1 0

Table 6: Truth Table for the D Flip-Flop

be changed. The other method is called edge triggered and is when the flip-flopresponds to the change in the enable signal. When the flip-flop is triggered bythe enable going high to low, the flip-flop is said to be negative-edge triggered. Ifthe flip-flop is triggered by the enable signal going high, it is called positive-edgetriggered. An edge-triggered flip-flop is far more desirable due to the change indata being nearly instantaneous, while the level-triggered flip-flop provides an

opportunity to have data modified. A block diagram of the level triggered DFlip-Flops is shown in Figure 25. On the left is an edge-triggered flip-flop andon the right is a level-triggered flip-flop. Figure 26 details the implementationof the level-triggered D Flip-Flop.

Figure 25: D Flip-Flop Block Diagrams

Figure 26: Level-Triggered D Flip-Flop Implementation

4.4 Step 0: Assemble the S-R Latch

The first step in this lab experiment is to assemble the S-R latch. Since NANDgates are not available, an equivalent circuit can be made by using an AND

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gate with a NOT gate connected to its output. An example of this is shown inFigure 27. Show your lab demonstrator the functioning circuit.

Figure 27: Implementation of a NAND Gate

4.5 Step 1: Assemble the D Flip-Flop

Once the S-R latch has been built and verified, it is time to build the D flip-flop.The variant implemented is a level-triggered flip-flop as seen in Figure 26. Whendone, show your lab demonstrator the functioning circuit.

4.6 *Step 2: Build A Positive-Edge Triggered D Flip-Flop

If there is time remaining in the lab period, a positive-edge triggered D flip-flopcan be built from two level-triggered D flip-flops. A block diagram is shown inFigure 28. If the inverter was moved so that the enable was inverted on theleftmost D flip-flop, it would act as a negative-edge triggered D flip-flop. Thismethod is called themaster-slaveimplementation.

Figure 28: Implementation of a Positive-Edge Triggered D Flip-Flop

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5 Project Experiment 0: The Timing Signal Gen-

erator5.1 Introduction

In this project experiment, the timing signal generator is built. This is essen-tial for the project since the timing signal generator produces the clock signal,important enable signals and will dictate how fast the computer will function.Before demonstrating the circuit, a few definitions and devices must be reviewed.

5.2 Duty Cycle and Frequency

The first term that is of interest is frequency. Frequency is how fast somethingmay alternate or repeat. It is measured in Hz and is defined as

fs= 1Ts

Ts is the period (in seconds) of how long the signal lasts until it is repeated.To calculate the duty cycle, use the following equation where t is the amount oftime that the signal is set to a logic 1:

DC= t

Ts

5.3 Timing Diagrams

A timing diagram is a useful tool to determine how a system may operate whensignals are bound to change. It is simply composed of a time axis and all the

signals of concern. Figure 29 demonstrates how the duty cycle and period maylook on a timing diagram. In this example, the frequency is 50 MHz (whichgives a timescale in nanoseconds). The period is found to be 20 ns. If we wereto use the frequency equation, it can easily be seen that the frequency is in fact50 MHz.

Figure 29: Sample Timing Diagram

5.4 A Review on Orders of Magnitude

Before proceeding further, a review on orders of magnitude is necessary. Table 7displays the orders of magnitude to be mindful of.

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Order of Magnitude Prefix

109

Giga (G)106 Mega (M)103 Kilo (K)

103 Milli (m)106 Micro ()109 Nano (n)

Table 7: Orders of Magnitude

5.5 The 555 Timer

At the core of the Timing Signal Generator circuit, a versatile integrated circuitcalled the 555 Timer is used. The 555 differs from all the integrated circuits

used at this point since it is an 8 pin device. This device has many modes ofoperation but in this lab, it is only used in astablemode so that it can providea signal that alternates between a logic 0 and logic 1 as seen in Figure 29. Thepin-out diagram for the 555 timer is shown in Figure 30.

Figure 30: 555 Timer Pin-Out Diagram

Like any integrated circuit used in this lab, the VCC and GND pins must beconnected for the device to operate. Another thing worth noting is that the 4thpin is a reset pin. To reset the 555 timer, RSTmust be a logic 0 so to preventthe device from constantly resetting, it is wired directly to VCC. The clock pulseis generated by using an RC (resistor and capacitor) circuit and measuring itsvoltage. This RC circuit constantly charges and discharges. Inside the 555 timeris a flip flop which switches value when the voltage in the RC circuit reaches13 VCC or 23 VCC. The value at the output of the timer is the value of the flipflop. To build a clock signal generator, the frequency and the duty cycle mustbe known. Two equations are used for determining these values. To determine

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the frequency, the following equation is used:

fs= 1

Ts= 1.44

(R1+ 2R2)C2

To determine the duty cycle, the following equation can be used:

D= R2

R1+ 2R2

Figure below shows a typical astable circuit with the output of the timer calledCLK (Clock). Note how pin 4, the reset pin, is wired to VCC. The capacitorC1 is optional but desirable to have because it can reduce noise. Even thoughpin 1 and 8 are not shown, they are wired to their respective VCC and Groundrails.

Figure 31: 555 Timer Astable Circuit

5.6 The 74LS164 SIPO Shift Register

The other integrated circuit of interest in this lab experiment is the 74LS164SIPO (Serial In, Parallel Out) Shift Register. This device takes an input andshifts all the contents by one output every clock cycle. It has 8 outputs whichcan all be accessed at any time but only one input. A shift register moves valuesfrom one internal flip flop to the next. The 74LS164 moves values from QA toQH. A graph showing this behavior for a 4 bit SIPO shift register is seen inFigure 32. The pin-out diagram for the 74LS164 is shown in Figure 33.

Figure 32: Shift Register Behavior

To wire the 74LS164 correctly, pin 14 must be wired to VCC and pin 7 toGround. The outputs are the pins that correspond to QA to QH where QA isthe first output stage. It should also be noted that the values from these pins

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Figure 33: 74LS164 Pin-Out Diagram

are denoted by T0 to T7. Pin 9 is used to clear the register. It is triggered whenthe input is a logic 0 in a similar manner as the 555 timer reset pin and must

be wired to VCC to not reset continuously. The input to the register is A B.With this in mind, if A = 1 and B = 0, the next value taken into the registerwill be a 0. When the device is powered on, all internal flip-flops are set to 0and when the CLR pin is triggered, the device is returned to this state.

5.7 Feedback For the Timing Signal Generator

The last thing necessary for the timing signal generator is feedback. The 555timer provides a clock which is fed into the shift register but now the inputsto the shift register need to be determined. Feedback is taken from the shiftregister and fed to a 4 input NAND gate (7420 IC). The output of this NANDgate is supplied to pins 1 and 2 of the 74LS164. By doing so, the input to theshift register will in fact be the output of the NAND gate Y =Y Y. The inputs

of the NAND gate are taken from QB, QD, QF and QG. Figure 34 provides thepin-out diagram for the 7420 Quad Input NAND Gate.


When the timing signal generator is powered on, all outputs are set to 0.Due to the feedback provided by the 7420, this will place a logic 1 at the shiftregister input for the next clock cycle. After several clock cycles, the shift

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registers outputs will all be set to logic 1. At this point, the input to theregister will become a 0. A pulse of two logic 0 values will circulate through the

shift registers outputs from this point onward. Since all the registers used onthe computer use an active low Enablesignal, this pulse will trigger the enableinputs or outputs on these registers.

5.8 Assembling the Timing Signal Generator

The first portion in assembling the timing signal generator is to build the circuitin Figure 31. Your lab instructor will provide the values of the resistors andcapacitors used for the timing circuit. Wire an LED to pin 3 of the 555 timerIC. This will provide a visual representation of the clock signal generated byyour circuit. It is suggested that you do not remove this LED for the remainderof the project.

Build the circuit in Figure 3. Your lab instructor will provide you withthe values used for the capacitor and resistors. Connect an LED to pin 3of the 555 timer. This will provide you with a visualization of the clocksignal. It is suggested that you keep this LED for the remainder of theproject to help with troubleshooting.

Assemble the shift register and feedback circuit.

Wire up the 74LS164 and 7420 ICs by connecting VCC and GND

Take the outputs QB, QD, QF and QG of the 74LS164 and connect themto the inputs of a NAND gate provided by the 7420

Connect the output of the NAND gate to the inputs of the 74LS164

Connect the clock generated by the 555 timer to the 74LS164

Wire the outputs of the 74LS164 to LEDs

5.9 Some Project Tips

Use a colour scheme: Red wires should be used for VCC, black wires forGND. Any other colours used is up to the students to decide. Remainingconsistent with colour choices will make the project easier to troubleshoot.

Use short wires: Longer wires may make things more difficult to trou-bleshoot. Longer wires can get in the way during troubleshooting andbecome harder to trace.

Maximize your space: Maximizing your space will go a long way. If youdecide to spread things out, you may run out of space on your breadboardand have to redo your work to create space for other parts of the project.

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Beware of exposed wire: When stripping wire, sometimes too much metalcan be exposed. If you use a wire with a substantial amount of metal ex-

posed, be careful that the metal does not make contact with other exposedwires. If this happens, your circuit may not function as desired despite itbeing wired correctly. Additionally, later on in the project, too much ex-posed wire can lead to unusual behaviour in your circuit due to magneticfields. Remove just enough of the coating to get a good connection intothe breadboard.

LEDs can be used to troubleshoot: An LED can be a useful tool to trou-bleshoot a circuit that may not function properly. By using an LED and along wire, a student can determine the logic value at any point in a circuitif the LED turns on.

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6 Project Experiment 1: The Bus, Arithmetic

Unit and Program Counter6.1 Introduction

This lab focuses around building the bus of the computer and implementingseveral crucial components of the computer, namely the arithmetic unit andprogram counter. Four integrated circuits are used for this experiment, three74LS395 4-bit shift registers and a 74LS283 4-bit adder. Before continuing anyfurther, let us focus on what a bus is and why it is of concern.

6.2 The Data Bus

A bus is a series of wires that numerous devices are connected to. Instead ofpatching numerous cables on a breadboard or traces on a circuit board, a set ofwires is used for multiple devices to pass data through. If multiple devices areconnected onto a bus, a major concern is how can the devices be controlled sothat they do not process the data when needed? In the case of the SOEN228lab, this is handled by the timing signal generator built in the previous lab. Asan example, assume that a 4 bit bus is needed for a project on a breadboard.To implement it, each row can be lengthened beyond the gaps on a breadboardby running one wire and connecting it to the next row. By doing this, long rowscan be linked with the same logic value and can be used to connect differentdevices. This can be visualized in Figure 35. For this experiment, the bus lanesare B3 to B0, going from left to right.

An advantage of using a bus is that devices have a centralized point in whichthey can communicate without patching numerous cables in many directions.

The two components being built in this lab use the bus to communicate. Inthis lab experiment, a four bit bus similar to what is shown in Figure 35 isconstructed. The program counter and arithmetic unit are connected to thisbus and communicate through it. These devices are controlled by the timingsignal generator built previously. The first four pulses of the instruction cycleare used: T0, T1, T2 and T3.

When dealing with numerous devices on a bus, some method is needed sothat the devices on the bus that output data do not interfere with each other.The shift registers used in this lab experiment have tri-state outputs. This meansthat they can output a logic 0, logic 1 or a high-impedance value (also knownas a High-Z). When these devices are outputting a High-Z, they effectively haveno output on the bus. This is used so that devices can share the bus withouthaving multiple devices try and output their data at the same time.

6.3 The Program Counter

The Program Counter of a computer is an essential register. It holds the locationof the instruction to be executed. During the execution cycle, the programcounter is incremented through the bus so that the next instruction can be read

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Figure 35: 4 Bit Bus Example

when needed. It can be envisioned as a bookmark used to keep the place in arather large book. It is implemented by using a 74LS395 shift register. Sincethe 74LS395 is a four bit shift register, the computer will have a total of 16available instructions before it rolls over back to 0000.

6.4 The Arithmetic UnitThe arithmetic unit provides the ability to increment the program counter.Without this, the computer would just execute a single instruction and wouldnot be of much use. The arithmetic unit is created by using a 74LS395 shiftregister and a 74LS283 4-bit adder. The inputs of the adder are taken from thebus, the output is fed to the inputs of the 74LS395 belonging to the arithmeticunit. The outputs of the 74LS395 are fed to the bus as well. Since the 74LS395has the ability to control the state of its outputs, the Timing Signal Generatoris used to ensure that only one shift register is outputting data at a time.Ultimately, this allows the program counter to increment itself and allow thecomputer to run any program provided. Additionally, the arithmetic unit isused as the incrementer when the IncB instruction is executed (more on that ina later project experiment).

6.5 74LS283 4-Bit Adder

The 74LS283 is a 4-bit adder in a 16 pin package. The pin-out diagram is shownin Figure 36. Pin 16 must be wired to VCC and Pin 8 must be wired to GND.

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The pins labeled S0, S1, S2 and S3 are the sum outputs, X0 to X3 are one set ofinputs and Y0 to Y3 are the other input. For this lab, the inputs Y0 to Y3 are

grounded while pin 7, the carry in is wired to VCC. Inputs X0 to X3 is takenfrom the bus. By doing this, the sum will always be P C= P C+ 1.


6.6 74LS395 4-Bit Shift Register

The 74LS395 is a 4-Bit Shift Register. In this case, it will be used as a regularregister with its shifting ability disabled. The pin out diagram can be seen inFigure 37. Each Pn pin can be seen as an input for a D flip-flop, while eachQn pin can be seen as the output for the flip-flop. The master reset pin is tiedto VCC to prevent the register from resetting. Pin 7 serves as a control modefor parallel loading or shifting and is set to VCC as well so that the register willdo parallel loads. In case there are no 74LS395s left, consult the section called

Using the 74LS173 As A Replacement for the 74LS395


Once again, pin 16 must be wired to VCC and pin 8 to ground. The clockfor this register to update is negative edged which works with the timing signalgenerator built in the previous lab. Pin 7 is wired to VCC so that the register

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will simply load all the data at once. Because of this, pin 2 is wired to GNDin this lab. Pin 1 is also wired to VCC except for the case where the register

needs to be reset. At that point, the wire attached to pin 1 can be bridgedto GND momentarily. Additionally, the output is controlled by an active lowinput. When pin 9 is set to logic 1, the outputs are high impedance.

6.7 A Brief Overview on the Program Counter and Incre-menter System

Each of the shift registers use one the first four clock pulses generated by the74LS164: T0, T1, T2 and T3. When T0 becomes active, the program counterregister outputs (the address of the current instruction) its contents onto thebus. The value flows into the 74LS283 4-bit adder and is incremented by 1.T1 becomes active and the SUM register stores the data. Afterwards, when T2becomes active, the output of the SUM register becomes available on the bus.The last step in the cycle is when T3 becomes active and causes the PC registerto write the incremented value. The end result of this cycle can be expressedas X = X + 1. Once the register reaches 1111, it will roll over to 0000 andrepeat the cycle. A third register is placed on the bus to be used as a tool tomirror any register. It must use the same timing signal of the register intendedto be mirrored for it to work. The outputs are wired to LEDs and the inputsare taken from the bus.

6.8 Assembling the Circuit

This portion of the computer makes use of the Timing Signal Generator and itsfirst four pulses, T0 to T3. The wiring is presented on the following pages in

Figures 38, 39, 40 and 41. It is up to the student to determine what referenceeach register and part is. The first signal, T0, triggers the output of the programcounter. It will be wired to the connection called PCout. T1 triggers the inputsof the SUM register so it will be connected to SUM inrespectfully. T2triggers theoutput of the SUM register, so it will be wired to SUMoutand lastly, T3triggersthe input of the program register so it will be wired to PCin. Additionally, theoutput enable on the mirror register is tied to Ground so that it will alwaysoutput the contents to a set of LEDs, making it useful for a debugging tool.

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Figure 38: Program Counter Register Schematic

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Figure 39: 4-Bit Adder Schematic

Figure 40: Sum Register Schematic

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Figure 41: Mirror Register Schematic

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7 Project Experiment 2: Data Registers and the

Memory Address Register7.1 Introduction

In this lab experiment, the data registers for the processor and the memoryaddress register are placed into the circuit. It is necessary that the bus andtiming signal generator have been produced at this point since these registers aredependent on the timing signal generator and bus. Before continuing onward,let us define what purpose the data registers and memory address register serve.

7.2 Data Registers

A data register is a memory storage device that holds data. For the purpose ofthe lab, these registers serve as storage devices for the processor. Data registersare necessary because generally manipulating contents of memory is slow or thecomputer is not able to do so. The ability to do so is referred to as DMA, directmemory access.

7.3 Putting It All Together

In this lab experiment, the 74LS395 shift register is used for the three registersneeded in this experiment. This is essential because the three registers discusseddo need to use the bus. The 74LS395 has tri-state outputs which make itdesirable for use with a bus. When the output enable of the 74LS395 (pin 9,see Figure 37) is a logic 1, the outputs are disconnected from the bus by usingthe high-impedance mode (Hi-Z). Three registers are needed for this portion ofthe project: data registers A, B and the memory address register.

The data registers at this point in time are wired to have both their inputsand outputs wired to the bus but their output enable and clock pins are to betied to VCC to disable the inputs and outputs. The MAR is wired differently.A memory address registers purpose is to constantly provide the address ofthe RAM used for the instruction. Because of this, the register must obtainits contents from the bus when the Program Counter register outputs its value.The output enable pin is wired to ground to ensure that it will always output.For now, the outputs are wired to LEDs to demonstrate that the register works.In the forthcoming parts of the project, the outputs of this register will be wiredto the address line inputs of the memory. The clock for the MAR should bewired to T1. This is done so that the MAR has the address of the memory forthe complete duration of the instruction execution.

Many of these connections are temporary and will be modified in the future.The enables on the data registers will eventually be wired so that they canfunction with the Control Signal Generator seen in Project Experiment 4. TheMAR is wired to LEDs to display its contents and verify that it does in factwork. In the next experiment, the outputs of the MAR are wired so that it canprovide the address necessary for the RAM.

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The functionality of these registers must be shown to the lab demonstrator.The timing signals produced by the Timing Signal Generator are to be used to

demonstrate that they are wired correctly. Whichever timing signals used toshow the functionality is up to the student to determine. Because of this, it iscritical that the previous lab experiments have been completed with successfulresults. A sample of how the data registers are intended to be wired is shownin Figure 42, while the wiring for the MAR is shown in Figure 43.

Figure 42: Data Register Schematic

Figure 43: Memory Address Register Schematic

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8 Project Experiment 3: Program Memory

8.1 Introduction

In this experiment, the program memory and its supporting circuit is wiredup and tested. Before delving into the details of how the computer makes useof these hardware components, a brief review of memory, tri-state buffers anddecoders will be presented.

8.2 A Brief Overview on Memory

Memory is a storage device conceived for the storing of multiple bits. Whilethe different types of memories will not be discussed here, the basics of howa memory is structured will be mentioned. For the experiments in this lab,Random Access Memory (RAM) is used. This implies that the memory is not

accessed in a sequential manner like traversing addresses (starting from address0 to address 1 to address 2 and so on until the desired location has been reached)but rather, the contents of a cell can be read or written by provided an address.This behaviour is similar to an array when programming. In this lab, the twoproperties of memory to be concerned with are the number of cells and the sizeof data they can hold. To read or write a cells contents, the address must beprovided. The number of addresses available are 2n where n is the number ofaddress lines available. As an example, if a memory has 5 address lines then ithas 25 or 32 addresses. Now, let us assume this memory holds a total of 8 bits(1 byte) in each cell. We can then say that this is a 32x1B memory or a 32Bmemory. An example of this memory and its contents is shown in Table 8.Notethat b denotes bits, while B denotes bytes. A 4Mb memory means4 220 bits,while a 4MB memory means4 220 bytes.

Address D7 D6 D5 D4 D3 D2 D1 D0

00000 (0x00) 0 1 1 1 0 0 0 000001 (0x01) 1 0 1 0 0 1 0 100010 (0x02) 1 1 1 0 0 1 0 100011 (0x03) 0 0 1 0 1 1 0 100100 (0x04) 1 1 1 1 0 1 0 1

... ...11111 (0x1F) 0 0 1 1 1 1 0 1

Table 8: Sample Layout of a 32 X 1B Memory

8.3 Decoders

A decoder is a combinational circuit that takes m inputs and sets the one outputthat corresponds with the numerical value in binary as active. It produces anoutput in the form of one-hot. This implies that if a 3 bit decoder is active

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high, a valid output would be 0b00100000 or 0b1101111 if it is active low. Thecomplete truth table for a 2 bit decoder is shown in Table 9.

Input Active High Active Low

00 1 0 0 0 0 1 1 101 0 1 0 0 1 0 1 110 0 0 1 0 1 1 0 111 0 0 0 1 1 1 1 0

Table 9: Truth Table for 2 bit Active High and Active Low Decoders

8.4 SCM21C14E-4 1K x 4 RAM

The SCM21C14E-4 is the memory used in the SOEN228 Lab. It is a 1K X 4RAM. This implies that it holds a total of 4096 bits with 4 bits per cell. It has10 address lines and therefore also has a total of 1024 addresses. A total of 18pins are found on the SCM21C14E-4. Pin 18 is VCC and pin 9 is GND, andboth must be connected. To read from and write to the device, pins 11 to 14 areI/O pins which serve the purpose of both reading and writing memory. Thereare two control pins on the SCM21C14E-4. The first pin is the chip select onpin 8. It is an active low input. When Pin 8 is set to logic 1, the I/O pins areset to a high impedance (High-Z) mode. When pin 8 is set to logic 0, the chipis enabled and the I/O pins are no longer in the high impedance state. Thedevices behaviour is dictated by pin 10when enabled. Pin 10 is known as thewrite enable. It is also active low and controls the I/O pins if pin 8 is logic 0as well. When pin 10 is given a logic 1 value, the I/O pins output the data at

the location provided by the address pins. If pin 10 is given a logic 0, the dataon the I/O pins is written to the address provided by the address pins. Thisis summarized in Table 10. The pin layout is shown in Figure 44. Note: ThisRAM is volatile, it does not store its contents when powered down.

Figure 44: SCM21C14E-4 Pin-Out Diagram

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CE W E I/O Pin Behavior

0 0 Write Contents to Address0 1 Output Contents at Address1 X High Impedance Mode

Table 10: Behavior of SCM21C14E-4

8.5 7442 Binary Coded Decimal to Decimal Decoder

The 7442 decoder is a 4 input, 10 output active low decoder. For any inputgreater than 9 or 0b1001 the value across all outputs will be a logic 1 sincethere are no outputs corresponding with any inputs greater than 9. The truthtable for the 7442 is shown below in Table 11.

I3 I2 I1 I0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9

0 0 0 0 0 1 1 1 1 1 1 1 1 10 0 0 1 1 0 1 1 1 1 1 1 1 10 0 1 0 1 1 0 1 1 1 1 1 1 10 0 1 1 1 1 1 0 1 1 1 1 1 10 1 0 0 1 1 1 1 0 1 1 1 1 10 1 0 1 1 1 1 1 1 0 1 1 1 10 1 1 0 1 1 1 1 1 1 0 1 1 10 1 1 1 1 1 1 1 1 1 1 0 1 11 0 0 0 1 1 1 1 1 1 1 1 0 11 0 0 1 1 1 1 1 1 1 1 1 1 0

1 0 1 0 1 1 1 1 1 1 1 1 1 1

1 0 1 1 1 1 1 1 1 1 1 1 1 11 1 0 0 1 1 1 1 1 1 1 1 1 11 1 0 1 1 1 1 1 1 1 1 1 1 11 1 1 0 1 1 1 1 1 1 1 1 1 11 1 1 1 1 1 1 1 1 1 1 1 1 1

Table 11: Truth Table for 7442 Decoder

The 7442 comes in a 16 pin dual inline package. This implies that pin 8 isground and pin 16 in VCC. Both pins must be connected to their respectivesupplies to allow proper functionality. The pin layout for the 7442 is shown inFigure 45.

8.6 74LS157 Quad Multiplexer

The 74LS157 Quad Multiplexer is an integrated circuit that contains four multi-plexers controlled by a single select signal. A multiplexer functions as a switch.In this case, there are 8 input pins, 4 output pins and one select pin. If the

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select pin is set to logic 0, the multiplexers will output the data on the A input.On the other hand, if the select pin is set to logic 1, the multiplexers will outputthe data on the B input. The 74LS157 also has an enable pin (pin 15) which isactive low. If the enable pin is set to an active high, the outputs of the 74LS157are in high impedance mode. The pin-out diagram is shown in Figure 46.


8.7 74LS126 Tri-State Buffer

The 74LS126 tri-state buffer provides 4 buffers that are controlled by indepen-dent enable signals for each buffer. A buffer simply outputs the value it is givenas an input. The tri-state feature makes using this integrated circuit ideal forbusses. When the enable signal is logic high, the output is enabled. If the enablesignal is a logic low, the output is a high-impedance mode which acts as if theoutputs were disconnected. The pin layout is presented in Figure 47.

8.8 The Experiment

The experiment is split into three components: the first component is to assem-ble the circuit needed to program the RAM, while the second task is to programthe RAM. Lastly, students are to demonstrate to their lab demonstrator whatthey have programmed.

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8.8.1 Building the Circuit

The circuit is built by using the schematic shown in Figure 48. Pull-down

resistors are necessary and cannot be omitted. The address lines A4 to A9 aregrounded so that the RAM will not use more than four bits to address since thememory address register and program counter only provide up to 4 bits. Thisimplies that the computer is able to execute a program of 16 instructions. Thewrite enable pin is tied to a switch so that the memory can be easily switchedbetween read or write modes.

Another bus is used to input the data. This is done so that the data canbe input then read without needing to switch wires around while the circuitis operational. The data being inputted is fed into a 74LS126 quad tri-statebuffer. The control pins of these buffers are tied to a switch called PROGRAM.When the switch provides a logic 1, the buffers output their contents. When setto 0, the buffers are in high-impedance mode. Another set of tri-state buffersare placed to output to the 7442 used to generate the instruction signals. This

extra set of buffers use the inversion of PROGRAM to enable the outputs. Thisis done so that the computer does not attempt to execute unwanted instructionswhile transitioning from reading and writing memory. The switches D3 to D0are used for data inputting.

The address lines A3 to A0 are tied to switches and fed through a 74LS157multiplexer. This is necessary since the MARs outputs will also be wired intothese address lines. The multiplexers select is controlled by the ADDRSELECTswitch.

8.8.2 Programming the RAM

Below are the steps to program the RAM. Please follow these instructions care-fully or else the programming will fail.

1. Turn on the circuit. Do not power down the circuit at all or else any saveddata will be lost and the process must be restarted.

2. Set the CE switch to high. By doing this, the RAM is in high impedancemode.

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3. Set the WE switch to low. This sets the RAM into write mode when theCE switch goes low.

4. Set the PROGRAM switch to high. This enables the buffers needed anddisables the ones not.

5. Set the ADDRSELECT switch to low. This selects the address switchesto the RAM.

6. Set the address switches accordingly. Start at 0000. At this moment aswell, set the data switches to reflect the desired instruction.

7. Set the CE switch to low. This will cause the RAM to write the instruc-tion defined by the data switches at the address provided by the addressswitches.

8. Repeat from Step 2 until all 16 instructions have been stored in the RAM.

8.8.3 Displaying the Contents of the RAM

At this point, the circuit should still be powered. If you do shut down the circuitat any point in time, you must reprogram your RAM. Set the CE switch to highso that the RAM is unaffected by any work being done. The write enable pin isnow to be set to a logic high so that the RAM enters read mode. Additionally,the PROGRAM switch should be set to low as well. The output of the RAMis fed into the decoder which will then produce the appropriate control signalfor the computer to execute. The decoders outputs are the instruction signalsISIG0 to ISIG5. Please refer to the schematic is shown in Figure 48. To set theRAM for outputting data:

1. Keep the circuit powered.

2. Set the CE switch to high to set I/O pins to high impedance mode.

3. Set PROGRAM switch to low to enable tri-state buffers for the decoderand disable the input buffers.

4. Set WE switch to high to enter read mode.

5. Set the ADDRSELECT switch to high.

6. Set the CE switch to low to re-enable the RAM.

7. Reset Program Counter if needed.

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8.8.4 Demonstrating Your Work

For this experiment, the students are expected to fill all 16 addresses in memoryand be able to show their contents to the lab demonstrator. It is best fordebugging to make a table of the values you input, the expected result and whatresult is actually obtained. The contents of each address is to be determinedby the students. The outputs of the 7442 decoder are intended to be wired toLEDs to visualize the results. Remember that anything above 0101 is a NULLinstruction!

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Figure 48: RAM Circuit Diagram

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9 Project Experiment 4: The Control Signal

GeneralThe control signal generator is the portion of the project that renders the com-puter able to execute functions. Up to this point, a program counter, tim-ing/clock system and memory have been implemented. This experiment buildsthe combinational logic needed to facilitate the instructions decoded from mem-ory. The decoded values are then fed into the control signal generator to producethe necessary signals to execute instructions.

The timing of this computer is subdivided into 8 pulses, T0 to T7. OnlyT0 to T3 have been used and have been used solely to increment the programcounter. The remaining four pulses are used for instruction execution. Whilethe design built has support for up to six instructions, only three will be im-plemented. There is no definition for which instruction signal corresponds with

a particular value stored in the memory. It is up to the student to decide whateach instruction signal from the decoder should trigger.

9.1 The IncB Instruction

The IncB instruction is an instruction that increments the value of B by 1. Thisinstruction makes use of the bus, the 74LS283 4-bit adder and SUM register thathave been used only for incrementing the program counter so far. In previousexperiments, the 74LS283 was wired to increment values by 1 and this does notchange. This behaviour is in fact identical to how the program counter worksbut with different timing signals.

The IncB instruction is executed by doing the order of tasks:

1. Data Register B outputs its contents onto the bus

2. SUM Register writes the incremented value of B = B + 1

3. SUM Register outputs value of B = B + 1 onto the bus

4. Data Register B writes the contents of the bus

9.2 The MovAB Instruction

The MovAB instruction simply copies the values of Data Register A to DataRegister B by using the bus. This is achieved by doing the following tasks inorder:

1. Data Register A outputs its contents onto the bus

2. Data Register B writes the contents of the bus

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9.3 The MovBA Instruction

The MovBA instruction operates and behaves the same way as the MovABinstruction but the contents of B is copied to A. It is achieved by:

1. Data Register B outputting its contents onto the bus

2. Data Register A writing the contents of the bus

9.4 The IncA Instruction

Similarly, the IncA instruction behaves the same way as the IncB instructionbehaves and increments the value of A by 1. The instruction is omitted butcan be implemented as an exercise by the students. It is executed by doing thefollowing:

1. Data Register A outputs its contents onto the bus

2. SUM Register writes the incremented value of A = A + 1

3. SUM Register outputs value of A = A + 1 onto the bus

4. Data Register A writes the contents of the bus

9.5 Implementing the Signal Generator

To implement the Control Signal Generator for three 3 instructions, two 7432ICs and one 7408 IC are needed. To implement the additional IncA instruc-tion, additional logic is needed and it is up to the student produce it. Beforeproceeding onward, the signal IncB is an output of the 7442 decoder used in

the previous experiment designated by the student to increment the data reg-ister B. Similarly, MovBA and MovAB are also output signals chosen by thestudents. There are two control signals for the Data Register B, Bin which con-trols the input and Bout which controls the output. Similarly, two signals existfor the Data Register A, Ain and Aout. The input signal goes to the clock ofthe register, while the output enables of the registers is fed the output signals.Additionally, the SUMin and SUMout signals for the SUM register are modifiedas well. The supporting logic is shown below, in Figure 49. Each instructionshould be implemented and tested at a time. This will make it easier to diagnoseand debug should any issue arise.

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Figure 49: Control Signal Generator Logic

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10 A Note on Circuit Schematics

This section aims to clarify some questions and misunderstandings about howa logic block diagram differs from an electrical schematic.

10.1 Block Diagrams

A block diagram is a quick way of visualizing how a logic system may function.Symbols are used to denote different components or gates within the system. Itis a suitable tool for prototyping a logic function. As an example, let us considerthe function F = (A B) + C. A logic block diagram of this function is shownin Figure 50.

Figure 50: Typical Block Diagram

This diagram easily shows how the function is built from logic but it does notprovide details about how it is physically implemented. How the user interactswith the inputs A and B is completely left unknown along with how the outputsare handled. These details are suited for an electrical schematic. In a blockdiagram, there should be no reference to switches, LEDs, part names, ground,VCCand so on...

10.2 Electrical Schematics

An electrical schematic is a comprehensive diagram, showing how devices areinterconnected. In an electrical schematic, the whole system is displayed. Thisincludes every detail such as labelled switches for inputs, resistors, LEDs. Ifsomebody were to recreate a system, an electrical schematic would be a suitabletool to do so rather than a block diagram. Using the same function F =(A B) + C, an electrical schematic is produced in Figure 51. In the schematic,there are switches, power supply connections, grounds, LEDs, resistors, partnames, references and pin numbers. This system can be easily replicated withno questions asked.

10.2.1 Using the Right Symbol and Showing Supply Connections

When making schematics, it is common practice to not show supply pins suchas connections to VCC and GND. This is due to the fact that it is assumed thatthe person who would read the schematic knows that having these supply pins

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Figure 51: Typical Electrical Schematic

wired is a necessity. As an example, the schematic for the 555 Timer (Figure 31)do not show the connections to VCC and GND (pins 1 and 8).

In an electrical schematic, it is common convention to use the logic symbolsfor the basic logic functions such as AND, NAND, NOR, NOT, OR, XNOR andXOR. These symbols do not have pins for supply voltages like VCC or GND.This is due to the fact that a schematic can be presented in a clearer manner.That being said, the symbols are still annotated with theirpart name, referenceand pin numbers. Depending on the schematic software used, a logic componentmay come as a whole IC for a part.

10.2.2 Part Names and References: Why Do They Matter?

Using the appropriate part in schematics can be confusing at times. To use theappropriate name, knowledge of the circuit is required beforehand. Considerthe example of an AND gate IC. There are multiple AND gates with differenttechnologies. Not all of them use the same logic level values, some may treata logic 1 as 3.3 Volts instead of 5 Volts. Some AND gates may be able tooperate faster than others. Because of this, it is critical to use the proper partin a schematic. A 74LS08 AND gate is not the same as a 4081 even if theymay perform the same logic function. Additionally, using the right part in aschematic is also beneficial since it is representative of what is performed in thelabs.

Note: While the 7400 logic family is used, the variants used in the lab arethe 74LS and 74HC families. The pin-outs are the same but internally, these

integrated circuits differ. They are equivalent in specification and can be usedinterchangeably. It would be incorrect to say a 74ACT08 was used as opposedto a 7408 or 74LS08. For the basic AND, NOT and OR gates, it is common tonot refer to the family unless necessary. Saying that a 7404 was used is correct,as well as saying that a 74LS04 was used.

In many cases, an integrated circuit may have multiple gates or units of

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the same function. This is a common occurrence as seen in the 7404, 7408and 7432. It would not be resourceful or efficient to take three 7432 devices

if three OR gates were needed. Since the 7432 provides four readily availableOR gates, one integrated circuit is sufficient. Each part used in a schematic isgiven a reference. Generally, for resistors, the scheme is R then the number ofthe resistor. For capacitors, it is similar with C then a number following theletter. For integrated circuits, however, the letter U is used to designate anintegrated circuit then followed by a number. As seen in Figure 51, each partis labeled appropriately and then a letter is designated. This letter indicatestheunitused. The first unit was used for the 7408 and it is the first integratedcircuit placed, therefore the reference is U1A.

Now, the function F = A B C calls for two AND gates. Only one 7408is needed since there are four AND gates onboard. In Figure 51, the schematicis shown. The two AND gates come from the same integrated circuit and aredenoted by U1. Each gate is an individual unit which explains why there is anAND gate designated by U1A and another designated by U1B. Also, take noteof how the pins differ for each unit.

Figure 52: Schematic With Multiple References

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11 Using the 74LS173 As a Replacement for the

74LS395The 741LS73 4 Bit Register can be used as a replacement for the 74LS395Register. There are a few notable differences between the two integrated circuitshowever and the goal of this Appendix is to detail what is needed so that the74LS173 can be used.

The most important difference is that the 74LS173 Register is a positive-edge clocked device. The register writes data when the clock signal transitionsfrom low to high. Throughout the project, negative-edged triggered devices areused. To make the 74LS173 compatible with the project, an inverter is neededon the clock. Because of this, the 74LS173 requires at least one 7404 for properuse. Additionally, the master reset (pin 15) is active high as well. To preventthe device from constantly resetting, pin 15 must be wired to ground.

Additionally, the data input enable pins (pins 9 and 10) are wired to ground.This is to ensure that the data will be written every clock pulse. The outputenable pins are active low so inverters are needed. Stored data will be outputwhen both pins 1 and 2 are active low and should be wired to the TSG. Asexpected, pin 8 is wired to ground and pin 16 is wired to VCC. Pins 3 to 6 areoutputs and Pins 11 to 14 are inputs.

The typical use of the 74LS173 as a replacement for the 74LS395 is shownin Figure 53.

Figure 53: 74LS173 Circuit for Replacing The 74LS395

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