lab 3 as you wait for the lab to start : reserve seats for your partners look at the course web...

Lab 3

As you wait for the lab to start : Reserve seats for your partners Look at the course web site :

http://cis.poly.edu/cs2204

Experiment 1

Digital Logic and

State Machine Design

CS 2204CS 2204CS 2204CS 2204

Spring Spring 20142014Spring Spring 20142014

Experiment 1 Lab 3 Outline Presentation

Using CS2204 Lab & Engineering Fundamentals Digital Design Trends

Digital Design Tools Using Term Project (pages 8 – 13 and 16 - 20)

The input/output relationship ≡ Operation ≡ Purpose ≡ Game rules

Term project operation diagram and initial partitionings Analysis of Block 2 of the term project

Individual work Experiment 1 is over three weeks : Labs 3, 4 and 5

Develop a 4-bit 2-to-1 MUX of Block 2 By using 1-bit 2-to-1 MUXes over three weeks

Today Analyze (simulate) a 4-bit 2-to-1 MUX of Block 2 Simulation of other components in ppm

Experiment 1 Lab 3CS 2204 Spring 2014


Digital Design Trends Current Digital Design Tools

Even if we use current digital engineering design techniques

Top-down, team-based and core-based design Today’s circuits are too complex to be developed fast

One needs powerful tools to simplify the design process


Current Digital Engineering Design Tools Computer aided design (CAD) software to

develop circuits on computersComputers handle the details

Field Programmable gate arrays (FPGAs) to physically test the chip designed

FPGAs are used when a new chip is developed

Complex circuits require more than one FPGA chip


CAD Software Abstracts the design by hiding details

unnecessary at the momentDesign editors

To design the circuit Schematic and hardware description language (HDL)

Logic and timing simulators To test the design

FPGA interfaces and downloadersChip layout editorsPCB layout editors

CAD Software Polytechnic digital design software packages

Xilinx ISE , Mentor Graphics, Cadence, Synopsis All industry software packages Senior-level and graduate courses use them

Xilinx ISE 12.4 Targets FPGA as the final product, not chips

Mentor Graphics, Cadence and Synopsis target chips and/or PCBs

We will use it to do schematic design, simulations and FPGA implementations

Installed on PCs in 227RH


Digital Design Schematic (traditional)

Circuit diagrams with gates, FFs and wires are drawn Impractical if the component (gate + FF) count is high

such as today’s microprocessors


b

a

c

a

y(a, b, c) =y(a, b, c) = a.b + a.ca.b + a.c


Schematic Design One schematic sheet containing many

components and wires is prohibitive Still impractical even if the schematic is

partitioned to sheetsThe designer has to deal with many

unnecessary details Drawing many wires and placing many components

are some of the unnecessary details

CS2204 uses schematic design since the term project is not very complex


Digital Design Hardware Description Language (HDL) -based

design (now) The designer writes a program in an HDL to design a

digital circuit CAD software converts text to components and wires The HDL program has “modules” to allow block-based,

team-based and core-based design Today’s digital circuits require HDL-based design

Software languages, including graphical languages (C, C++, MATLAB, LabVIEW,…) will be used to design hardware (in the future)

C, C++, MATLAB and LabVIEW are increasingly used to design hardware today


Popular HDL Languages VHDL : VHSIC HDL

VHSIC ≡ Very High Speed Integrated Circuit A project of DARPA (Defense Advanced Projects

Agency)Developed in the 1980sLooks like the ADA language (of the 1980s)Taught at Poly

Verilog HDLEqually used with VHDLDeveloped earlier than VHDLLooks like the C language


A VHDL Program Examplelibrary IEEE;

use IEEE.std_logic_1164.all;

entity caralarm is

port (

engine: in STD_LOGIC;

belt: in STD_LOGIC;

alarm: out STD_LOGIC

);

end caralarm;

architecture caralarm_dataflow of caralarm is

begin

alarm <= ‘1’ when engine = ‘1’ and belt = ‘0’

else ‘0’ ;

end caralarm_dataflow ;

belt

engineAND

alarmNOT

Car Alarm Schematic

alarm = engine belt


A VHDL Program Examplelibrary IEEE;use IEEE.std_logic_1164.all;

entity caralarm is port ( engine: in STD_LOGIC; belt: in STD_LOGIC; alarm: out STD_LOGIC );end caralarm;

architecture caralarm_dataflow of caralarm isbegin alarm <= engine and not belt ;end caralarm_dataflow ;

belt

engineAND

alarmNOT

Car Alarm Schematic

alarm = engine belt


Another VHDL Program Example

A

B

CINSUM

COUT1-bit

Adder

library IEEE;use IEEE.std_logic_1164.all

entity fulladder isport (A, B, CIN : in STD_LOGIC;

SUM, COUT : out STD_LOGIC);end fulladder;

architecture fulladder_dataflow of fulladder issignal s1, s2, s3,s4,s5: STD_LOGIC;begin

s1 <= A xor B;SUM <= s1 xor CIN;s2 <= A and B;s3 <= B and CIN;s4 <= A and CIN;s5 <= s2 or s3;COUT <= s4 or s5;

end fulladder_dataflow;


VHDL at Poly CS2204 covers VHDL during the last

lecture of the semester EE4313 (Computer Engineering Design

Project I) is on VHDL A number of EL (EE graduate) courses also

cover VHDL


Field Programmable Gate Arrays (FPGAs) FPGAs are used for prototyping of chips to test

the design physically They are used to develop a new chip The new chip is tested on FPGAs

Complex circuits require more than one FPGA chip Designers have a better understanding of their new chip

Design problems not discovered while simulating the circuit on computers are discovered

► Additional logic errors

► Speed, cost, power, size, etc. issues

FPGAs are now finding use in commercial products

Xilinx, Altera, Lattice Semiconductor, Microsemi, are some of the largest FPGA companies


FPGAs to Test the design physically Why not fabricate the prototype chip after

extensive simulations on computers ?Not all logic errors and issues can be

discovered via simulations

FPGAs at PolySome upper level EE and EL (graduate EE)

courses require FPGAsEL6493 Advances in Reconfigurable Systems


Xilinx FPGAs An FPGA is hardware programmed (reconfigured)

by downloading a bit file to the FPGA The bit file is generated from the schematic by the Xilinx

ISE software

The internal circuitry consist of Configurable (programmable) logic blocks (CLBs)

A CLB contains look-up tables (LUTs), flip-flops and other components

A look-up table implements a combinational circuit Gates do NOT implement combinational circuits on the FPGA

chip !

Programmable connections Other blocks


Xilinx FPGAs Consist of configurable (programmable) logic

blocks (CLBs), programmable connections and other blocks

A CLB contains look-up tables (LUTs), flip-flops and other components

A look-up table implements a combinational circuit

CLB. . .

. . .

. . .

. . . . . . . . . . . . . . .


CS2204 Xilinx FPGA Spartan-3E : XC3S500E-5FG320

1164 CLBs organized as a 46x34 array Input/output blocks

Connecting the pins to the internal logic Interfacing to the external world

360 Kbit Block RAM Embedded in the CLB array, replacing some of the CLBs

20 18-bit multipliers 4 Digital clock manager blocks

Distributing and generating clock signals on the chip

. .

. .

. . . . . . . . . . .. . . . . .

CLB



A CLB Implemented by means of four slices Contains eight LUTs and 8 FFs

Each LUT implements a 4-input 1-output combinational circuit It contains 16 bits !

There are also multiplexers, carry and arithmetic logicCLB




Each slice has 2 LUTs and 2 D FFs Right two slices in each CLB support only logic (SLICEL) Left two slices in each CLB support both logic and memory functions

(SLICEMEM) The four LUTs in all the SLICEMEMs can be used to form a 74496-bit

Distributed RAM




Each slice has 2 LUTs and 2 D FFs There are also multiplexers, carry and arithmetic logic

Each slice accepts cin and outputs cout through a number of AND gates

Each slice also outputs sum by using EXOR gates



360 Kbit Block RAM Embedded in the CLB array, replacing some of the CLBs 20 18Kbit dual ported Block RAMS on two columns replacing the

CLBs there 20 18-bit multipliers

Each is immediately adjacent to a block RAM Each is a 18x18 multiplier



4 Digital clock manager (DCM) blocks Distributing and generating clock signals on the chip

Clock-skew Elimination: Clock skew within a system occurs due to the different arrival times of a clock signal at different points on the chip, typically caused by the clock signal distribution network

Clock skew is undesirable in high frequency applications The DCM eliminates clock skew by phase-aligning the output clock

signal that it generates with the incoming clock signal This mechanism effectively cancels out the clock distribution delays Frequency Synthesis: The DCM can generate a wide range of

different output clock frequencies derived from the incoming clock signal

This is accomplished by either multiplying and/or dividing the frequency of the input clock signal by any of several different factors

Phase Shifting: The DCM provides the ability to shift the phase of all its output clock signals with respect to the input clock signal

There are global clock lines to distribute clock signals with little delay



Consist of configurable (programmable) logic blocks (CLBs), programmable connections and other blocks

Interconnect, also called routing, is segmented for optimal connectivity

There are four kinds of interconnects: long lines, hex lines, double lines, and direct lines

The Xilinx Place and Route (PAR) software tries to use the interconnect array to deliver optimal system performance

. .

. .

. . . . . . . . . . .. . . . . .

CLB


Xilinx FPGAs Spartan-3E : XC3S500E-5FG320

There are 320 pins on the bottom of the FPGA chip


. . .

. . .

. . .. . . . . . . . .. . .. . .

Xilinx FPGAs An FPGA is hardware

programmed (reconfigured) by downloading a bit file to the FPGA

The bit file is generated from the schematic by the Xilinx Foundation software

Spartan-3E : XC3S500E-5FG320

1164 CLBs organized as a 46x34 array


. . .

. . .

. . .. . . . . . . . .. . .. . .

Xilinx FPGAs An FPGA is hardware programmed (reconfigured) by downloading

a bit file to the FPGA The bit file is generated from the schematic by the Xilinx Foundation

software Spartan-3E : XC3S500E-5FG320


CLBslice SLICEL


Xilinx FPGAs An FPGA is hardware

programmed (reconfigured) by downloading a bit file to the FPGA

The bit file is generated from the schematic by the Xilinx Foundation software

Spartan-3E : XC3S500E-5FG320


What are they ?


Xilinx FPGAs An FPGA is hardware programmed (reconfigured) by downloading

a bit file to the FPGA The bit file is generated from the schematic by the Xilinx Foundation

software Spartan-3E : XC3S500E-5FG320



Xilinx FPGAs An FPGA is hardware programmed (reconfigured) by downloading a bit file

to the FPGA The bit file is generated from the schematic by the Xilinx Foundation software

Spartan-3E : XC3S500E-5FG320 1164 CLBs organized as a 46x34 array


The Term Project Usage of the XC3S500E-5FG320

282 out of 4656 slices used : 6%utilization


Analysis of the Term Project The term project black-box view The term project operation diagram The term project black box partitioning


The Analysis of the Term Project Polytechnic Playing Machine, Ppm

The term project is human vs. machine

There are two other Ppm versions which are not term projects

Machine vs. machine Human vs. human


The Term Project, Ppm The black-box view

Ppm is sequential (not combinational) A large number of FFs are used ! We need to partition the Ppm based on major operations

We have to obtain the operation diagram

From page 2 of the Term Project Handout

Figure 1. The Ppm black box view.

Ppm13 19

From the input devices To the output devices


The Term Project, Ppm The black-box view


Clock

Pp

m

P1SEL4

SW7 - SW4

LD2 - LD0

Four 7-Segment Displays

P2playBTN2

P1playBTN3

ResetBTN1

ShptsBTN0

Figure 3. Inputs and outputs of the Ppm term project.

CLK1

LD7 - LD4

P1addSW0

Add

STR0

STR1

STR2

RD0

RD1

RD2

RD3

LD3

A4

A3

A1

A0

CG

CF

CE

CD

CC

CB

CA

TRD3

SW3 - SW1


The term project, Ppm The input/output devices of the Ppm (without clock)


Please be gentle with push buttons and switches

SW7 SW6 SW5 SW4 SW3 SW2 SW1 SW0

LD7 LD6 LD5 LD4 LD3 LD2 LD1 LD0

BTN3 BTN2 BTN1 BTN0

STR

All zero when the

Position Displays

A display blinks fast if display overflow

Reset P1play/ Shpts/

All displays blink if points limit exceeded

P2play

FPGA is downloaded/reset

P1add

Figure 2. FPGA Board Input/Output device utilization of the Ppm Term Project.

PD3 PD2 PD1 PD0

RDAdd

P1SEL

7-segment displays Switches

LED Lights

Push buttons

NextRDs/

Random Digit

Use SW3-SW0 as RD Code digitsCode digits


Sequential Circuit Basics Today’s sequential circuit are synchronous, meaning that all

operations start and end at the same time This implies all operations take the same time

Add, subtract, compare, and, or, not, nand, nor,… These operations are performed by combinational circuits Combinational circuits are high speed circuits !

Actually, some operations take less time than others Addition and subtraction take the longest time Comparing two 32-bit numbers takes much less time than adding

two 32 bit numbers We still wait as if we are doing an add or subtract ≡ We waste time Our circuit would be faster if they were not synchronous ≡

asynchronous

If we used asynchronous sequential circuits, they would be faster There is no clock ! An asynchronous microprocessor ≡ There is no clock ! However, designing, testing, modifying and upgrading asynchronous

sequential circuits are more difficult


Sequential Circuit Basics Today’s sequential circuit are synchronous, meaning that all

operations start and end at the same time All operations take the same time

A special input, the clock input indicates when operations start and end

All operations take the same time ≡ One clock period of time ! All synchronous sequential circuits use a clock signal

Clock

Startnow

End now

Startnow

End now

All operations take this time !

One clock period


Sequential Circuit Basics A special input, the clock input indicates when operations

start and end The clock period duration indicates the operation duration

The clock period duration is determined by the longest operation duration

The clock period duration is slightly longer than the longest operation duration to account for temperature and humidity changes and component variations

We check all operation duration lengths and determine which one takes the longest time and so adjust the clock period duration

Clock

Startnow

Endnow

Startnow

Endnow

All operationstake this time !

Maxaddtime

Device tolerancetime

One clock period


Sequential Circuit Basics A special input, the clock input indicates when

operations start and end The clock period duration indicates the operation duration

The clock period duration is specified in terms of seconds The relationship between the clock period and clock

frequency

Clock

Cp 1 Cp 2 Cp 3 Cp 4 Cp 5 Cp 6 Cp 7 Cp 8

seconds frequencyClock

1 periodClock


Sequential Circuit Basics A special input, the clock input indicates when

operations start and end The clock period duration indicates the operation

duration The clock frequency is specified in terms of Hertz One Hertz means there is one clock period in one

second Then, the clock period duration is 1 second

Operations take less than 1 second !

Clock


second 1 1

1

frequencyClock

1 periodClock

1 second 1 second 1 second 1 second


Sequential Circuit Basics A special input, the clock input indicates when operations

start and end The clock period duration indicates the operation duration The clock frequency is specified in terms of Hertz If the clock frequency is 1 GHz ?

1 GHz ≡ 109 Hertz Then, there are 1 billion clock periods in second ! Then, the clock period duration is 1 ns Operations take less than 1 nano second ≡ They take in terms of

picoseconds !

Clock


ns 1 seconds 9-10 910

1

frequencyClock

1 periodClock

1 ns1 ns 1 ns1 ns


Sequential Circuit Basics We indicate which operation takes place when by using a diagram

that has circles and arrows To show operations with respect to time

A circle specifies which set of operations take place in parallel The circle is a state In a particular clock period only one state happens

A state indicates which operations happen in parallel in the clock period that corresponds to a state

Arrows indicate which operations follows which operations Arrows may be tagged with labels indicating conditions to satisfy to take

them The result is a high-level state diagram with microoperations !

R K + M a

M M - 1

a

……

Clock period 45

Clock period 46

Time

OUT = R


Sequential Circuit Basics When we start designing a complex sequential circuit, we

would not specify all the details ≡ Top-down design ! We would not draw a high-level state diagram

We draw an abstract state diagram We draw an operation diagram

We use words to specify operations We use complex tags next to arrows

Eventually, we obtain the high-level state diagram

Add K and Ma is nonzero ?

Subtract 1 from M

a is zero ?

Output result

……

Clock period 45

Clock period 46

Time


Sequential Circuit Basics When we start designing a complex sequential circuit, we

would not specify all the details ≡ Top-down design ! We draw an operation diagram

The operation diagram indicates major operations ≡ The input/output relationship !

We partition the complex sequential circuit based on the major operations, the design goals and technology ≡ Product goals

We use complex tags next to arrows

Eventually, we obtain the high-level state diagram with more details !

Add K and Ma is nonzero ?

Subtract 1 from M

a is zero ?

Output result

……

Clock period 45

Clock period 46

Time


Designing the Ppm circuit Ppm is complex sequential circuit

We must obtain its operation Diagram ! First take

Convert the simplified operation diagram to a (more detailed) operation diagramConvert each circle to one or more circles (steps or states)

Reset mode

Player 1 mode

Player 2 mode

Press BTN3 4 times

Press BTN2 to skip

Press BTN2 after playing RD without an

adjacency

Press BTN3 after playing RD with an adjacency

Press BTN2 after playing RD with an adjacency

Press BTN3 after playing RD without an adjacency

This operation diagram is too abstractWe cannot obtain the major operations !


PpmInput/outputrelationship

Ppmoperationdiagram

Fro

m p

ag

e 8

of

the T

erm

Pro

ject

Han

dou

t

LD0-LD2 on the FPGA board show the current state

The game is reset : 0 points for players, 0s on posi tion displays !

Player 1 turns on SW0 if wanted. Player 1 turns on and off one of SW7-SW4 to select a position. Player 1 turns off SW0 if on

Player 1 presses BTN2, P2play,

1

2

3

Play

er 1

mod

eP

laye

r 2

mod

e

Download to the FPGA chip

Res

et m

ode

Player 1 points being calculated !

Player 1 presses

BTN 2, P2play, to skip play

Player 1 examines the s ituation !

Player 1 thinks !

4

Player 2 thinks !

5

Player 2 plays on a pos ition

6

Player 1 examines the situation !

Player 2 skips play

(Pla

yer 1

pla

ys)

(Pla

yer

2 p

lays

)

Figure 5. The operation diagram of Ppm.

Player 1 can press BTN3, Reset, in any

Pla

yer

1 c

an p

ress

BT

N4

, Sh

pts

, in

an

y s

tate

to

see

pla

yers

’ p

oin

ts

Player 1 presses BTN3, P1play, four times to play(In

itia

l sta

te)


to allow the machine player to play


to allow herself to play again ifthere is an adjacency

Player 1 presses BTN3, P1play, to allow herself to play

Play

er 1

pre

sses

BTN

2, P

2pla

y,

to a

llow

the

mac

hine

pla

yer

to

play

aga

in if

ther

e is

an

adja

cenc

y

0Player 1 can press BTN3, P1play,in state 1 or 3 to see next two RDs

If one of SW7-SW4 is onin state 3, a random digitis input for the machineplayer from SW3-SW0when BTN2 is pressed

state to return to the Reset state, State 0


Points Calculation block

Machine play block

Human play block

Play check block

Machine Play Block is also active states 2 and 5

Input/Output Block

The game is reset : 0 points for players, 0s on position displays !



1

2

3Pl

ayer

1 m

ode

Pla

yer

2 m

ode

Download to the FPGA chip

Res

et m

ode


Player 1 presses



Player 1 thinks !

4

Player 2 thinks !

5


6


Player 2 skips play

(Pla

yer 1

pla

ys)

(Pla

yer

2 p

lays

)



Pla

yer

1 c

an p

ress

BT

N4

, Sh

pts,

in

any

sta

te to

see

pla

yers

’ poi

nts


itia

l sta

te)






Play

er 1

pre

sses

BTN

2, P

2pla

y,

to a

llow

the

mac

hine

pla

yer

to

play

aga

in if

ther

e is

an

adja

cenc

y




Input/Output Block is active in every state


The Ppm Term Project Partitioning We have observed the following major operations

Interfacing to the input/output devices Handling human player’s play Controlling display operations based on game rules Calculating new player points Determining the machine player play

Hint for general partitioning If you cannot figure out major operations,

partition one major operation at a time

Experiment 1 Lab 3

The Ppm Term Project Partitioning Any other major operation ?

Control (time) the operations All other operations

A Digital System

The game is reset : 0 points for players, 0s on position displays !



1

2

3

Play

er 1

mod

eP

laye

r 2

mod

e

Download to the FPGA chip R

eset

mod

e


Player 1 presses



Player 1 thinks !

4

Player 2 thinks !

5


6


Player 2 skips play

(Pla

yer 1

pla

ys)

(Pla

yer

2 p

lays

)



Play

er 1

can

pre

ss B

TN

4, S

hpts

, in

any

stat

e to

see

play

ers’

poi

nts


itia

l sta

te)






Play

er 1

pre

sses

BTN

2, P

2pla

y,

to a

llow

the

mac

hine

pla

yer

to

play

aga

in if

ther

e is

an

adja

cenc

y




CS 2204 Spring 2014


Digital Systems A digital system consists of digital circuits

A digital system performs microoperations

A microprocessor is a digital system An iPhone is a digital system A computer is a collection of digital

systems

Sun Niagara dieIntel Tukwila die IBM Power 6 dieMIPS R10000 die


The Ppm Digital System Partitioning A Control Unit (Sequencer)

Just one block !

A Datapath (Data Unit) controlled by the Control Unit

There are five blocks in the Datapath



The term project black box partitioning• Six schematics for six blocks

• Block 1 : Control Unit• Block 2 : Input/Output

• Experiment 1 is on a circuit in this block

• Block 3 : Human Play• Block 4 : Play Check• Block 5 : Points Calculation file• Block 6 : Machine

• The Machine Play Block uses all other blocks except the Human Play Block

• These six schematics are in the ppm.sch file


Input/Output Block, Block 2 Has 84 inputs and 38 outputs Controls input/output devices on the FPGA board

and generates timing signals Has sequential circuits

Block 284 38


The Ppm Data Unit Block 2, Input/Output Block

Fro

m p

ag

e 1

7 o

f th

e T

erm

Pro

ject

Han

dou

t

Block 284 38

Clear

Calcpts

P1PT 8

P2PT 8

Figure 11. The input and output signals of the Input/Output Block.

Clock

P1SEL4

SW7 - SW4

P1playBTN3

P2playBTN2ResetBTN1ShptsBTN0

CLK1

3STR LD2 - LD0

16DISP

Ptovf

4RD LD7 - LD4Add

Clff

Bpdf

Bpds

LD3

Inp

ut/O

utp

ut B

lock

Blo

ck 2

Core

Stp1pt

Stp2pt

A1

A2

A3

A4CACBCCCDCECFCG

SBUS

Four

7-SegmentDisplays

DISPEN

P1addSW0

4RD

3STR

Pdprd4

PSEL

Q7

Rdclk

Sysclk

P2playsynch

P1playsynch

Lpdprd

Lptovf

4R1D

4R2D

P1unbufgplay

P2clk

TRD3

SW3 - SW1

Add

Reset

P1SEL4

Shpts

P1add

3TRD

2DISPSEL

8P2CODE



Controls input/output devices on the FPGA board and generates timing signals

Three major operations Controls Input/Output Devices

I/O Buffer Subblock Display Subblock

Generates timing signals Timing Subblock

Block 284 38



DisplaySubblock

TimingSubblock

I/O BufferSubblock

Today’s work : 4-bit 2-to-1 MUX


Block 2, Input/Output Block Development I/O Buffer Subblock implementation

SW7-SW4

BTN3-BTN0

RD

Add

PD3 – PD0

Inputs

Clock : 50MHz

SW0

P1SEL

Outputs

FPGA chip pins


Block 2, Input/Output Block Development Timing Subblock implementation

32-bit frequency divider

Sysclk

P2clk

Rdclk6 Hz

48 Hz

192 Hz

Clock from the board : 50 MHz


Block 2, Input/Output Block Development Display Subblock implementation



Block 2, Input/Output Block Development Display Subblock implementation

Convert the 4-bit codeof the selected displayto a 7-bit code

SelectDisplays,Points,next RDs, discovered code digitsOutput to displaysone digit at a timea 4-bitcode



Today’swork

Xilinx Project Development Steps Develop the schematic

Design the schematic Do a schematic check Test the schematic via logic simulations

Do a Xilinx IMPLEMENTATION (Synthesis, Implement Design, Generate Programming File)

It maps the components to the CLBs of the chip Do timing simulations to test the schematic

It generates the bit file

Download the bit file to the FPGA and test the design

It programs the chip which emulates the design


Why Simulate the Design on Computers ? Simulating the design allows engineers

catch logic errors and deviations from operations, speed, cost, power, size, etc. early

Logic (functional) simulations allow designers to determine if the circuit is functioning according to operation specification

Today !Timing simulations allow designers to

determine if there are deviations from speed and power, etc.

In two weeks !


Digital Engineering Terminology Gates and FFs are implemented by

electronic circuitsElectronic circuits use electronic components

Transistors, resistors, diodes, capacitors,…Most Common Voltages for Logic Values

Logic 1 is +5v Logic 0 is 0v

The terminology +5v VCC 0v GND (Ground)

NAND

NAND gate


Block 2, Input/Output Block Development Today’s work : 4-bit 2-to-1 MUX

Ground0 Volts

Enable

Common Logic Errors


U3

The OR gate is an AND gate by mistake !

Input “a” is input “b” by mistake !

Must becorrected

Must be corrected

b

a

c

b

y(a, b, c) =y(a, b, c) = a.b + a.ca.b + a.c

The correct expression

y(a, b, c) =y(a, b, c) = a.ba.b (b (b.c.c))

The incorrectexpression


There is another value besides 1 and 0 ! It does not exist in Digital Logic

It exists in digital electronic implementations

Hi-Z ≡ High-Impedance ≡ Floating ≡ Static voltage

It is observed when there is no connection between two components and the U4 input receives Hi-Z

Hi-Z is interpreted as no value in Digital LogicU1 U2

U3

a

b

a

c

yU4


QUESTIONS ?

Continue reading the Term Project handout

Think about the machine player strategy

Do not leave the lab before your partners finish► Help your partners

Make sure you have the LABS account and see the S driveMake sure you have installed WebPACK 12.4 on your laptop

Make sure you create a CS2204 folder on both

Start thinking about forming teams before leaving the lab

DigitalLogic and

State Machine Design


Today’s Individual Xilinx Work We will experiment with block-based design, especially

block partitioning in the context of a 4-bit 2-to-1 MUX in the Input/Output Block (Block 2)

The 4-bit 2-to-1 MUX is the same as the one studied in class We will test the design on the computer assuming ideal gates

We will enter team information on all schematics Do logic simulations

We will simulate other components to practice more about simulations

We will play the Ppm game on the board We will study the other two versions of the Ppm game :

ppmhvsh and ppmmvsm To understand the playing better To have a better idea about the playing strategy of our machine

player Help our partners complete today’s project We will continue reading the Term Project handout

Also read slides at the end to learn about the software, Project Manager, Schematic design and other related topics


Today’s Individual Xilinx Work (High Level Steps)

1. By using Microsoft and Xilinx create the exp1 project from the termproject project to experiment with the Ppm schematics

2. Open the ppm project in the exp1 folder and analyze the project navigator window

3. Open the schematics and analyze the schematics

Enter team information on the schematics Make sure to save the schematics after the they

are changed !

4. Perform a Xilinx IMPLEMENTATION To generate a new bit file


Today’s Individual Xilinx Work (High Level Steps)5. Study the 4-bit 2-to-1 MUX in the Input/Output Block (Block 2)

in schematic 2 (ppm2.sch) of the term projecta) Take a look at the MUXb) Do logic (functional) simulations

6. Perform other functional simulations to master the Xilinx simulation process

7. Program the FPGA chip Test the Ppm to refresh your memory

Play the game on the FPGA board to refresh your memory

8. Help your partners complete today’s project9. Continue reading the Term Project handout

Study and play the other two types of the Ppm game to think more about the our machine player’s strategy Human vs. human : ppmhvsh Machine vs. machine : ppmmvsm

Think about the playing strategy of the machine player that will be designed Also read slides at the end to learn about the software, Project

Manager, Schematic design and other related topics


Today’s Individual Xilinx Work1. By using Microsoft and Xilinx create the exp1

project from the termproject project to experiment with the Ppm schematics

a) By using Microsoft create the exp1 folder in the CS2204 folder

b) Start the Xilinx ISE software and open the Ppm project in the termproject folder Double click on the Project Navigator icon on your desk

top


Today’s Individual Xilinx Work1. By using Microsoft and Xilinx create the exp1 project from

the termproject project to experiment with the Ppm schematics

Xilinx will show a “Tip of the Day” window in the foreground and the “ISE Project Navigator” window in the background :


Today’s Individual Xilinx Work1. By using Microsoft and Xilinx create the exp1 project from the

termproject project to experiment with the Ppm schematics The ISE opens the last project you worked on by default otherwise

Though this can be changed by changing the Preferences settings If you did not open any Xilinx project, it will not open any project as

you saw on the previous slide and see below Click on OK to close the “Tip of the Day” window :

Note that this window can be turned off by clicking on this :




After the “Tip of the Day” window is closed you will see the following :




Click on Open Project... on the “Start” panel on the left to start opening the term project



termproject project to experiment with the Ppm schematics The “Open Project”window will pop up asking you to select the project

folder which is termproject Select the project folder S;\CS2204\termproject by using typical

Windows operations You will see the partial content of the termproject folder where all seven

folders and the “Xilinx ISE Project” file are shown :



termproject project to experiment with the Ppm schematics Double click on “Xilinx ISE Project” :



termproject project to experiment with the Ppm schematics Xilinx will open the term project in the termproject folder :



termproject project to experiment with the Ppm schematics Xilinx will open the term project in the termproject folder

Click on the pull down menu File and select Copy Project… to have the following window :




Xilinx will open the term project in the termproject folder Enter ppm for the Name;

As you enter ppm, automatically the software enters ppm in Location: and Working directory

We do not want ppm to be the folder name and so we need to change it

Change the Location: entry so that it is S:\CS2204\exp1 As you enter the new path automatically enters the same path to

Working directory



termproject project to experiment with the Ppm schematics Xilinx will open the term project in the termproject folder

After you enter all the information the window will look like the one below After you enter all the necessary information Click OK

It will take a few minutes until the termproject is copied as exp1 project


Today’s Individual Xilinx Work2. Open the ppm project in the exp1 folder and analyze the project

navigator window Click on the pull down menu File and select Open Project…

to have window below Select the project folder S;\CS2204\exp1 by using typical Windows

operations You will see the partial content of the exp1 folder where all seven folders

and the “Xilinx ISE Project” file are shown :



navigator window Double click on “Xilinx ISE Project” :



navigator window Xilinx will open the exp1 project :


Xilinx Projects on the Screen : Three sections are shown when a Xilinx project is open

The left section is a number of tiled panels where the top one is still the “Start” panel



The right section is a single panel which is the “Design Summary” panel



The bottom section is a single panel which is the “Console” panel



The left section is a number of panels tiled where the top one is still the “Start” panel

Click on Close on the left tiled panels until you see the ”Design” panel



The left section is a number of panels tiled where the top one is still the “Start” panel

Click on Close on the left tiled panels until you see the ”Design” panel You will click three times :



The “Design” panel view shows the current “IMPLEMENTATION” of the project :

It shows the hierarchy of the project

The name of the project is ppm

The FPGA chip used is the XC3S500E-5fg320

The name of the schematic file is ppm.sch

The list of all user designed macros (black boxes) with their labels (U125, U152,…) in the schematics

The list shown is not complete !

One has to scroll down !



The “Design” panel view show the current “IMPLEMENTATION” of the project :

It shows the hierarchy of the project

The list of all user designed macros (black boxes) with their labels (U125, U152,…) in the schematics

The list is now complete !

After scrolling down !

The User Constraints File of the project

The User Constraints File allows the project designer to indicate • Which input/output devices (switches, push buttons, LED lights, 7-segment display, the USB controller , flash memory, etc.) are used

• Which pins of the FPGA chip they are connected to




It shows any process running for the project

We will be concerned with only three processes for the project

These three processes are Synthesize Implement Design Generate programming File

We will call these three steps Xilinx IMPLEMENTATION







sign indicates the process has been completed successfully but there are warnings

sign indicates the process has been completed successfully without warnings nor errors

sign indicates that the project has been changed and the process has to be run

sign indicates that the project has an error and has to be corrected

We will these three steps Xilinx IMPLEMENTATION







The goal of these processes is to• Check for errors• Check for potential issues that can cause timing problems• Generate a file, the “bit file,” to program the FPGA chip








If there is one of the two symbols next to the “Generate Programming File” process :

• One can program the FPGA chip : The bit file is ready !• By downloading it to the FPGA chip

The “Generate Programming File” process generates the bit file !








To program the FPGA chip we will use another software package !

We will use ADEPT from Digilent !



The right section is a number of stacked up panels where the top one is the “ISE Design Summary” panel

It summarizes the ppm Project Status




The panel below it is the ISE Design Suite Info Center We will not use this panel much this semester




It summarizes the ppm Project Status It gives a summary of the last Synthesis, Implementation Design and Generate

Programming File steps






The summary shown is not complete !

One has to scroll down !






The summary shown is nowcomplete !

after scrolling down !






We will pay attention to these two entries all the time !






We will pay attention to these two entries all the time !

No Errors65 Warnings



The bottom section is a single panel which is the “Console” panel It shows messages from the ISE Project Navigator



The bottom section is a single panel which is the “Console” panel

It shows messages from the ISE Project Navigator Warnings are in pink with the following symbol in the beginning : Errors are pink with the following symbol in the beginning : All other messages are in black without any symbol !


Today’s Individual Xilinx Work3. Open the schematics and analyze the schematics

Double click on ppm (ppm.sc) to view the six schematics


Today’s Individual Xilinx Work3. Open the schematics and analyze the

schematics Take a look at the six schematics for the six

blocks of the term project• Block 1 : Control Unit• Block 2 : Input/Output• Block 3 : Human Play• Block 4 : Play Check• Block 5 : Points Calculation• Block 6 : Machine Play



Double click on ppm (ppm.sc) to view the six schematics Notice that as the schematic file is open the first schematic sheet is shown

and also the left panel changes to the “Options” panel :

First schematic sheet : Control Unit

First schematic sheet



Click on 2 to the left of the schematic sheet to view the second schematic sheet :

Second schematic sheet : Input/Output Block

Secondschematic sheet



Click on 3 to the left of the schematic sheet to view the third schematic sheet :

Thirdschematic sheet Third

schematic sheet : Human Play Block



Click on 4 to the left of the schematic sheet to view the fourth schematic sheet :

Fourthschematic sheet Fourth

schematic sheet : Play Check Block



Click on 5 to the left of the schematic sheet to view the fifth schematic sheet :

Fifthschematic sheet Fifth

schematic sheet : Points CalculationBlock



Click on 6 to the left of the schematic sheet to view the sixth schematic sheet :

Sixthschematic sheet

Sixthschematic sheet : Machine PlayBlock



schematics There are six schematics !

The Term Project handout discusses the schematics in detail !

We will cover these schematics in detail !



schematics Take a look at the six schematics for the six blocks of

the term project• Blocks 1, 2, 3, 4 and 5 are core blocks

• All of their circuits are given

• Block 6 is completely non-core• Students will replace all the circuits with their own circuits


Today’s Individual Xilinx Lab Work3. Open the schematics and analyze the

schematics Take a look at the six schematics for the six

blocks of the term project• Each block (schematic) consists of subblocks and

subsubblocks• The software identifies each schematic sheet by

automatically assigning it a number• Subblocks and subsubblocks are identified by their

names and distance and lines between them on the schematic sheet

• Common document processor editing rules and key sequences apply to edit schematics


Today’s Individual Xilinx Lab Work3. Open the schematics and analyze the

schematics All components use the same convention

that inputs are on one side and outputs are on the other side There are exceptions like 4-bit ADDers, and

sequential circuits (flip-flops, registers, counters, etc.) that additional inputs are on the remaining two sides as well

Black boxes students will implement (M2 and M3) use the same convention : Inputs are one side Outputs are on the other side


Today’s Individual Xilinx Lab Work3. Open the schematics and analyze the schematics

Enter the team information on the schematics• To enter the team info schematic 1 switch to schematic 1 and

zoom into the lower right corner where project information is shown :



Enter the team information on the schematics• To enter the team info on schematic 1 switch to schematic 1 and

zoom into the lower right corner where project information is shown :

• Right click on the project information object• Select Object Properties• On the NameFieldText row, under value enter the names of the

members of the team• In the Title area enter “ CS 2204 – Your Lab Section – Spring

2014” Place some space before “CS 2204” so that it is not right next

to “Ppm Control Unit”



Enter the team information on the schematics• To enter the team info on schematic 1 switch to schematic 1 and

zoom into the lower right corner where project information is shown

• Save the schematic to record the changes• After you save, the Date area is automatically entered the date

and time the save was done• After you enter all the information, the project information area

in schematic 1 will look like as follows for an imaginary team :



Enter team information on the schematics The Project Navigator window after the schematic is saved is different

where there are symbols next to Synthesis, Implement Design and Generate Programming File steps in the Processes section, signaling that they must be done to incorporate these changes to the design



Enter team information on the schematics Repeat these steps above for the remaining five schematics so that they

all have the same team information The Project Navigator window will still have symbols next to

Synthesis, Implement Design and Generate Programming File steps in the Processes section



Enter team information on the schematics Repeat these steps above for the remaining five schematics so that they

all have the same team information The Project Navigator window will still have symbols next to

Synthesis, Implement Design and Generate Programming File steps in the Processes section

In order to record these changes, we have to save all the schematic and do a synthesis Save the all the schematic Perform a Synthesis operation by double clicking on the

Synthesize – XST process on the Project Navigator panel Switch to the Design Summary panel and notice that there

are 137 warnings We know this due to the fact that we are working on a copied

and pasted project and the ISE is complaining about the file paths Right click and select ReRun on the Synthesize – XST

process on the Project Navigator panel to eliminate the unnecessary warnings

The new number of warnings is 63 as it is the case with the term project and the symbol next to the Synthesize – XST process is


Today’s Individual Xilinx Lab Work4. Perform a Xilinx IMPLEMENTATION

• Xilinx IMPLEMENTATION is required after a schematic is changed• When we indicate IMPLEMENTATION we mean Synthesis,

Implement Design and Generate Programming File steps we see on the Project Navigator window

• Since we changed all the schematics to enter the team info and/or to work on the MUX, we have to do a Xilinx IMPLEMENTATION

• Xilinx IMPLEMENTATIONS are needed for three reasons Catching more errors not discovered via schematic checks

and functional simulations as the software analyzes the schematics

Catching even more errors by doing timing simulations possible after the Xilinx IMPLEMENTATION

Creating a new bit file



• Xilinx IMPLEMENTATION maps the schematics to the FPGA resources (CLBs and wires) If the mapping is complete then there are no errors but

there can be warnings Mapping allows real components to be considered,

hence timing simulations• Xilinx IMPLEMENTATION consists of 3 major steps

• Synthesis to translate the schematic to a netlist file after converting the schematic to a VHDL file

• Implement Design which consists of Translate, Map, Place & Route

Generate Programming File to generate the bit file



Click on Design Summary (out of date) to be able to see number of errors and warnings

Right click on Generate Programming File and select Rerun All We will do the Synthesis, Implement Design and Generate Programming

File steps altogether Even though we already did the synthesis, we will do it again to get

practice on this as we will do it many times Wait until the IMPLEMENTATION completes

If it does not complete, it stops at one of the steps We have to read the errors to read on the Design Summary panel

Once completed, there are no marks next to any one of the steps just performed

See the Project Navigator window on the next slide



The Project Navigatorwindow looks like this after the IMPLEMENTATION is completed successfully :



For the current IMPLEMENTATION we will get 0 Errors 65 6% Slice utilization

Read the warnings by clicking on 65 Warnings on the Design Summary window whether or not the Xilinx IMPLEMENTATION completes

• We often check Design Summary for the warnings and the FPGA utilization

Most warnings we check are in the Synthesis section The FPGA utilization is lower than expected if there

are errors or warnings that must be corrected In Experiment 1, the number of warnings will be 65

this week This number will change next week



The FPGA utilization The term project now has 6% slice utilization : Number of occupied Slices: 282 out of 4656 6%

Now that the Xilinx IMPLEMENTATION is over without errors, the bit file has been generated and can be used to program the FPGA chip We will program the FPGA chip after we complete our

simulations !


Today’s Individual Xilinx Lab Work5. Study the 4-bit 2-to-1 MUX in the Input/Output Block (Block 2)

in schematic 2 of the term projecta) Take a look at the MUX

Switch to Schematic 2 that contains the MUX we want to work on

4-bit 2-to- 1 MUX circuit : DDISP


Today’s Individual Xilinx Lab Work5. Study the 4-bit 2-to-1 MUX in the Input/Output Block

(Block 2) in schematic 2 of the term projecta) Take a look at the MUX

Zoom into the left side of the 7-Segment Digit Content Selection Subsubblock

4-bit 2-to- 1 MUX circuit : DDISP




Zoom into the MUX area

We need a 4-bit 2-to-1 MUX

The MUX determines what to show on the leftmost display :

Display 3 : DISP15 – DISP12

Most significant Player 2 Points digit : P2PT7 – P2PT4

4 bits !

4 bits !




Zoom into the MUX area The operation tableDISPSEL0 Operation

0 DDSIP = DISP

1 DDISP = P2PT

u74_157A 4-bit 2-to-1 MUX

We need a 4-bit 2-to-1 MUX

We do not design it : It hasalready been implemented & it is satisfactory for us


Today’s Individual Xilinx Lab Work5. Study the 4-bit 2-to-1 MUX in the Input/Output

Block (Block 2) of the term projecta) Take a look at the MUX

This MUX is a u74_157 MUX Xilinx does not have it and so it has been designed since

it is a very frequent operation : It is a “user designed block”

That is why all u74_157 blocks are listed on the Design panel

The MUX select input is S If S is 0, it selects the A inputs

The Y outputs are equal to the A inputs If S is 1, it selects the B inputs

The Y outputs are equal to the B inputs




What is the G input ? The G input is another control input which is the enable input If the Enable input is 1, S does not matter, all four outputs are 0 The G input is active low ! The circle (bubble) at the G input indicates it is active low !

4-bit 2-to-1 MUX operation table

S Operation

0 0 Y = A0 1 Y = B

G

1 X Y = 0

S is don’t care



Block (Block 2) in schematic 2 of the term project

a) Take a look at the MUX There is an extra input that disables (zeros) all the

outputs of the MUX if it is 1 : G This is an active-low enable input that controls the whole MUX

► If G is 0, the MUX is enabled and operates as described above

► If G is 1, the MUX is disabled and its four outputs are 0

We do not need this input and so will connect it to the ground permanently




GND ≡ Ground ≡ 0 Volts ≡ 0 The G input is permanently connected to 0 ! Since the Enable is permanently 0, the outputs are always enabled

How DDISP uses the MUX

DISPSEL0 Operation

0 0 DDISP = DISP0 1 DDISP = P2PT

G

1 X DDISP = 0

G = 0 Only these two rows are valid for U80




a) Take a look at the MUX Major operations are not explicit on the previous

operation table Obtain a more detailed operation table

There are four identical major operations : 1-bit 2-to-1 MUXing


S Operation

0 0 Y = A0 1 Y = B

G

1 X Y = 0


S Operation

0 0 Y3=A3, Y2=A2, Y1=A1, Y0=A00 1 Y3=B3, Y2=B2, Y1=B1, Y0=B0

G

1 X Y3=0, Y2=0, Y1=0, Y0=0


Today’s Individual Xilinx Lab Work5. Study the 4-bit 2-to-1 MUX in the

Input/Output Block (Block 2) of the term project

a) Take a look at the MUX Do a Hierarchy Push to see the implementation of

the 4-bit 2-to-1 MUX by Right clicking on the MUX and selecting Symbol ->

Push into Symbol Confirm that it has four 1-bit Xilinx 2-to-1 MUXes See the Xilinx implementation of the 4-bit MUX on

the next slide


Today’s Individual Xilinx Lab Work5. Study the 4-bit 2-to-1 MUX in the Input/Output Block (Block 2)

in schematic 2 of the term projecta) Take a look at the MUX

It is implemented by four Xilinx 1-bit 2-to-1 MUXes


S Operation

0 0 Y3=A3, Y2=A2, Y1=A1, Y0=A0

0 1 Y3=B3, Y2=B2, Y1=B1, Y0=B0

G

1 X Y3=0, Y2=0, Y1=0, Y0=0


Today’s Individual Xilinx Lab Work5. Study the 4-bit 2-to-1 MUX in the

Input/Output Block (Block 2) in schematic 2 of the term project

a) Take a look at the MUX Do another Hierarchy Push to see the

implementation of one of the (1-bit) 2-to-1 MUXes and confirm that it is similar what we discussed in class, except The AND gates have three inputs since the enable

input is connected to the AND gates to control the output

The separate inverter we have in mux2to1 is implemented by a special Xilinx AND gate, AND3B1

► One input of the AND gate is internally inverted

See the Xilinx implementation of the 1-bit MUX on the next slide

Close the two schematics by clicking on the Close Tab buttons on the bottom of the schematic display




a) Take a look at the MUX The implementation of one of the (1-bit) 2-to-1 MUXes by

using gates !




a) Take a look at the MUX The MUX selects between DISP and P2PT The MUX select input is DISPSEL0 (Select Display)

If DISPSEL0 is 0, it selects DISP (Position display) If DISPSEL0 is 1, it selects P2PT (Player 2 points)

The MUX outputs DDSIP DDISP = DISP if DISPSEL0 = 0 DDISP = P2PT if DISPSEL0 = 1




The four 2-to-1 MUXes operate as follows The select input is DISPSEL0 (Select Display) There are two sets of 4-bit data inputs DISP and P2PT There are four outputs named DDSIP If DISPSEL0 is 0, it selects DISP

► The DDISP outputs are equal to the DISP inputs

If DISPSEL0 is 1, it selects P2PT► The DDISP outputs are equal to the P2PT

inputs




a) Take a look at the MUX DISP has four bits labeled as DISP15, DISP14, DISP13 and

DISP12 : Xilinx bus DISP P2PT has four bits labeled as P2PT7, P2PT6, P2PT5 and

P2PT4 : Xilinx bus P2PT DDISP has four bits labeled as DDISP15, DDISP14,

DDISP13 and DDISP12 : Xilinx bus DDISP DDISP15 is either DISP15 or P2PT7 DDISP14 is either DISP14 or P2PT6 DDISP13 is either DISP13 or P2PT5 DDISP12 is either DISP12 or P2PT4



(Block 2) in schematic 2 (ppm2.sch) of the term projectb) Do logic (functional) simulations

We want to see that the MUX is used as 4-bit 2-to-1 MUX such that The MUX select input is DISPSEL0 (Select Display) The MUX outputs four signals named DDISP If DISPSEL0 is 0, it selects DISP

► The DDISP outputs are equal to the DISP inputs

If DISPSEL0 is 1, it selects P2PT► The DDISP outputs are equal to the P2PT

inputs

We will apply inputs and observe the outputs to verify it via simulations Simulation steps are shown starting next slide




b) Do logic (functional) simulations Start functional simulations

Make sure that you have Design panel on the left side :

The MUX we will work on !



(Block 2) in schematic 2 of the term projectb) Do logic (functional) simulations

Start functional simulations Click on Simulation :




b) Do logic (functional) simulations Start functional simulations

You will see that the Processes panel has a new selection : Simulate Behavioral Model (functional simulation)




Start functional simulations Double click on Simulate Behavioral Model to get the following

simulation window :




Start functional simulations Close the Search Results panel on the bottom Other panels will be shown there Close all of them so that the view is as follows :




Start functional simulations The window shows a number of ppm wires and their values at the

moment :

The wire list is already scrolled down




Start functional simulations Scroll all the way up to get the following view :




Start functional simulations There is color coding to stress the values better Orange indicates that the value is U (Uninitialized) Green indicates the value is 0 or 1 Red indicates that the value is X (Strong Unknown)




Start functional simulations There is color coding to stress the values better There are other values one of which is very important : Hi-Z The Hi-Z value is shown as “Z” which will be shown in blue




Start functional simulations Since we want to simulate MUX U80, we need to have the wires that

are the inputs and outputs of the MUX We need to have the following wires on the screen in the order given

below : DISPSEL0 DISP12, DISP13, DISP14, DISP15 P2PT(4), P2PT(5), P2PT(6), P2PT(7) DDISP12, DDISP13, DDISP14, DDISP15


Today’s Individual Xilinx Lab Work5. Study the 4-bit 2-to-1 MUX in the Input/Output Block (Block 2) in

schematic 2 of the term projectb) Do logic (functional) simulations

Start functional simulations On the “Name” panel on the left side the wires are ordered alphabetically Select and Delete wires (by using typical word processing operations) such

that only those that are needed are left on the screen DISPSEL0 DISP12, DISP13, DISP14, DISP15 P2PT(4), P2PT(5), P2PT(6), P2PT(7) DDISP12, DDISP13, DDISP14, DDISP15




Start functional simulations After selecting the needed wires the screen will look like as follows :

P2PT lines are shown as a bus




Start functional simulations We need only the leftmost four bits of P2PT and so right click on the

P2PT[7:0] row and select Expand so that all eight wires are shown :

You can also Expand and Collapse the bus wires by clicking on this triangle




Start functional simulations Pull down outputs lines DDISP12 through DDISP 15 to observe them easily :




Start functional simulations Arrange the wires so that they have the following order :

How DDISP uses the MUX

DISPSEL0 Operation

0 DDISP = DISP

1 DDISP = P2PT

Select input

Select DISP lines when Select is 0

Select P2PT lines when Select is 1

Output DDISP lines




Start functional simulations We will separate the output lines from the inputs to recognize the output lines

easily Right click on P2PT[0] and select New Divider and delete the words New

Divider so that the output rows are separated from the input rows After all these steps, we have the following :




Start functional simulations Click on Restart on the upper tool bar so that the starting time is 0 seconds

Change observation duration time from 1 microseconds to 20 picoseconds by entering 20ps




Start functional simulations We need to assign values to each input so that we can observe the output

values Right click on DISPSEL0 and select Force Constant… The Force Selected Signal window will pop up Enter 0 in the Force to Value entry Click OK




Start functional simulations Assign values to the remaining eight inputs as follows : DISP15 = 1 ; DISP14 = 0 ; DISP13 = 1 ; DISP12 = 0 P2PT = 11110000 where P2PT7 = 1 ; P2PT6 = 1 ; P2PT5 = 1 ; P2PT4 = 1 The assigned values are still not shown on the simulator window :




Click on the icon to do a simulation for 20ps :

The DDISP outputs are equal to the DISP lines since Dispsel0 is 0 :




Assign 1 to DISPSEL0 and simulate again The outputs are equal to the P2PT lines :




Assign different values to the inputs and simulate the circuit until you are comfortable with simulations For example, now have P2PT = 00110000 where P2PT7 = 0 ; P2PT6 = 0 ; P2PT5

= 1 ; P2PT4 = 1 The outputs are still equal to the P2PT lines :




Note that we have done functional (behavioral) simulations where the outputs change instantly (without any delay) In reality outputs change with a delay We will observe the delays when we have timing simulations !


Today’s Individual Xilinx Lab Work6. Perform other functional simulations to master

the Xilinx simulation processa) Simulate the 2-gate circuit in Block 4

• Determine what it does as much as you can ! • That is do an analysis of the circuit• See the next slide


Today’s Individual Xilinx Lab Work6. Perform other functional simulations to master the Xilinx

simulation processa) Simulate the 2-gate circuit in Block 4

• Apply all possible input combinations and observe the outputs• Obtain the truth table of the gate network

• What does the circuit do ? That is, what is its purpose ?

PSEL3 PSEL2 PSEL1 ENCPSEL1 ENCPSEL0

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

Tru

th t

ab

le



the Xilinx simulation processb) Simulate component U65 in Block 1

• Determine what it does as much as you can ! • That is do an analysis of the circuit

Apply all possible input combinations and observe the outputs

Obtain the truth table of the gate network with 8 rows

Hint : Apply inputs so that you have two buses, one is STR and the other

one is S

See the next slide



simulation processa) Simulate component U65 in Block 1

• Apply all possible input combinations and observe the outputs• Obtain the truth table of the gate network

• What does the circuit do ? That is, what is its purpose ?

STR2 STR1 STR0 S6 S5 S4 S3 S2 S1 S0

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

Tru

th t

ab

le



the Xilinx simulation processb) Simulate components U175 and 176 in Block 5

• Determine what it does as much as you can ! • That is do an analysis of the circuit

Apply all possible input combinations and observe the outputs

Obtain the truth table of the gate network with 16 rows

What does it do ? What is its purpose ?msb

lsb



simulation processb) Simulate component U160 in Block 5

• Determine what it does as much as you can ! • That is do an analysis of the circuit• There are more than 4 inputs therefore an operation table is obtained

What does it do ? What is its purpose ?

Obtain an operation table !



simulation processb) Simulate component U149 in Block 4

• Determine what it does as much as you can ! • That is do an analysis of the circuit• There are more than 4 inputs therefore an operation table is

obtained





simulation processb) Simulate Macro 3, M3, in Block 6

• Determine what it does as much as you can ! • That is do an analysis of the circuit• There are more than 4 inputs therefore an operation table is obtained

DISP3-DISP0 : Display 0DISP7-DISP4 : Display 1DISP11-DISP8 : Display 2DISP15-DISP12 : Display 3




Today’s Individual Xilinx Lab Work7. Program the FPGA chip

Test the Ppm to refresh your memory Play the game on the FPGA board to refresh your

memory Download the bit file generated to the FPGA

chip (program the FPGA chip) After a successful download, the four displays

show 0s and the seven LED lights are off


Today’s Individual Xilinx Lab Work8. Help your partners complete today’s

project

9. Continue reading the Term Project handout

Study and play the other two types of the Ppm game to think more about the our machine player’s strategy

Human vs. human : ppmhvsh Machine vs. machine : ppmmvsm

Think about the playing strategy of the machine player that will be designed

Also read slides at the end to learn about the software, Project Manager, Schematic design and other related topics


Understand Critical WiresRD : 4 bits

The random digitR1D : 4 bits

Next random digitR2D : 4 bits

The random digit after next random digitDISP : 16 bits

They represent the four position displays In Hex

DISP15-DISP12 : The leftmost position display, PD3 DISP11-DISP8 : position display PD2, etc

NPDISP : 16 bits The result of RD to each display digit

In Hex NPDISP15-NPDISP12 : The leftmost position, PD3, value + RD NPDISP11-NPDISP8 : Position display PD2 value + RD

NPSELDISP : 4 bits Selects one of NPDISP display values

In Hex


Understand Critical WiresBRWD : 4 bits

Basic reward In Hex

The digit played and also minimum points earned It is selected from RD or NPSELDISP

Based on how the player played : Directly or with an addition

Brwdeqz : 1 bit BRWD is zero when it is 1

PDPRD : 4 bits Display overflow bits after addition

Pdprd : 1 bitThe display overflow bit of the position played

Selplyr : 1 bit The current player

If it is 0, it is the human player, otherwise, it is the machine player


Understand Critical WiresP1SEL : 4 bits

The position played by the human playerP2SEL : 4 bits

The position played by the machine playerPSEL : 4 bits

Position Select bits of current playerENCPSEL : 2 bits

The number of the position playedEQ : 4 bits

The equality of the four displays to the digit playedNSD : 2 bits

The number of similar digits, i.e. the adjacency information of the position played

RWD : 8 bits The regular reward points calculated based on adjacencies

In Unsigned Binary CODERWD : 8 bits

The code reward points calculated based on the code digits In Unsigned Binary


Understand Critical WiresP1PT : 8 bits

Player 1 points In Hex

P2PT : 8 bits Player 2 points

In Hex

PT : 8 bits The points of the current player

In Hex

NPT : 8 bits New player points for the current player

In Hex

Ptovf : 1 bitThe points overflow

if it is 1, the new player points is above (255)10


Understand Critical WiresP1add : 1 bit

Player 1 adds when it is 1

P2add : 1 bit Player 2 adds when it is 1

Add : 1 bit The current player adds when it is 1

P1skip : 1 bit Player 1 skips when it is 1

P2skip : 1 bit Player 2 skips when it is 1

P1played : 1 bit Player 1 has played when it is 1

P2played : 1 bit Player 2 has played when it is 1


Understand Critical WiresDISPSEL : 2 bit

Selects one of four values for displays 00 Selects position displays (displays that RD is played on) 01 Selects player points 10 Selects next two random digits 11 Selects discovered code digits

Add : 1 bitShows that the current player has selected to add

Stp1pt : 1 bit Store Player 1 points

Stp2pt : 1 bit Store Player 2 points

Grd : 1 bit Signals to generate a new random digit

The random digit counter output is stored as P2RD while P2RD and P1RD are shifted to generate the new P1RD and RD

Bpds : 1 bitBlink one or all displays slowly

Bpdf : 1 bitBlocks a display fast after a display overflow


Understand Critical WiresClear : 1 bit

Clear FFs, registers, counters, etc. during reset in Block 2, Block 4 and Block 6 so that it can play again

Clearp2ffs : 1 bit Clears Player 2 FFs, counters and registers

Clff : 1 bit Clears FFs in Block 2 so that the next player can play if there is

no overflowS1 : 1 bit

State 1 where when it is 1, the Ppm is in state 1P2sturn : 1 bit

Signals that Player 2 has the turn It is 1 when the Ppm is in state 4

Sysclk : 1 bit System clock of the operation diagram at 6 Hz

P2clk : 1 bit The clock signal of Player 2 at 48 Hz

Rdclk : 1 bit The random digit counter clock at 192 Hz

lab 3 as you wait for the lab to start : reserve seats for your partners look at the course web...

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