l19 – resolved signals. resolved signals what are resolved signals in systems in vhdl resolution...

L19 – Resolved Signals

Resolved Signals What are resolved signals

In systems In VHDL Resolution – Isn’t that for resolving conflicts?

Ref: text Unit 10, 17, 20

9/2/2012 – ECE 3561 Lect 9

Copyright 2012 - Joanne DeGroat, ECE, OSU 2

9/2/2012 – ECE 3561 Lect 9


Busses and Wires What is the difference between a bus and a wire? Wires – have only one driving source

wires

9/2/2012 – ECE 3561 Lect 9


Busses and Wires Busses, on the other hand,

can be driven by one or more sources

In both cases, wires and busses, there can be more than one destination for the signal

With busses, only the device acting as source will actually drive a value. All others will have their output set at high impedance (Z).

ENB

ENB

ENB

9/2/2012 – ECE 3561 Lect 9


How do you handle Busses in an HDL? First must consider the information present on

a wire and on a bus in a digital circuit. Information present on a wire or bus:

Wire is limited to 2 stable states Using TYPE BIT

High or 1 or ‘1’ Low or 0 or ‘0’

There is a transition period between the two but High and Low are the only 2 stable states.

1/8/2007 - L17 Resolved Siganls


Information on a Bus Possible states for a BUS

Driven high (driven to a 1) Driven low (driven to a 0) No driving value (Z or high impedance) Capacitive high (H) Capacitive low (L) Conflict (one driver driving it to a 1, another a 0) (X) Conflict of capacitive values (W)

And other useful values U – Uninitialized – - a Don’t Care

Type std_logic Std_logic has 9 states

TYPE std_ulogic IS ( ‘u’, --uninitialized ‘x’, --forcing unknown ‘0’, --forcing 0 ‘1’, --forcing 1 ‘Z’, --forcing 0 ‘W’, --weak unknown ‘L’, --weak 0 ‘H’, --weak 1 ‘-’ --don’t care );

9/2/2012 – ECE 3561 Lect 9




In an HDL need Resolution With multiple drivers of a signal how do you

resolve the value seen by devices using the bus?

RESOLUTION How to determine the value when two or more

drivers are driving the same signal Must look at all drivers and determine the

appropriate value to use.



The resolution function function resolved (s : mv4_logic_vector) RETURN mv4_logic IS variable result : mv4_logic := Z; – weakest state BEGIN IF (s’length = 1) then return s(s’low) ELSE FOR i IN s’range LOOP result := resolution_table(result,s(i)); END LOOP; END IF; return result; END resolved;

Execution could be shortened by adding exit when result=‘U’



The big picture(or the little picture) After posting of a

transaction(s) to the current value of one or more of the drivers, a vector composed of the current values of the drivers is sent to the resolution function for determination of the resolved value.

1st Process for a <= equation ….1st Driver for a

CV ‘Z’ t

2nd Process for a <= 2nd equation ….2nd Driver for a

CV ‘0’ t

nth Process for a <= nth equation ….nth Driver for a

CV ‘Z’ t

* * *

ResolvedValue



Completeness of a MVL package Having a MVL type with resolution is only

part of creating a MVL system. ALSO need

Overloaded function for standard operators Type conversion functions to convert from other

type to this type and the reverse ieee_1164 standard MVL package is a

standard package for a multi-value logic system and contains all of these.



Use of Resolved signals Must use a resolved signal

type for any signals of mode INOUT PORT ( ABUS : INOUT

mv4r_logic; …

Within an ARCHITECTURE they are needed whenever the signal will have more than one driver

ARCHITECTURE abcd OF wxyz IS … SIGNAL a,b,c : mv4r_logic; …BEGIN a <= ‘0’, ‘1’ after 10 ns, ‘0’ after 20 ns;

p1: process begin a <= ‘Z’; wait … end process;

p2: process begin a <= ‘0’; wait … end process;END abcd;

Driver 1 of a

Driver 2 of a

Driver 3 of a



Standard logic 1164 Package is online in the

course directory but not on the course webpage

Opens with comments on the code

What is the first part of declaring an MVL system in a package?

-- -------------------------------------------------------------------- -- -- Title : std_logic_1164 multi-value logic system -- Library : This package shall be compiled into a library -- : symbolically named IEEE. -- : -- Developers: IEEE model standards group (par 1164) -- Purpose : This packages defines a standard for designers -- : to use in describing the interconnection data types -- : used in vhdl modeling. -- : -- Limitation: The logic system defined in this package may -- : be insufficient for modeling switched transistors, -- : since such a requirement is out of the scope of this -- : effort. Furthermore, mathematics, primitives, -- : timing standards, etc. are considered orthogonal -- : issues as it relates to this package and are therefore -- : beyond the scope of this effort. -- : -- Note : No declarations or definitions shall be included in, -- : or excluded from this package. The "package declaration" -- : defines the types, subtypes and declarations of -- : std_logic_1164. The std_logic_1164 package body shall be -- : considered the formal definition of the semantics of -- : this package. Tool developers may choose to implement -- : the package body in the most efficient manner available -- : to them. -- : -- -------------------------------------------------------------------- -- modification history : -- -------------------------------------------------------------------- -- version | mod. date:| -- v4.200 | 01/02/92 | -- --------------------------------------------------------------------



Declaration Part of the Package Declare MVL logic

system types Declare the resolution

function Declare the resolved

type And declare the array

types for vectors Declare subtype of

reduced logic systems

PACKAGE std_logic_1164 IS ------------------------------------------------------------------- -- logic state system (unresolved) ------------------------------------------------------------------- TYPE std_ulogic IS ( 'U', -- Uninitialized 'X', -- Forcing Unknown '0', -- Forcing 0 '1', -- Forcing 1 'Z', -- High Impedance 'W', -- Weak Unknown 'L', -- Weak 0 'H', -- Weak 1 '-' -- Don't care ); ------------------------------------------------------------------- -- unconstrained array of std_ulogic for use with the resolution function ------------------------------------------------------------------- TYPE std_ulogic_vector IS ARRAY ( NATURAL RANGE <> ) OF std_ulogic; ------------------------------------------------------------------- -- resolution function ------------------------------------------------------------------- FUNCTION resolved ( s : std_ulogic_vector ) RETURN std_ulogic; ------------------------------------------------------------------- -- *** industry standard logic type *** ------------------------------------------------------------------- SUBTYPE std_logic IS resolved std_ulogic; ------------------------------------------------------------------- -- unconstrained array of std_logic for use in declaring signal arrays ------------------------------------------------------------------- TYPE std_logic_vector IS ARRAY ( NATURAL RANGE <>) OF std_logic; ------------------------------------------------------------------- -- common subtypes ------------------------------------------------------------------- SUBTYPE X01 IS resolved std_ulogic RANGE 'X' TO '1'; -- ('X','0','1') SUBTYPE X01Z IS resolved std_ulogic RANGE 'X' TO 'Z'; -- ('X','0','1','Z') SUBTYPE UX01 IS resolved std_ulogic RANGE 'U' TO '1'; -- ('U','X','0','1') SUBTYPE UX01Z IS resolved std_ulogic RANGE 'U' TO 'Z'; -- ('U','X','0','1','Z')



Overload operators All operators are

overloaded Can find the package in

~degroat/ee762_assign/std_1164.vhd

------------------------------------------------------------------- -- overloaded logical operators ------------------------------------------------------------------- FUNCTION "and" ( l : std_ulogic; r : std_ulogic ) RETURN UX01; FUNCTION "nand" ( l : std_ulogic; r : std_ulogic ) RETURN UX01; FUNCTION "or" ( l : std_ulogic; r : std_ulogic ) RETURN UX01; FUNCTION "nor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01; FUNCTION "xor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01; -- function "xnor" ( l : std_ulogic; r : std_ulogic ) return ux01; FUNCTION "not" ( l : std_ulogic ) RETURN UX01; ------------------------------------------------------------------- -- vectorized overloaded logical operators ------------------------------------------------------------------- FUNCTION "and" ( l, r : std_logic_vector ) RETURN std_logic_vector; FUNCTION "and" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector; FUNCTION "nand" ( l, r : std_logic_vector ) RETURN std_logic_vector; FUNCTION "nand" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector; FUNCTION "or" ( l, r : std_logic_vector ) RETURN std_logic_vector; FUNCTION "or" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector; FUNCTION "nor" ( l, r : std_logic_vector ) RETURN std_logic_vector; FUNCTION "nor" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector; FUNCTION "xor" ( l, r : std_logic_vector ) RETURN std_logic_vector; FUNCTION "xor" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector; -- ----------------------------------------------------------------------- -- Note : The declaration and implementation of the "xnor" function is -- specifically commented until at which time the VHDL language has been -- officially adopted as containing such a function. At such a point, -- the following comments may be removed along with this notice without -- further "official" ballotting of this std_logic_1164 package. It is -- the intent of this effort to provide such a function once it becomes -- available in the VHDL standard. -- ----------------------------------------------------------------------- -- function "xnor" ( l, r : std_logic_vector ) return std_logic_vector; -- function "xnor" ( l, r : std_ulogic_vector ) return std_ulogic_vector; FUNCTION "not" ( l : std_logic_vector ) RETURN std_logic_vector; FUNCTION "not" ( l : std_ulogic_vector ) RETURN std_ulogic_vector;



Type conversion functions and edge detection To convert from built

in logic types of BIT and BIT_VECTOR

And there are similar conversion functions for the reduced logic systems

Also have functions for rising and falling edge

------------------------------------------------------------------- -- conversion functions ------------------------------------------------------------------- FUNCTION To_bit ( s : std_ulogic; xmap : BIT := '0') RETURN BIT; FUNCTION To_bitvector ( s : std_logic_vector ; xmap : BIT := '0') RETURN BIT_VECTOR; FUNCTION To_bitvector ( s : std_ulogic_vector; xmap : BIT := '0') RETURN BIT_VECTOR; FUNCTION To_StdULogic ( b : BIT ) RETURN std_ulogic; FUNCTION To_StdLogicVector ( b : BIT_VECTOR ) RETURN std_logic_vector; FUNCTION To_StdLogicVector ( s : std_ulogic_vector ) RETURN std_logic_vector; FUNCTION To_StdULogicVector ( b : BIT_VECTOR ) RETURN std_ulogic_vector; FUNCTION To_StdULogicVector ( s : std_logic_vector ) RETURN std_ulogic_vector;

------------------------------------------------------------------- -- edge detection ------------------------------------------------------------------- FUNCTION rising_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN; FUNCTION falling_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN;



Now have the package body Starts with a header First code is for the

resolution function

Note initial state Note sink state

Sink state is state that overrides all others

PACKAGE BODY std_logic_1164 IS ------------------------------------------------------------------- -- local types ------------------------------------------------------------------- TYPE stdlogic_1d IS ARRAY (std_ulogic) OF std_ulogic; TYPE stdlogic_table IS ARRAY(std_ulogic, std_ulogic) OF std_ulogic; ------------------------------------------------------------------- -- resolution function ------------------------------------------------------------------- CONSTANT resolution_table : stdlogic_table := ( -- --------------------------------------------------------- -- | U X 0 1 Z W L H - | | -- --------------------------------------------------------- ( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U | ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X | ( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ), -- | 0 | ( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ), -- | 1 | ( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ), -- | Z | ( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X' ), -- | W | ( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ), -- | L | ( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ), -- | H | ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | - | ); FUNCTION resolved ( s : std_ulogic_vector ) RETURN std_ulogic IS VARIABLE result : std_ulogic := 'Z'; -- weakest state default BEGIN -- the test for a single driver is essential otherwise the -- loop would return 'X' for a single driver of '-' and that -- would conflict with the value of a single driver unresolved -- signal. IF (s'LENGTH = 1) THEN RETURN s(s'LOW); ELSE FOR i IN s'RANGE LOOP result := resolution_table(result, s(i)); END LOOP; END IF; RETURN result; END resolved;



The various functions The AND table The OR table

------------------------------------------------------------------- -- tables for logical operations ------------------------------------------------------------------- -- truth table for "and" function CONSTANT and_table : stdlogic_table := ( -- ---------------------------------------------------- -- | U X 0 1 Z W L H - | | -- ---------------------------------------------------- ( 'U', 'U', '0', 'U', 'U', 'U', '0', 'U', 'U' ), -- | U | ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | X | ( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | 0 | ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 1 | ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | Z | ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | W | ( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | L | ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | H | ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ) -- | - | ); -- truth table for "or" function CONSTANT or_table : stdlogic_table := ( -- ---------------------------------------------------- -- | U X 0 1 Z W L H - | | -- ---------------------------------------------------- ( 'U', 'U', 'U', '1', 'U', 'U', 'U', '1', 'U' ), -- | U | ( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | X | ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 | ( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | 1 | ( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | Z | ( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | W | ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L | ( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | H | ( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ) -- | - | );



For operation on single logic values and vectors Single values and

vectors

------------------------------------------------------------------- -- overloaded logical operators ( with optimizing hints ) ------------------------------------------------------------------- FUNCTION "and" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS BEGIN RETURN (and_table(l, r)); END "and"; FUNCTION "nand" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS BEGIN RETURN (not_table ( and_table(l, r))); END "nand"; FUNCTION "or" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS BEGIN RETURN (or_table(l, r)); END "or";

------------------------------------------------------------------- -- and ------------------------------------------------------------------- FUNCTION "and" ( l,r : std_logic_vector ) RETURN std_logic_vector IS ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l; ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r; VARIABLE result : std_logic_vector ( 1 TO l'LENGTH ); BEGIN IF ( l'LENGTH /= r'LENGTH ) THEN ASSERT FALSE REPORT "arguments of overloaded 'and' operator are not of the same length" SEVERITY FAILURE; ELSE FOR i IN result'RANGE LOOP result(i) := and_table (lv(i), rv(i)); END LOOP; END IF; RETURN result; END "and"; --------------------------------------------------------------------- FUNCTION "and" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l; ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r; VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH ); BEGIN IF ( l'LENGTH /= r'LENGTH ) THEN ASSERT FALSE REPORT "arguments of overloaded 'and' operator are not of the same length" SEVERITY FAILURE; ELSE FOR i IN result'RANGE LOOP result(i) := and_table (lv(i), rv(i)); END LOOP; END IF; RETURN result; END "and";

Using std_logic in a design Create a bus driver and then set up 3 units

driving the bus. Only 1-bit data. As 3 units have 3 control signals that control driving the data onto the bus line, drive1, drive2, drive3.

Again start with the HDL code.

9/2/2012 – ECE 3561 Lect 9


The HDL code for the bus driver LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all; ENTITY busdr IS PORT (drive : IN std_logic; data : IN std_logic; intbus : OUT std_logic); END busdr;

ARCHITECTURE one OF busdr IS BEGIN PROCESS (drive,data) BEGIN IF (drive='1') THEN intbus <= data; ELSE intbus <= 'Z'; END IF; END PROCESS; END one;

9/2/2012 – ECE 3561 Lect 9


Notes on using std_logic First you must make the VHDL design library

visible to the design unit. This is done with the LIBRARY clause. If the clause is before the ENITY then the

Library is visible to the ENTITY and all ARCHITECTURES of the ENTITY If it were before the ARCHITECTURE then the

library is visible only to that ARCHITECTURE

9/2/2012 – ECE 3561 Lect 9


The USE clause To use the declarations, functions, and

procedures of a package you must give access to them. This is done through a USE clause which has same visibility rules as LIBRARY clause.

USE library.packagename.all provides access to all the declarations of the PACKAGE declarative part.

9/2/2012 – ECE 3561 Lect 9


Back to bus driver Make std_logic useable Bus driver interface

Data input Bus connection Drive control – when

asserted data driven onto bus – otherwise Z

ARCHITECTURE implements behavior.

Done with an if statement in a PROCESS

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all; ENTITY busdr IS PORT (drive : IN std_logic; data : IN std_logic; intbus : OUT std_logic); END busdr;

ARCHITECTURE one OF busdr IS BEGIN PROCESS (drive,data) BEGIN IF (drive='1') THEN intbus <= data; ELSE intbus <= 'Z'; END IF; END PROCESS; END one;

9/2/2012 – ECE 3561 Lect 9


Using the bus driver Connect multiple

sources than can generate information

Here 3 drivers of the bus.

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all; ENTITY mdrv IS PORT (intbus : INOUT std_logic); END mdrv;

ARCHITECTURE one OF mdrv IS COMPONENT busdr IS PORT (drive : IN std_logic; data : IN std_logic; intbus : OUT std_logic); END COMPONENT; FOR all : busdr USE ENTITY work.busdr(one); --internal signals SIGNAL dr1,dr2,dr3 : std_logic; SIGNAL data1,data2,data3 : std_logic; BEGIN u1 : busdr PORT MAP (dr1,data1,intbus); u2 : busdr PORT MAP (dr2,data2,intbus); u3 : busdr PORT MAP (dr3,data3,intbus); END one;

9/2/2012 – ECE 3561 Lect 9


And then synthesize it in Quartis What does an FPGA tool do with this?

9/2/2012 – ECE 3561 Lect 9


data

driveintbus

data

driveintbus

data

driveintbus

BUF (DIRECT)

0

0

0

0

0

0

intbusbusdr:u3

busdr:u1

busdr:u2 comb~[2..0]

The results 3 single bit driving units

connect to one bus line

Within the 3 boxes in the top figure you have a tristate driver.

9/2/2012 – ECE 3561 Lect 9


data

driveintbus

data

driveintbus

data

driveintbus

BUF (DIRECT)

0

0

0

0

0

0

intbusbusdr:u3

busdr:u1

busdr:u2 comb~[2..0]

IO_BUF (TRI)

intbusdrive (GND)

data (GND) intbus

Keys to having Quartis work Project has name pnm Top level VHDL file is pnm.vhdl In the VHDL code it is “ENTITY pnm IS …”

9/2/2012 – ECE 3561 Lect 9


Extending the one bit to 8 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all; ENTITY busdr IS PORT (drive : IN std_logic; data : IN std_logic_vector(7 downto

0); intbus : OUT std_logic_vector(7

downto 0)); END busdr;

ARCHITECTURE one OF busdr IS BEGIN PROCESS (drive,data) BEGIN IF (drive='1') THEN intbus <= data; ELSE intbus <= "ZZZZZZZZ"; END IF; END PROCESS; END one;

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all; ENTITY mdrv IS PORT (intbus : INOUT std_logic_vector(7 downto 0)); END mdrv;

ARCHITECTURE one OF mdrv IS COMPONENT busdr8 IS PORT (drive : IN std_logic; data : IN std_logic_vector(7 downto 0); intbus : OUT std_logic_vector(7 downto 0)); END COMPONENT; FOR all : busdr8 USE ENTITY work.busdr(one); --internal signals SIGNAL dr1,dr2,dr3 : std_logic; SIGNAL data1,data2,data3 : std_logic_vector(7 downto

0); BEGIN u1 : busdr8 PORT MAP (dr1,data1,intbus); u2 : busdr8 PORT MAP (dr2,data2,intbus); u3 : busdr8 PORT MAP (dr3,data3,intbus); END one;

9/2/2012 – ECE 3561 Lect 9


Notes on extension The only change was to

the data and bus size – from single bit to 8-bits

9/2/2012 – ECE 3561 Lect 9


drive

data[7..0]intbus[7..0]

0

drive


0

drive


0

BUF (DIRECT)

busdr:u1

8' h00 --

busdr:u2

8' h00 --

busdr:u3

8' h00 --

comb~[23..0]

intbus[7..0]

IO_BUF (TRI)

intbus[7..0]

intbus[7..0]

drive (GND)

data[7..0]

D QPRE

ENA

CLR

dataout[7..0]~reg0

loaddatain[7..0] dataout[7..0]

Now adding a register The register HDL code

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all; ENTITY reg8 IS PORT (datain : IN std_logic_vector(7 downto 0); load : IN std_logic; dataout : OUT std_logic_vector(7 downto 0)); END reg8;

ARCHITECTURE one OF reg8 IS BEGIN PROCESS (datain,load) BEGIN IF (load='1' AND load'event) THEN dataout <= datain; END IF; Synthesis results: END PROCESS; LUTS – 0 Registers – 8 Pins – 17 END one;

9/2/2012 – ECE 3561 Lect 9


Putting them together Now desire to add the register to the bus

driver Need 3 segments of VHDL code

Code for the registers

9/2/2012 – ECE 3561 Lect 9


Register code LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all; ENTITY reg8 IS PORT (datain : IN std_logic_vector(7 downto 0); load : IN std_logic; dataout : OUT std_logic_vector(7 downto 0)); END reg8;

ARCHITECTURE one OF reg8 IS

BEGIN PROCESS (datain,load) BEGIN IF (load='1' AND load'event) THEN dataout <= datain; END IF; END PROCESS; END one;

9/2/2012 – ECE 3561 Lect 9


Bus driver code LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all; ENTITY busdr IS PORT (drive : IN std_logic; data : IN std_logic_vector(7 downto 0); intbus : OUT std_logic_vector(7 downto 0)); END busdr;

ARCHITECTURE one OF busdr IS BEGIN PROCESS (drive,data) BEGIN IF (drive='1') THEN intbus <= data; ELSE intbus <= "ZZZZZZZZ"; END IF; END PROCESS; END one;

9/2/2012 – ECE 3561 Lect 9


The total code – 3 instances reg8 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all; ENTITY regmdrv8 IS PORT (intbus : INOUT std_logic_vector(7 downto

0)); END regmdrv8;

ARCHITECTURE one OF regmdrv8 IS COMPONENT busdr8 IS PORT (drive : IN std_logic; data : IN std_logic_vector(7 downto 0); intbus : OUT std_logic_vector(7 downto 0)); END COMPONENT; FOR all : busdr8 USE ENTITY work.busdr8(one); COMPONENT reg8 IS PORT (datain : IN std_logic_vector(7 downto 0); load : IN std_logic; dataout : OUT std_logic_vector(7 downto 0)); END COMPONENT; FOR all : reg8 USE ENTITY work.reg8(one);

--internal signals SIGNAL l1,l2,l3 : std_logic; SIGNAL dr1,dr2,dr3 : std_logic; SIGNAL data1,data2,data3 :

std_logic_vector(7 downto 0); SIGNAL datai1,datai2,datai3 :

std_logic_vector(7 downto 0); BEGIN u1 : busdr8 PORT MAP

(dr1,data1,intbus); u2 : busdr8 PORT MAP

(dr2,data2,intbus); u3 : busdr8 PORT MAP

(dr3,data3,intbus); r1 : reg8 PORT MAP (datai1,l1,data1); r2 : reg8 PORT MAP (datai2,l1,data2); r3 : reg8 PORT MAP (datai3,l1,data3); END one;

9/2/2012 – ECE 3561 Lect 9


Quartis results Registers with bus drivers

9/2/2012 – ECE 3561 Lect 9


drive


0

drive


drive


load

datain[7..0]dataout[7..0]

0

load


0

load


0

BUF (DIRECT)

0

0

busdr8:u1reg8:r1

8' h00 --

reg8:r2

8' h00 --

reg8:r3

8' h00 --

comb~[23..0]

intbus[7..0]

busdr8:u3

busdr8:u2

D QPRE

ENA

CLR

datain[7..0] dataout[7..0]load (GND)

dataout[7..0]~reg0

IO_BUF (TRI)

drive (GND)

data[7..0] intbus[7..0]

intbus[7..0]

The objective Dual ported register set

2 data busses Can load or drive either

bus No timing – only control

To insure this unit will synthesize need to do it subcomponent by subcomponent and structurally.

9/2/2012 – ECE 3561 Lect 9


Reg 0

Reg 1

Reg 2

Reg 15

A BUS

BBUS

AregNo Aload Adrive

BregNo Bload Bdrive

Lecture summary TYPE std_logic Using std_logic to build into creating a

register set

Next step – class input???

9/2/2012 – ECE 3561 Lect 9


l19 – resolved signals. resolved signals what are resolved signals in systems in vhdl resolution...

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