keynote 3: spin torque mram is ready for applications today · 2018-08-14 · keynote 3: spin...
TRANSCRIPT
Keynote 3: Spin Torque MRAM Is
Ready for Applications Today
Spin Torque MRAM: Today and Tomorrow
– Daniel Worledge, IBM Research –
Implementation in IBM FlashCore Modules
– Brent Yardley, IBM Systems –
MRAM Developer Day 2018
Santa Clara, CA 1
Daniel Worledge, IBM Research 8/6/18 p2 MRAM Developer Day © 2018 IBM
Daniel Worledge, G. Hu, J. J. Nowak, D. Houssameddine, J. Bak, S. L. Brown, B.
Doris, D. Edelstein, M. G. Gottwald, P. Hashemi, Q. He, D. Jeong, J. Kim, C.
Kothandaraman, G. Lauer, H K Lee, N. Marchack, E. O’Sullivan, M. Reuter, R. P.
Robertazzi, J. Z. Sun, T. Suwannasiri, P. L. Trouilloud, and Y. Zhu
IBM-Samsung MRAM Alliance, IBM TJ Watson Research Center, Yorktown Heights, New York
Outline
• Key Advances in Spin Torque MRAM
• Applications: Today & Future
• Future Technology: What is possible in 2 – 5 years
Spin Torque MRAM: Today and Tomorrow
Daniel Worledge, IBM Research 8/6/18 p3 MRAM Developer Day © 2018 IBM
Magnetic Tunnel
Junction
Spin Transfer
Torque
MgO Tunnel
Barriers
Perpendicular
Magnetization
Daniel Worledge, IBM Research 8/6/18 p4 MRAM Developer Day © 2018 IBM
MRAM Applications
Standalone Embedded Non-volatile Embedded Cache
• Lower temp process is OK
• 4 - 256 Mb and up
• 10 - 50 ns read/write
• High endurance (1010 - 1017)
• 400C process required
• 1 kb – 16 Mb
• Relaxed performance requirement
• Endurance: 106 writes/bitKe
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• Replace battery-backed SRAM
• Buffer for hard disk drive
• Replace DRAM
• Fast dense memory for L3
cache
• Alternative to eDRAM
• 400C process required
• 4 - 256 Mb and up
• 1 - 2 ns read/write
• Unlimited endurance (1019)
• Non-volatile memory for:
• Microcontroller program code
• Encryption key storage
• Trimming and calibration
Increasing difficulty
Daniel Worledge, IBM Research 8/6/18 p5 MRAM Developer Day © 2018 IBM
Increasing difficulty
MRAM Applications
Standalone Embedded Non-volatile Embedded Cache
• Lower temp process is OK
• 4 - 256 Mb and up
• 10 - 50 ns read/write
• High endurance (1010 - 1017)
• 400C process required
• 1 kb – 16 Mb
• Relaxed performance requirement
• Endurance: 106 writes/bitKe
y r
eq
uire
me
nts
A
pp
lica
tio
n e
xa
mp
les
• Replace battery-backed SRAM
• Buffer for hard disk drive
• Replace DRAM
• Fast dense memory for L3
cache
• Alternative to eDRAM
• 400C process required
• 4 - 256 Mb and up
• 1 - 2 ns read/write
• Unlimited endurance (1019)
• Non-volatile memory for:
• Microcontroller program code
• Encryption key storage
• Trimming and calibration
Mobile embedded
Replace SRAM for low performance,
low power applications
• Wearable electronics
• Co-processors
• Internet of Things
• 400C process required
• 1 ~ 64 Mb
• 10 ns read/write
• Unlimited endurance (1018)
Daniel Worledge, IBM Research 8/6/18 p6 MRAM Developer Day © 2018 IBM
Technology options for faster writing
3 Terminal2 Terminal
• 3 terminal devices may enable new physics ideas for faster switching
• Spin orbit torques, voltage control of magnetic anisotropy
• But, 3 terminal devices require 2 transistors not dense enough
• Focus on improving 2 terminal devices
Daniel Worledge, IBM Research 8/6/18 p7 MRAM Developer Day © 2018 IBM
First Demonstration of Reliable Spin Torque Writing
• Every bit has a probability of a write error, on every write cycle inherent to spin torque
• 498 devices, 120 nm diameter. 100 ns pulses. External field Hoffset = 28 Oe applied.
• No anomalous switching at 10-2 – 10-3 level like that seen for in-plane junctions.
D. C. Worledge, et al., IEDM 2010.
Daniel Worledge, IBM Research 8/6/18 p8 MRAM Developer Day © 2018 IBM
First Demonstration of Reliable Spin Torque Writing
D. C. Worledge, et al., IEDM 2010.
• Compare to previous in-plane results
• ‘Ballooning’
Tai Min, et al., IEEE Trans. Mag. 46, 2322 (2010).
Daniel Worledge, IBM Research 8/6/18 p9 MRAM Developer Day © 2018 IBM
Reliable 10 ns writing is possible now
• 256 devices, 39 nm diameter, 10 ns pulses, no external field, Rmin = 6.6 kΩ, Eb = 63 kT, Ic1e-6 = 83 uA
• Compared to 2010 IEDM paper: 10x faster, 4x lower power, 4x denser, 7x larger Hc
Daniel Worledge, IBM Research 8/6/18 p10 MRAM Developer Day © 2018 IBM
Scaling down to 11 nm
• Spin torque physics works well down to 11 nm
• WER = 7e-10 demonstrated in 7.5 uA
• Write current scales well with area
J. J. Nowak, et al., IEEE Mag. Lett., 7, 3102604 (2016)
Daniel Worledge, IBM Research 8/6/18 p11 MRAM Developer Day © 2018 IBM
Concept of Double Magnetic Tunnel Junction (DMTJ)
Double MTJ Structure
Free Layer
Top Reference
Layer
Bottom Reference
Layer
Tunnel Barrier I
Tunnel Barrier II
Free Layer
Bottom Reference
Layer
Tunnel Barrier I
Single MTJ Structure
• Torque from both interfaces reduce Ic by 2x
• Must set reference layers anti-parallel
Daniel Worledge, IBM Research 8/6/18 p12 MRAM Developer Day © 2018 IBM
DMTJ Patterned Device Switching Performance
Junction Size [nm]
Eb/I
c0
[kBT
/μA
]
• DMTJ shows ~2x improvement in switching efficiency.
• Write error rate down to 5x10-10 was demonstrated in DMTJ devices with 20 ns write pulse.
Switching efficiency Write-error-rate
Daniel Worledge, IBM Research 8/6/18 p13 MRAM Developer Day © 2018 IBM
What can we expect over the next 2 – 5 years?
• Higher densities: 1 Gb – 4 Gb for standalone
• Due to: smaller devices, lower write current, more efficient materials & devices
• Faster writing: 10 ns soon, then maybe 5 ns. Faster than 5 ns is tough.
• Faster write than read?
• Embedded with higher temperature operation: 150 C
• No fundamental reason MRAM cannot operate at 250 C!
Keynote 3: Spin Torque MRAM Is Ready
for Applications Today
Implementation in IBM FCMs
Brent Yardley
MRAM Developer Day 2018
Santa Clara, CA 14
IBM FlashSystem – A Different Approach…
▪ FlashSystem MicroLatency Modules are a
custom form factor and rely on the system for
power loss protection…
▪ How do we take this design, implement an
improved feature set, using a more broadly
adopted form factor?
8/6/2018 15
Introducing The IBM FlashCore Module
• Built in, performance neutral hardware compression and encryption
• Using 64 layer 3DTLC NAND
• Enterprise data reliability
• Cognitive Algorithms for Wear Levelling, Health binning, Heat segregation and media management
• Intelligent media management that keeps settings idealto keep performance consistent.
• Endurance without latency penalty
• FIPS 140 certification
4.8TBu, 9.6TBu, 19.2TBu capacity options with up to 3:1 compression
IBM FlashCoreTM technology delivers key differentiators
FCMs Implement Everspin’s STT-MRAM
▪ Technology BER and Endurance meets FCM
design requirements
• Component level qualification approved and
validated by IBM component teams
▪ Meets performance requirements with
persistence
• Solves the power loss use case
and data retention requirements8/6/2018 17
IBM FCM Design Features / Uses
▪ STT-MRAM• Write Cache / Data Buffer / Streams
• Journaling / Logs
▪ FPGA• Agile Development
▪ 64 Layer 3DTLC NAND• Higher Usable Capacity
▪ NVMe Interface• 2x2 Gen 3 / Gen 4 capable
8/6/2018 18