june 2005computer architecture, background and motivationslide 1 part i background and motivation
TRANSCRIPT
June 2005 Computer Architecture, Background and Motivation Slide 1
Part IBackground and
Motivation
June 2005 Computer Architecture, Background and Motivation Slide 2
I Background and Motivation
Topics in This Part
Chapter 1 Combinational Digital Circuits
Chapter 2 Digital Circuits with Memory
Chapter 3 Computer System Technology
Chapter 4 Computer Performance
Provide motivation, paint the big picture, introduce tools:• Review components used in building digital circuits• Present an overview of computer technology• Understand the meaning of computer performance (or why a 2 GHz processor isn’t 2 as fast as a 1 GHz model)
June 2005 Computer Architecture, Background and Motivation Slide 3
1 Combinational Digital Circuits
First of two chapters containing a review of digital design:• Combinational, or memoryless, circuits in Chapter 1• Sequential circuits, with memory, in Chapter 2
Topics in This Chapter
1.1 Signals, Logic Operators, and Gates
1.2 Boolean Functions and Expressions
1.3 Designing Gate Networks
1.4 Useful Combinational Parts
1.5 Programmable Combinational Parts
1.6 Timing and Circuit Considerations
June 2005 Computer Architecture, Background and Motivation Slide 4
1.1 Signals, Logic Operators, and Gates
Figure 1.1 Some basic elements of digital logic circuits, with operator signs used in this book highlighted.
x y
AND Name XOR OR NOT
Graphical symbol
x y
Operator sign and alternate(s)
x y x y xy
x y
x x or x
_
x y or xy Arithmetic expression
x y 2xy x y xy 1 x
Output is 1 iff: Input is 0
Both inputs are 1s
At least one input is 1
Inputs are not equal
June 2005 Computer Architecture, Background and Motivation Slide 5
Variations in Gate Symbols
Figure 1.2 Gates with more than two inputs and/or with inverted signals at input or output.
OR NOR NAND AND XNOR
June 2005 Computer Architecture, Background and Motivation Slide 6
Gates as Control Elements
Figure 1.3 An AND gate and a tristate buffer act as controlled switches or valves. An inverting buffer is logically the same as a NOT gate.
Enable/Pass signal e
Data in x
Data out x or 0
Data in x
Enable/Pass signal e
Data out x or “high impedance”
(a) AND gate for controlled transfer (b) Tristate buffer
(c) Model for AND switch.
x
e
No data or x
0
1 x
e
ex
0
1 0
(d) Model for tristate buffer.
June 2005 Computer Architecture, Background and Motivation Slide 7
Wired OR and Bus Connections
Figure 1.4 Wired OR allows tying together of several controlled signals.
e
e
e Data out (x, y, z, or high
impedance)
(b) Wired OR of t ristate outputs
e
e
e
Data out (x, y, z, or 0)
(a) Wired OR of product terms
z
x
y
z
x
y
z
x
y
z
x
y
June 2005 Computer Architecture, Background and Motivation Slide 8
Control/Data Signals and Signal Bundles
Figure 1.5 Arrays of logic gates represented by a single gate symbol.
/ 8
/
8 / 8
Compl
/ 32
/ k
/ 32
Enable
/ k
/ k
/ k
(b) 32 AND gates (c) k XOR gates (a) 8 NOR gates
June 2005 Computer Architecture, Background and Motivation Slide 9
1.2 Boolean Functions and Expressions
Ways of specifying a logic function
Truth table: 2n row, “don’t-care” in input or output
Logic expression: w (x y z), product-of-sums, sum-of-products, equivalent expressions
Word statement: Alarm will sound if the door is opened while the security system is engaged, or when the smoke detector is triggered
Logic circuit diagram: Synthesis vs analysis
June 2005 Computer Architecture, Background and Motivation Slide 10
Table 1.2 Laws (basic identities) of Boolean algebra.
Name of law OR version AND versionIdentity x 0 = x x 1 = x
One/Zero x 1 = 1 x 0 = 0
Idempotent x x = x x x = x
Inverse x x = 1 x x = 0
Commutative x y = y x x y = y x
Associative (x y) z = x (y z) (x y) z = x (y z)
Distributive x (y z) = (x y) (x z) x (y z) = (x y) (x z)
DeMorgan’s (x y) = x y (x y) = x y
Manipulating Logic Expressions
June 2005 Computer Architecture, Background and Motivation Slide 11
Proving the Equivalence of Logic Expressions
Example 1.1
Truth-table method: Exhaustive verification
Arithmetic substitution x y = x + y xy x y = x + y 2xy
Case analysis: two cases, x = 0 or x = 1
Logic expression manipulation
Example: x y ? x y x y x + y – 2xy ? (1 – x)y + x(1 – y) – (1 – x)yx(1 – y)
June 2005 Computer Architecture, Background and Motivation Slide 12
1.3 Designing Gate Networks
AND-OR, NAND-NAND, OR-AND, NOR-NOR
Logic optimization: cost, speed, power dissipation
(a) AND-OR circuit
z
x y
x
y z
(b) Intermediate circuit
(c) NAND-NAND equivalent
z
x y
x
y z z
x y
x
y z
Figure 1.6 A two-level AND-OR circuit and two equivalent circuits.
(x y) = x y
June 2005 Computer Architecture, Background and Motivation Slide 13
BCD-to-Seven-Segment Decoder
Example 1.2
Figure 1.8 The logic circuit that generates the enable signal for the lowermost segment (number 3) in a seven-segment display unit.
x 3 x 2 x 1 x 0
Signals to enable or turn on the segments
4-bit input in [0, 9] e 0
e 5
e 6
e 4
e 2
e 1
e 3
1
2 4
5
0
3
6
June 2005 Computer Architecture, Background and Motivation Slide 14
1.4 Useful Combinational Parts
High-level building blocks
Much like prefab parts used in building a house
Arithmetic components will be covered in Part III (adders, multipliers, ALUs)
Here we cover three useful parts: multiplexers, decoders/demultiplexers, encoders
June 2005 Computer Architecture, Background and Motivation Slide 15
Multiplexers
Figure 1.9 Multiplexer (mux), or selector, allows one of several inputs to be selected and routed to output depending on the binary value of a
set of selection or address signals provided to it.
x
x
y
z
1
0
x
x
z
y
x x
y
z
1
0
y
/ 32
/ 32
/ 32 1
0
1
0
3
2
z
y 1 0
1
0
1
0
y 1
y 0
y 0
(a) 2-to-1 mux (b) Switch view (c) Mux symbol
(d) Mux array (e) 4-to-1 mux with enable (e) 4-to-1 mux design
0
1
y
1 1
1
0
0 0
x x x x
1 0
2
3
x
x
x
x
0
1
2
3
z
e (Enable)
June 2005 Computer Architecture, Background and Motivation Slide 16
Decoders/Demultiplexers
Figure 1.10 A decoder allows the selection of one of 2a options using an a-bit address as input. A demultiplexer (demux) is a decoder that
only selects an output if its enable signal is asserted.
y 1 y 0
x 0
x 3
x 2
x 1
1
0
3
2
y 1 y 0
x 0
x 3
x 2
x 1 e
1
0
3
2
y 1 y 0
x 0
x 3
x 2
x 1
(a) 2-to-4 decoder (b) Decoder symbol (c) Demultiplexer, or decoder with “enable”
(Enable)
June 2005 Computer Architecture, Background and Motivation Slide 17
Encoders
Figure 1.11 A 2a-to-a encoder outputs an a-bit binary number
equal to the index of the single 1 among its 2a inputs.
(a) 4-to-2 encoder (b) Encoder symbol
x 0
x 3
x 2
x 1
y 1 y 0
1
0
3
2
x 0
x 3
x 2
x 1
y 1 y 0
June 2005 Computer Architecture, Background and Motivation Slide 18
1.5 Programmable Combinational Parts
Programmable ROM (PROM)
Programmable array logic (PAL)
Programmable logic array (PLA)
A programmable combinational part can do the job of many gates or gate networks
Programmed by cutting existing connections (fuses) or establishing new connections (antifuses)
June 2005 Computer Architecture, Background and Motivation Slide 19
PROMs
Figure 1.12 Programmable connections and their use in a PROM.
. . .
.
.
.
Inputs
Outputs
(a) Programmable OR gates
w
x
y
z
(b) Logic equivalent of part a
w
x
y
z
(c) Programmable read-only memory (PROM)
De
cod
er
June 2005 Computer Architecture, Background and Motivation Slide 20
PALs and PLAs
Figure 1.13 Programmable combinational logic: general structure and two classes known as PAL and PLA devices. Not shown is PROM with
fixed AND array (a decoder) and programmable OR array.
AND array (AND plane)
OR array (OR
plane)
. . .
. . .
.
.
.
Inputs
Outputs
(a) General programmable combinational logic
(b) PAL: programmable AND array, fixed OR array
8-input ANDs
(c) PLA: programmable AND and OR arrays
6-input ANDs
4-input ORs
June 2005 Computer Architecture, Background and Motivation Slide 21
1.6 Timing and Circuit Considerations
Gate delay : a fraction of, to a few, nanoseconds
Wire delay, previously negligible, is now important (electronic signals travel about 15 cm per ns)
Circuit simulation to verify function and timing
Changes in gate/circuit output, triggered by changes in its inputs, are not instantaneous
June 2005 Computer Architecture, Background and Motivation Slide 22
Glitching
Figure 1.14 Timing diagram for a circuit that exhibits glitching.
x = 0
y
z
a = x y
f = a z 2 2
Using the PAL in Fig. 1.13b to implement f = x y z
June 2005 Computer Architecture, Background and Motivation Slide 23
CMOS Transmission Gates
Figure 1.15 A CMOS transmission gate and its use in building
a 2-to-1 mux.
z
x
x
0
1
(a) CMOS transmission gate: circuit and symbol
(b) Two-input mux built of two transmission gates
TG
TG TG
y
P
N