jtag environment full chip testing

1 JTAG course - Dolev Eyal

JTAG environmentJTAG environment Full Chip testingFull Chip testing


Test Logic Architecture Test Logic Architecture

In the following presentation we will discuss the In the following presentation we will discuss the needs and means for the creation of a JTAG dft needs and means for the creation of a JTAG dft environment. environment. – Within the chipWithin the chip

– Outside of the chipOutside of the chip

The environment is designed for:The environment is designed for:– RTL block testingRTL block testing

– Creating the patterns for the testersCreating the patterns for the testers

– Gate-level testingGate-level testing

– FPGA testingFPGA testing

– Silicon testingSilicon testing



Basically making a complicated testing seem Basically making a complicated testing seem so simple from the outsideso simple from the outside



The following elements shall compose the test The following elements shall compose the test logic architecture within the chip:logic architecture within the chip:

– A TAPA TAP

– A TAP controllerA TAP controller

– An instruction registerAn instruction register

– A group of test data registersA group of test data registers


Test Access Port - TAPTest Access Port - TAP

The TAP is a general-purpose port that can provide The TAP is a general-purpose port that can provide access to many test support functions built into a access to many test support functions built into a component.component.

It is composed as a minimum of the three input It is composed as a minimum of the three input connections and one output connection.connections and one output connection.

An optional fourth input connection provides for An optional fourth input connection provides for asynchronous initialization.asynchronous initialization.


TAP connections TAP connections

Test clock input (TCK)Test clock input (TCK)– Provides the clock for the test logic.Provides the clock for the test logic.

– Stored-state devices in the test logic shall retain their state Stored-state devices in the test logic shall retain their state indefinitely when the signal applied to TCK is stopped at 0.indefinitely when the signal applied to TCK is stopped at 0.

Test mode select input (TMS)Test mode select input (TMS)– This signal is decoded to the TAP controller to control test This signal is decoded to the TAP controller to control test

operations.operations.

– Shall be sampled on the rising edge of TCK.Shall be sampled on the rising edge of TCK.

Test data input (TDI)Test data input (TDI)– Serial test instruction and data.Serial test instruction and data.

– Shall be sampled on the rising edge of TCK.Shall be sampled on the rising edge of TCK.


TAP connections TAP connections continue…continue…

Test data out (TDO)Test data out (TDO)– Serial output for test instruction and data.Serial output for test instruction and data.

– Changes in the state of the signal driven through TDO shall Changes in the state of the signal driven through TDO shall occur only on the falling edge of TCK.occur only on the falling edge of TCK.

Test reset input (TRST*)Test reset input (TRST*)– Provides for asynchronous initialization of the TAP controller.Provides for asynchronous initialization of the TAP controller.

– Active low.Active low.


Interconnection of components compatible Interconnection of components compatible with the standardwith the standard

The figures on the next slide illustrate three The figures on the next slide illustrate three alternative board-level interconnections of alternative board-level interconnections of components conforming to IEEE Std 1149.1-components conforming to IEEE Std 1149.1-2001 standard.2001 standard.


Interconnection of components compatible Interconnection of components compatible with the standardwith the standard

Serial connection using one TMS signalSerial connection using one TMS signal

Connection in two paralleled serial chainsConnection in two paralleled serial chains Multiple independent paths with common Multiple independent paths with common TMS and TCK signalsTMS and TCK signals


Test Logic Architecture Test Logic Architecture Top level design - figuresTop level design - figures

Clock and/or controlsClock and/or controls

A conceptual schematic of test logicA conceptual schematic of test logic



The following elements shall be contained in The following elements shall be contained in the test logic architecture within the chip :the test logic architecture within the chip :

– A TAPA TAP

– A TAP controllerA TAP controller

– An instruction registerAn instruction register

– A group of test data registersA group of test data registers


The full chip - The full chip - Communication chip exampleCommunication chip example

The full chip top

PERIPHERYTHERMAL

SensorCCM

COMMONP

CI

CLOCK_RESET_COMM

GIO

DNW_MNG

GHOST

FLEEP

RMII Pass

Through

LAN_PORT

MACPHY_GLUE

CAR ARBELCLK_WRAP

EEPROM LOGIC STAT REGS

TARGET LOGIC

MAC CORERX FILTER

DMATX

LED STRECH

XTX

DMA TX

MAC_TX

MAC_RXDMA RX

CB

GHOST i/f

Target i/f

GHOST i/f

MNG-LAN

Target i/f

FLEEP i/f

FLEEP i/f

CB

IO RING GLUE (DFT,Jtag,BSCAN) IO Buff

ARCsubsys

DMARX

MNG-HOST

PBCBQ

CB HDR

CB HDR

LAN_PORT

MACPHY_GLUE

CARclk


TARGET LOGIC

MAC CORERX FILTER

DMATX

LED STRECH

XTX

DMA TX

MAC_TX

MAC_RXDMA RX

CB

CB

DMARX

PBCBQ

CB HDR

CB HDR

MNG-HOST

MNG-LAN

SGMII

SGMII

ULT_WRAP

PHY

PHY

SerDes /SGMII

SerDes /SGMII

PERIPHERYCLOCK_RESETDFT pins IO RING GLUE (DFT,Jtag,BSCAN) IO Buff


TAP Functional Overview TAP Functional Overview

Compiles with the IEEE Std 1149.1 (“JTAG”) test Compiles with the IEEE Std 1149.1 (“JTAG”) test architecture standard architecture standard

additionally provides access to most of the full chip additionally provides access to most of the full chip testability features testability features

provides not only a customer-visible feature of the chip provides not only a customer-visible feature of the chip but also provides crucial proprietary functionality for but also provides crucial proprietary functionality for silicon debug and production testing silicon debug and production testing


Inside the Chip JTAG FSMInside the Chip JTAG FSM

The JTAG commands are 6 bit words chosen according The JTAG commands are 6 bit words chosen according to the IEEE standard and the test you want the JTAG to to the IEEE standard and the test you want the JTAG to cover. cover. For example:For example:

The controller must implement the IEEE standard FSM. The controller must implement the IEEE standard FSM. For example:For example:

Using the JTAG commands we issue instructions to the Using the JTAG commands we issue instructions to the correct test/action we want to activate.correct test/action we want to activate.

– BS,BIST,DAT and so on…BS,BIST,DAT and so on…


The TAP controllerThe TAP controller

The TAP state machine



The TAP controller is a synchronous finite state machine that responds to changes at the TMS and TCK signals of the TAP and controls the sequence of operations of the circuitry.




All state transitions of All state transitions of the TAP controller shall the TAP controller shall occur based on the value occur based on the value of TMS at the time of a of TMS at the time of a rising edge of TCK.rising edge of TCK.

Actions of the test logic Actions of the test logic (instruction register, test (instruction register, test data registers, etc.) shall data registers, etc.) shall occur on either the rising occur on either the rising or the falling edge of TCK or the falling edge of TCK in each controller state.in each controller state.



The TAP state machineThe TAP state machine

ContainsContains– Reset stateReset state

– Run-test/idle stateRun-test/idle state

– Two major branchesTwo major branches– Access to the TAP Access to the TAP

instruction registerinstruction register

– Access to one of the Access to one of the TAP/core data registersTAP/core data registers

TMS pin is used as the TMS pin is used as the controlling input.controlling input.





Test-Logic-ResetTest-Logic-Reset– Test logic disabledTest logic disabled– Normal operation of the Normal operation of the

processor can continue.processor can continue.– Enters this state:Enters this state:

– When the TMS input is held When the TMS input is held active for at least five clocks.active for at least five clocks.

– When TRST_N is pulled When TRST_N is pulled active.active.

– Upon power-up.Upon power-up.

Test-Logic-Reset

maximum of 5 clocks

with TMS signal hold

at 1'b1TMS=1'b1

asynchronousTRST_N

asynchronouslan_pwrgood




Run-Test/IdleRun-Test/Idle– The idle state of the TAP The idle state of the TAP

controller.controller.– The contents of all test data The contents of all test data

registers retain their registers retain their previous values.previous values.

– Self tests may run.Self tests may run.

Shift-DR-ScanShift-DR-Scan– Temporary controller state.Temporary controller state.

Shift-IR-ScanShift-IR-Scan– Temporary controller state.Temporary controller state.




Capture-IRCapture-IR– The shift register The shift register

contained in the contained in the instruction register loads a instruction register loads a fixed value. (two lsb are 01)fixed value. (two lsb are 01)

– Test data registers Test data registers selected by the current selected by the current instruction retain their instruction retain their previous state.previous state.

– The instruction does not The instruction does not change.change.

IR branchIR branch



Shift-IRShift-IR– The shift register The shift register

contained in the contained in the Instruction Register is Instruction Register is connected between TDI connected between TDI and TDO and is shifted one and TDO and is shifted one stage toward its serial stage toward its serial output on each rising edge output on each rising edge of TCK. of TCK.

– The output arrives at TDO The output arrives at TDO on the falling edge of TCK.on the falling edge of TCK.

– The current instruction The current instruction does not change in this does not change in this state.state.


IR branchIR branch



Exit1-IRExit1-IR– a temporary state. a temporary state. – TMS held high – the TMS held high – the

controller enters Update-IR controller enters Update-IR which terminates the which terminates the scanning process.scanning process.



Pause-IRPause-IR– Allows shifting of the Allows shifting of the

Instruction Register to be Instruction Register to be temporarily halted.temporarily halted.

– The current instruction does The current instruction does not change in this state.not change in this state.

IR branchIR branch



Exit2-IRExit2-IR– a temporary state. a temporary state. – TMS held high – the TMS held high – the

controller enters Update-IR controller enters Update-IR which terminates the which terminates the scanning process.scanning process.



IR branchIR branch




Update-IRUpdate-IR– The instruction which has The instruction which has

been shifted into the been shifted into the Instruction Register is Instruction Register is latched onto the parallel latched onto the parallel output of the Instruction output of the Instruction Register on the falling Register on the falling edge of TCK.edge of TCK.

IR branchIR branch




Capture-DRCapture-DR– Data may be parallel-loaded Data may be parallel-loaded

into test data registers into test data registers selected by the current selected by the current instruction (on the rising instruction (on the rising edge of TCK).edge of TCK).


DR branchDR branch



Shift-DRShift-DR– The Data Register The Data Register

connected between TDI connected between TDI and TDO as a result of and TDO as a result of selection by the current selection by the current instruction is shifted one instruction is shifted one stage toward its serial stage toward its serial output on each rising edge output on each rising edge of TCK.of TCK.

– The output arrives at TDO The output arrives at TDO on the falling edge of TCK. on the falling edge of TCK.

– The parallel, latched output The parallel, latched output of the selected Data of the selected Data Register does not change Register does not change while new data is being while new data is being shifted in.shifted in.


DR branchDR branch



Exit1-DRExit1-DR– a temporary state. a temporary state. – TMS held high – the TMS held high – the

controller enters Update-controller enters Update-DR which terminates the DR which terminates the scanning process.scanning process.



Pause-DRPause-DR– Allows shifting of the Allows shifting of the

Instruction Register to be Instruction Register to be temporarily halted.temporarily halted.


DR branchDR branch



Exit2-DRExit2-DR– a temporary state. a temporary state. – TMS held high – the TMS held high – the

controller enters Update-controller enters Update-DR which terminates the DR which terminates the scanning process.scanning process.



DR branchDR branch




Update-DRUpdate-DR– Data from the shift register Data from the shift register

path is loaded into the path is loaded into the latched parallel outputs of latched parallel outputs of the selected Data Register the selected Data Register (if applicable) on the falling (if applicable) on the falling edge of TCK.edge of TCK.

– This (and Test-Logic-This (and Test-Logic-Reset) are the only Reset) are the only controller states in which controller states in which the latched paralleled the latched paralleled outputs of a data register outputs of a data register can change.can change.

DR branchDR branch


Test logic operationTest logic operation

Instruction scan

Test-Logic-reset

Run-Test/Idle

Select-DR-Scan

Select-IR-Scan

Capture-IR

Shift-IR

Exit1-IR

Pause-IR

Exit2-IR

Update-IR


TAP registersTAP registers

Allows an instruction to be shifted into the design.Allows an instruction to be shifted into the design. The instruction is used to select the test to be The instruction is used to select the test to be

performed or the test data register to be accessed or performed or the test data register to be accessed or both. both.

The instruction registerThe instruction register

Actual Instruction Register

Shift Register

Ir_ltch_out

Shift Register

(MSB) (LSB)

TDOTDI

Cupture_irShift_irTst_lgc_rst

Update_irTst_lgc_rst



This register consists of 6 bit shift register and the This register consists of 6 bit shift register and the actual instruction register.actual instruction register.

The parallel output of the TAP instruction register goes The parallel output of the TAP instruction register goes to the TAP instruction decoder .to the TAP instruction decoder .


(a) Capture-IR (b) Shift-IR (c) Update-IR

Operation of the TAP Instruction registerOperation of the TAP Instruction register



In Capture-IR, the shift register portion of the In Capture-IR, the shift register portion of the instruction register is loaded in parallel with the fixed instruction register is loaded in parallel with the fixed value “NOP”.value “NOP”.

In Shift-IR, the shift register portion of the instruction In Shift-IR, the shift register portion of the instruction register forms a serial data path between TDI and TDO.register forms a serial data path between TDI and TDO.

In Update-IR, the shift register contents are latched in In Update-IR, the shift register contents are latched in parallel into the actual instruction register. parallel into the actual instruction register.



The chip TopThe chip Top

Every Chip has a Top layer which contains all it’s IO Every Chip has a Top layer which contains all it’s IO pins (functional and testing)pins (functional and testing)

The IO pins change their functionality from one feature The IO pins change their functionality from one feature to another. to another.

In order to test the full chip we wrap this top with our In order to test the full chip we wrap this top with our own new top – AV top. Where we can control the JTAG own new top – AV top. Where we can control the JTAG IO pins and check the other IO pinsIO pins and check the other IO pins


AV TopAV Top

The full chip top

PERIPHERYTHERMAL

SensorCCM

COMMONP

CI

CLOCK_RESET_COMM

GIO

DNW_MNG

GHOST

FLEEP

RMII Pass

Through

LAN_PORT

MACPHY_GLUE

CAR ARBELCLK_WRAP


TARGET LOGIC

MAC CORERX FILTER

DMATX

LED STRECH

XTX

DMA TXMAC_TX

MAC_RXDMA RX

CB

GHOST i/f

Target i/f

GHOST i/f

MNG-LAN

Target i/f

FLEEP i/f

FLEEP i/f

CB

IO RING GLUE (DFT,Jtag,BSCAN) IO Buff

ARCsubsys

DMARX

MNG-HOST

PBCBQ

CB HDR

CB HDR

LAN_PORT

MACPHY_GLUE

CARclk


TARGET LOGIC

MAC CORERX FILTER

DMATX

LED STRECH

XTX

DMA TXMAC_TX

MAC_RXDMA RX

CB

CB

DMARX

PBCBQ

CB HDR

CB HDR

MNG-HOST

MNG-LAN

SGMII

SGMII

ULT_WRAP

PHY

PHY

SerDes /SGMII

SerDes /SGMII

AV TopAV Top

TCKTMSTDITDO

IO pins


Chip external dft environmentChip external dft environment

Chip_dftChip_dft

Jtag_stubJtag_stub dft_utilsdft_utils dft_strapsdft_straps dft_testsdft_testsdft_signalsdft_signals

basic dft basic dft operations:operations:

Writing a Writing a JTAG JTAG

command, command, reading the reading the output …output …

Different Different utils utils

neededneeded

Strap utils: Strap utils: powering powering

up, z up, z straps, straps, clock clock

bypassing bypassing ……

Connecting Connecting the signals the signals threw Hw threw Hw

pathspaths

The tests!! The tests!! Block/FC Block/FC

teststests


Creating the patternsCreating the patterns

After testing and approving the validity of the design on After testing and approving the validity of the design on RTL we create patterns of 1 & 0 for each pin in the RTL we create patterns of 1 & 0 for each pin in the proper time.proper time.

We use the patterns for the Gate level testing and the We use the patterns for the Gate level testing and the silicon debug.silicon debug.

TDI: 800ns – 1 850ns – 1 870ns – 0

….


Testing the Gate level & siliconTesting the Gate level & silicon

Using the JTAG device along with the patterns as Using the JTAG device along with the patterns as inputs for the 4 (or 5) access ports for before and after inputs for the 4 (or 5) access ports for before and after silicon validation.silicon validation.


Questions??Questions??

jtag environment full chip testing

Documents