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Field Programmable Port Extender (FPX) 1
JPEG Processing Modules forReal-Time Decoding and Recoding
Chris Neely
Washington University, Applied Research Lab
June 19, 2002
Supported by: NSF
http://www.arl.wustl.edu/arl/projects/fpx
Field Programmable Port Extender (FPX) 2
Outline
• Introduction• Motivation of JPEG
Recoder Module• JPEG Encoding Concepts• FPX JPEG Recoder
• Up to N coefficients• Block Diagram• Image Results• Thumbnail size Images• Network Configuration
Hardware Synthesis
Field Programmable Port Extender (FPX) 3
Hardware JPEG Application
• FPX Video Recoder ModuleThis module was implemented to adjust the bandwidth of MotionJPEG video midway through the network. Control cells are sent tospecify the number of coefficients to drop on eachluminance/chrominance channel (YCbCr).
Field Programmable Port Extender (FPX) 4
Motivation for JPEG Recoding
MMXMMX
NTSC
NTSC
JPEG Compressed VideoVideo
Monitor
Network
FPX
Field Programmable Port Extender (FPX) 5
Motivation for JPEG Recoding
MMXMMX
NTSC
NTSC
Video
Monitor
Network
FPX
Congestion Flashes or No Video
Field Programmable Port Extender (FPX) 6
Motivation for JPEG Recoding
MMXMMX
NTSC
NTSC
Video
Monitor
Network
FPX
Recoded Video ReducesDownstream Bandwidth
Video continues to playbut with less detail
Congestion
Field Programmable Port Extender (FPX) 7
FDCT JPEG entropy encoder
Table Specifications
Quantizer
Table Specifications
CompressedImageData
JPEG Encoder – 4 Step Process
31 24
SourceImageData
JPEG Encoder – 4 Step Process
Field Programmable Port Extender (FPX) 8
JPEG Encoding Concepts
• First, encode the information that is the most valuableto human perception.
• Convert from RGB to a luminance chrominancerepresentation to preserve the luminance becausethat is considered valuable.
• Divide into 8x8 block computational units becausethey are small and efficient for processing.
• The human eye functions like a low pass filter, soencode low spatial frequencies with more accuracythan high frequencies.
Field Programmable Port Extender (FPX) 9
JPEG Encoding Concepts
• The compression ratio is controlled by varying thequantization tables. Fewer/smaller coefficients afterquantization means greater compression.
• Use variable length representations for data thatassign as few bits as possible to frequently occurringdata patterns (entropy encoding).
• 0xFF Marker codes indicate the start and end ofimages.
Field Programmable Port Extender (FPX) 10
Raw ATM cells containing RAW JPEG
Motion JPEG Input Cell Format:
0xFFE0 = Start of ImageAAL0 Cell Header
Network Data format for Motion-JPEG Video
Field Programmable Port Extender (FPX) 11
JPEG Video Recoder Design
ByteStuffer
EntropyDecoder
Convert toThumbnail
Control CellProcessor
Bit SerialEgress
EntropyRecoder
JPEG_MODULE
OutputController
Field Programmable Port Extender (FPX) 12
This pattern begins by mapping thethe value at the lowest spatialfrequency, the DC coefficient.
The first AC coefficient is next.
Now the Zig-Zag pattern
The last values to be coded are thosethat relate to the highest spatialfrequencies.
4.1. Follow Zig-Zag Coding SequenceData Order is a Zig-Zag Sequence
0 1 5 6 14 15 27 28
2 4 7 13 16 26 29 42
3 8 12 17 25 30 41 43
9 11 18 24 31 40 44 53
10 19 23 32 39 45 52 54
20 22 33 38 46 51 55 60
21 34 37 47 50 56 59 61
35 36 48 49 57 58 62 63
Increasing Horizontal Frequency
Incr
ea
sing
Ve
rtic
alF
req
uenc
y
Field Programmable Port Extender (FPX) 13
The Huffman table for theVariable Length Codedescribes therun-length pairs: the zero-run and thenumber of zeros in the integer.
4.1. Follow Zig-Zag Coding SequenceHuffman Variable Length Code Tables
Run/Sz Co_len Co_wrd0/0 2 00/1 3 20/2 3 30/3 3 40/4 3 50/5 3 60/6 4 e0/7 5 1e0/8 6 3e0/9 7 7e0/A 8 fe0/B 9 1fe
Run/Sz Co_len Co_wrd0/0 4 a0/1 2 00/2 2 10/3 3 4
…F/6 16 fffaF/7 16 fffbF/8 16 fffcF/9 16 fffdF/A 16 fffe
Field Programmable Port Extender (FPX) 14
TheVariable Length Integers can be up to 11 bits for the DC component and 10 bitsfor the AC component.
4.1. Follow Zig-Zag Coding SequenceVariable Length Integers
Integer Value-1,1
-3,-2, 2, 3-7..-4, 4..7
-15..-8, 8..15-31..-16, 16..31-63..-32, 32..63
-127..-64, 64..127-255..-128, 128..255-511..-256, 256..511
-1023..-512, 512..1023
Number of bits123456789
10
VLI Representation0, 1
00, 01, 10, 11000..011, 100..111
0000..0111, 1000..111100000..01111, 10000..11111
000000..011111, 100000..1111110000000..0111111, 1000000..1111111
00000000..01111111, 10000000..11111111000000000..011111111, 100000000..111111111
0000000000..0111111111, 1000000000..1111111111
Field Programmable Port Extender (FPX) 15
Entropy Decoder Module
• Bit-serial shift register– Bit-serial data-in– Identifies 0xFFEx marker control codes– Removes byte stuffing (0xFF00)– If (vlc_state = ‘1’), then shifts overflow to VLC register
for lookup operation– If (vli_state = ‘1’), then shifts overflow to store VLI
based on lookup result• Variable length data output
– VLI (up to 11 bits) is reverse-sign extended to a fixed12 bit output
– VLC (up to 16 bits) is padded with zeros to a fixed 16bit output
• 4 Huffman Code Tables implemented asCombinational Logic
Field Programmable Port Extender (FPX) 16
Entropy Decoder Module
Huffman TableSpecifications
Combinational Logic
DataENDATA
LUM_CHR_H
RESET_L, CLK
HUFF_TBL_SEL
Serial Shift Reg.
DecoderFSM
SAMP_MODE
VLC_OUTVLI_OUTPOSITION_OUTBLOCK_NUM_OUT
SOI_OUTEOI_OUTEOB_OUTMCU_OUTVLC_OUTVLI_OUTEVEN_FIELD_L
111110110 0000 1111111110100111
VLC VLI
1 First shift register is not full yet.
Field Programmable Port Extender (FPX) 17
Entropy Decoder Module
Huffman TableSpecifications
Combinational Logic
DataENDATA
LUM_CHR_H
RESET_L, CLK
HUFF_TBL_SEL
Serial Shift Reg.
DecoderFSM
SAMP_MODE
VLC_OUTVLI_OUTPOSITION_OUTBLOCK_NUM_OUT
SOI_OUTEOI_OUTEOB_OUTMCU_OUTVLC_OUTVLI_OUTEVEN_FIELD_L
111110110 0000 1111111110100111
VLC VLI
1111101100000111
AC value (Zero Run = 1, Bits = 4)
Filled first shift register, soshifting overflow to VLC
Field Programmable Port Extender (FPX) 18
Entropy Decoder Module
Huffman TableSpecifications
Combinational Logic
DataENDATA
LUM_CHR_H
RESET_L, CLK
HUFF_TBL_SEL
Serial Shift Reg.
DecoderFSM
SAMP_MODE
VLC_OUTVLI_OUTPOSITION_OUTBLOCK_NUM_OUT
SOI_OUTEOI_OUTEOB_OUTMCU_OUTVLC_OUTVLI_OUTEVEN_FIELD_L
VLC VLI
1111011000001111 1
111110110 0000 1111111110100111
Doing Lookup on VLCon each shift.
Field Programmable Port Extender (FPX) 19
Entropy Decoder Module
Huffman TableSpecifications
Combinational Logic
DataENDATA
LUM_CHR_H
RESET_L, CLK
HUFF_TBL_SEL
Serial Shift Reg.
DecoderFSM
SAMP_MODE
VLC_OUTVLI_OUTPOSITION_OUTBLOCK_NUM_OUT
SOI_OUTEOI_OUTEOB_OUTMCU_OUTVLC_OUTVLI_OUTEVEN_FIELD_L
VLC VLI
0000111111111010 11110110
1111101100000 1111111110100111
Found VLC = “11110110”AC value (Zero Run = 1, Bits = 4)
Field Programmable Port Extender (FPX) 20
Entropy Decoder Module
Huffman TableSpecifications
Combinational Logic
DataENDATA
LUM_CHR_H
RESET_L, CLK
HUFF_TBL_SEL
Serial Shift Reg.
DecoderFSM
SAMP_MODE
VLC_OUTVLI_OUTPOSITION_OUTBLOCK_NUM_OUT
SOI_OUTEOI_OUTEOB_OUTMCU_OUTVLC_OUTVLI_OUTEVEN_FIELD_L
VLC VLI
0001111111110100 0
1111101100000 1111111110100111
Find VLI of size 4 bits.
Field Programmable Port Extender (FPX) 21
Entropy Decoder Module
Huffman TableSpecifications
Combinational Logic
DataENDATA
LUM_CHR_H
RESET_L, CLK
HUFF_TBL_SEL
Serial Shift Reg.
DecoderFSM
SAMP_MODE
VLC_OUTVLI_OUTPOSITION_OUTBLOCK_NUM_OUT
SOI_OUTEOI_OUTEOB_OUTMCU_OUTVLC_OUTVLI_OUTEVEN_FIELD_L
VLC VLI
1111111110100111 0000
11111011000001111111110100111
Found VLI = “0000”,Integer = -15.
Field Programmable Port Extender (FPX) 22
Symmetric Entropy FSM
(hit = '1' & SSSS > 0)K += R
block_num++
block_num++
LUM_DC_VLC
IDLE
LUM_DC_VLI
LUM_AC_VLC LUM_AC_VLI
(hit = '1' & SSSS >0)
(vli_done ='1')(hit = '1' & SSSS = 0)
(hit = '1' & SSSS > 0)K += R
(R = 0)?
(hit = '1' & SSSS = 0)
Y
N(R = 15)?
Y
N
K += 16
(vli_done = '1')
(K = 63)?
K++
N
Y
CHR_DC_VLC CHR_DC_VLI
CHR_AC_VLC CHR_AC_VLI
(hit = '1' & SSSS >0)
(vli_done ='1')(hit = '1' & SSSS = 0)
(R = 0)?
(hit = '1' & SSSS = 0)
Y
N(R = 15)?
Y
N
K += 16
(vli_done = '1')
(K = 63)?
K++
N
Y
(SOI = '1')
End of ImageMarker
(EOI = '1')
Decoded all MCULuminance
Blocks?
Y
N
Decoded both MCUChrominance
Blocks?
Y
N
block_num++
block_num++
Start of ImageMarker
Error
(error_h = '1')
mcu_blip <= '1'
// Build VLC and Do Huffman Table lookupcodeword <= code_word(15 downto 0) & buf_val(15)code_length++
1* 2*
1*
2*
2*
1*
2*1*
2* =
1* =
// Build VLI based on the SSSS saved from Huffman lookupinteger_val <= integer_val(8 downto 0) & buf_val(15)integer_length++
LumDC_VLCLumDC_VLI
LumAC_VLC
LumAC_VLI
ChrDC_VLC
ChrDC_VLI
ChrAC_VLC
ChrAC_VLI
Field Programmable Port Extender (FPX) 23
Entropy Recoder Module
DataENDATA
RESET_L, CLK
Shift Register (32 bits data with 32 bits overflow)
SOI_INEOI_IN
EOB_INLUM_CHR_H
Position_KN_coeff_reqVLC_ReadyVLC_valueVLI_ReadyVLI_value
EVEN_FIELD_LHUF_TBL_SEL
Recoder FSM shift_ptr
11110110
Found VLC = “11110110”AC value (Zero Run = 1, Bits = 4)
Is the coefficient position <= N?
Field Programmable Port Extender (FPX) 24
Entropy Recoder Module
DataENDATA
RESET_L, CLK
Shift Register (32 bits data with 32 bits overflow)
SOI_INEOI_IN
EOB_INLUM_CHR_H
Position_KN_coeff_reqVLC_ReadyVLC_valueVLI_ReadyVLI_value
EVEN_FIELD_LHUF_TBL_SEL
Recoder FSM shift_ptr
111101100000
Found VLI = “0000”,Integer = -15.
Is the coefficient position <= N?
Field Programmable Port Extender (FPX) 25
Perform Byte Stuffing
Byte Shifting Pipeline– Shift Most significant byte to
check for 0xFF’s– Stuff 0x00 if 0xFF is found that
is not a marker code
Data_out
Wr_en
Data
RecodedEntropy Data
RegA32 bits
Byte Stuffer
RegB32 bits
RegC32 bits
Shift_Cntr
Load_CntrFIFO_empty Byte Stuffer FSM
Field Programmable Port Extender (FPX) 26
Perform Byte Stuffing
Byte Shifting Pipeline– Shift Most significant byte to
check for 0xFF’s– Stuff 0x00 if 0xFF is found that
is not a marker code
Data_out
Wr_en
Data
RecodedEntropy Data
RegA32 bits
Byte Stuffer
RegB32 bits
RegC32 bits
Shift_Cntr
Load_CntrFIFO_empty Byte Stuffer FSM
Looking for 0xFF…
Field Programmable Port Extender (FPX) 27
Perform Byte Stuffing
Byte Shifting Pipeline– Shift Most significant byte to
check for 0xFF’s– Stuff 0x00 if 0xFF is found that
is not a marker code
Data_out
Wr_en
Data
RecodedEntropy Data
RegA32 bits
Byte Stuffer
RegB32 bits
RegC32 bits
Shift_Cntr
Load_CntrFIFO_empty Byte Stuffer FSM
Found 0xFF!
Do an extra shift in order to stuffwith zeros (0xFF00).
Field Programmable Port Extender (FPX) 28
Format INPUT_CELLS.DAT
Simulation Testbench
Field Programmable Port Extender (FPX) 29
Simulation Waveforms – Finding VLCs and VLIs
Matched VLC
Stored VLI
Field Programmable Port Extender (FPX) 30
Reformat SW_CELLSOUT.DAT
Field Programmable Port Extender (FPX) 31
Simulation JPEG Output – DC Values
Field Programmable Port Extender (FPX) 32
Recoded for Greater Compression
(Normal video)
17.14 KB, 0.88 bits-per-pixelup to 8 Y, 8 Cb, 8 Cr
11.78 KB, 0.61 bits-per-pixel
Field Programmable Port Extender (FPX) 33
Recoded for Greater Compression
(Normal video)
17.14 KB, 0.88 bits-per-pixel
up to 4 Y, 4 Cb, 4 Cr
9.29 KB, 0.48 bits-per-pixel
Field Programmable Port Extender (FPX) 34
Recoded for Greater Compression
(Normal video)
17.14 KB, 0.88 bits-per-pixel
up to 2 Y, 2 Cb, 2 Cr
5.60 KB, 0.289 bits-per-pixel
Field Programmable Port Extender (FPX) 35
Recoded for Greater Compression
(Normal video)
17.14 KB, 0.88 bits-per-pixel
up to 1 Y, 1 Cb, 1 Cr
4.35 KB, 0.22 bits-per-pixel
Field Programmable Port Extender (FPX) 36
Convert to “Thumbnail”
• 4 Pipeline Conversion Stages– Determine VLI size and
convert to 12 bit signedinteger
– Add to 12 bit DPCM(DC running sum)
– Denormalize (convert to 8 bitunsigned integer)
– Average Blocks Horizontally
Data_out
DataEn_out
DC_VLI_ready
VLI_data
Stage1:VLI_size
Convert to Thumbnail
Stage2:Add_DPCM
Stage3:Denormalize
Stage4:Average Luma
Lum_chr_h
Field Programmable Port Extender (FPX) 37
Convert to “Thumbnail”
• 4 Pipeline Conversion Stages– Determine VLI size and
convert to 12 bit signedinteger
– Add to 12 bit DPCM(DC running sum)
– Denormalize (convert to 8 bitunsigned integer)
– Average Blocks Horizontally
Data_out
DataEn_out
DC_VLI_ready
VLI_data
Stage1:VLI_size
Convert to Thumbnail
Stage2:Add_DPCM
Stage3:Denormalize
Stage4:Average Luma
Lum_chr_h
Field Programmable Port Extender (FPX) 38
Convert to “Thumbnail”
• 4 Pipeline Conversion Stages– Determine VLI size and
convert to 12 bit signedinteger
– Add to 12 bit DPCM(DC running sum)
– Denormalize (convert to 8 bitunsigned integer)
– Average Blocks Horizontally
Data_out
DataEn_out
DC_VLI_ready
VLI_data
Stage1:VLI_size
Convert to Thumbnail
Stage2:Add_DPCM
Stage3:Denormalize
Stage4:Average Luma
Lum_chr_h
Field Programmable Port Extender (FPX) 39
Convert to “Thumbnail”
• 4 Pipeline Conversion Stages– Determine VLI size and
convert to 12 bit signedinteger
– Add to 12 bit DPCM(DC running sum)
– Denormalize (convert to 8 bitunsigned integer)
– Average Blocks Horizontally
Data_out
DataEn_out
DC_VLI_ready
VLI_data
Stage1:VLI_size
Convert to Thumbnail
Stage2:Add_DPCM
Stage3:Denormalize
Stage4:Average Luma
Lum_chr_h
Field Programmable Port Extender (FPX) 40
Convert to “Thumbnail”
• 4 Pipeline Conversion Stages– Determine VLI size and
convert to 12 bit signedinteger
– Add to 12 bit DPCM(DC running sum)
– Denormalize (convert to 8 bitunsigned integer)
– Average Blocks Horizontally
Data_out
DataEn_out
DC_VLI_ready
VLI_data
Stage1:VLI_size
Convert to Thumbnail
Stage2:Add_DPCM
Stage3:Denormalize
Stage4:Average Luma
Lum_chr_h
Field Programmable Port Extender (FPX) 41
Sample Baseline Bitmap Output
Created by Image Editing Software(Corel PhotoPAINT)
JPEG Decoder Simulation Result(flipped and w/ header)
Field Programmable Port Extender (FPX) 42
Sample MMX Bitmap Output
JPEG Decoder Simulation Result
Field Programmable Port Extender (FPX) 43
Results
• How fast does it go?– 27.443 MHz, RAD_CLKB
• How much logic / memory does it require?– 22 logic levels– 45 % BLOCKRAMs– 12% SLICEs
Field Programmable Port Extender (FPX) 44
Motivation for JPEG Recoding
MMXMMX
NTSC
NTSC
Video
Monitor
Network
FPX
NCHARGE
Field Programmable Port Extender (FPX) 45
Video Recoder NCHARGE Module Listing
NCHARGE
Field Programmable Port Extender (FPX) 46
NCHARGE is used from a web browser to configure the module.Module ID: 60 (0x3C)Opcode: 0x04 Manually specify the number of coefficients per color component (N1xY, N2xCr, N3xCb)Opcode: 0x10 Preset to blocky color (1xY, 1xCr, 1xCb)Opcode: 0x12 Preset to blocky grayscale (1xY, 0xCr, 0xCb)
Video Recoder NCHARGE Module Listing
NCHARGE Listing File:<module>Video Recoder</module><input_opcodes>0x04,A,3,Lum,Cb,Cr,0x10,B,0,0x12,C,0,</input_opcodes><output_opcodes>0x05, A,3,Lum,Cb,Cr,0x11,B,0,0x13,C,0,</output_opcodes><fields>Lum,x,1,22,1,16,Cb,x,1,14,1,8,Cr,x,1,6,1,0</fields><help>A Manual set coefficientsB Preset blocky colorC Preset blocky grayscale</help>
Field Programmable Port Extender (FPX) 47
References
• Wallace, Gregory K. "The JPEG Still Picture Compression Standard"Reprinted from IEEE Transactions on Consumer Electronics.December 1991.
• Pennebaker and Mitchell. JPEG: Still Image Data CompressionStandard. Van Nostrand Reinhold. 1993.
• Neely and Bogale "Motion JPEG Decoder for MMX ImageProcessing Applications." Original project website 2001.http://userfs.cec.wustl.edu/~cen1/mmx_jpeg.htm
• Braun, Lockwood, and Waldvogel. "Layered Protocol Wrappers forInternet Packet Processing in Reconfigurable Hardware."Washington University in Saint Louis. July 2001.
• "Discrete Cosine Transform Tutorial." HTML page accessed July 10,2001.http://ce597n.www.ecn.purdue.edu/CE597N/1997F/students/aaron.r.bouillet.1/project/Application
Field Programmable Port Extender (FPX) 48
Field Programmable Port Extender (FPX) 49
MMX JPEG Format
• Half-size images of NTSC fields(even or odd scan lines) areencoded as individual JPEGimages (60 frames/sec)
• 0xFFxx Marker Codes identify theimages:
0xFFE0 = Start of Even Field0xFFE1 = Start of Odd Field0xFFE2 = End of Field
• Image Resolution: 640x248
Field Programmable Port Extender (FPX) 50
Monitor
Video
Monitor
JavaApplet
CS535 Project Logical Connection Diagram
ATM
FPXMMXNTSC
Field Programmable Port Extender (FPX) 51
Connections: MMX Video station to the FPX VR
Camera
Monitor
JPEG(0/101)
NCHARGE
MMXFPX
NTSC
NTSC
JPEG(0/101)
Control(0/35)
Contro
l(0
/142
) VideoRecoder
WUGS
Control
(0/1
52)
Field Programmable Port Extender (FPX) 52
CS535 “Thumbnail” Image Decoder
Dequantize& Average
Entropydecoder
TableSpecifications
CompressedImage Data
640x248pixels
VCI = 0/101
UDP OutputController
1240 Byte
UDP Packet
AAL0HeaderRAWJPEG
AAL0HeaderRAWJPEG
AAL0Header
RAWJPEG
DCValues
UDP Wrappers
TableSpecifications
AAL0HeaderRAWJPEG
AAL0HeaderRAWJPEG
ATM
OTHERATM
8-bit GrayscaleImage Data
(40x31 pixels)1240 Bytes/image
Control Cell ProcUpdatePacing
Field Programmable Port Extender (FPX) 53
The conversion from RGB to YCbCr uses the following equations:
24-bit RGB (Original)
8-bit Luminance (Y) 8-bit Chrominance Blue (Cb) 8-bit Chrominance Red (Cr)
1. Separate the Color Channels1.1. Convert the Color Channels
Y = ( LumaRed* R + LumaGreen* G + LumaBlue*B )Cb = ( B - Y ) / ( 2 - 2 * LumaBlue)Cr = ( R - Y ) / ( 2 - 2 * LumaRed)
where:LumaRed= 299/1000LumaGreen= 587/1000LumaBlue= 114/1000
Note: 64-bit arithmetic is the recommended precision for this conversion.
Since most of the perceivable informationcomes from the luminance, we can sample thechrominance half as often as we sample theluminance with only a minor change in imagequality.
Here, the sampling ratio used 4:2:2, whichmeans that there is a 2:1 ratio betweenluminance to each chrominance channel.
Field Programmable Port Extender (FPX) 54
The images is divided below into 8x8 pixel blocks beforebeing encoded in the following MCU data order.
2. Partition into Blocks1.2. Partition into 8x8 Blocks
24-bit RGB (Original)
8-bit Luminance (Y) 8-bit Chrominance Blue (Cb) 8-bit Chrominance Red (Cr)
Field Programmable Port Extender (FPX) 55
Chrominance Red (Cr)MCU0 =
…
Chrominance Blue (Cb)
= 8x8 Pixel BlockNote: For an MMX Image M = 40, N = 31
1.3. Minimum C oded U nits Data Ordering
0
1
…
Luminance (Y)0 1 … M - 1
0
1
…
N - 1
0 1 … M - 1
N - 1
0
1
…
N - 1
a b c
d
0 1 … M - 1
MCU1 =
e f g
h
1.3. Form M inimum C oded U nits
a b c d
e gf h
Field Programmable Port Extender (FPX) 56
voidforward_DCT (){
double temp[N][N];double temp1 = 0;
for (int j = 0; j < N; j++) {C[0][j] = 1.0 / sqrt(N);Ct[j][0] = C[0][j];
}for (int i = 1; i < N; i++) {
for (int j = 0; j < N; j++) {C[i][j] = sqrt( 2. 0 / N ) *
cos( ( 2 * j + 1 ) * i * pi/ ( 2.0 * N ) ) ;
Ct[j][i] = C[i][j];}
for (int i = 0; i < N; i++ ) {for (int j = 0; j < N; j++) {
temp[i][j] = 0.0;for (int k = 0; k < N; k++)
temp[i][j] += ( Pixels[i][k] - 128 ) *Ct[k][j];
}}
Matrix-MultiplyShifted Pixels by Ct
Shift Pixel (source) between(-128) and 127
}
} Prepare a Cosine matrix, Ct, that is a linearcombination of the basis functions for the
transformation
Ct:0.353 0.49 0.461 0.415 0.353 0.277 0.191 0.0970.353 0.415 0.191 -0.097 -0.353 -0.49 -0.461 -0.2770.353 0.277 -0.191 -0.49 -0.353 0.097 0.461 0.4150.353 0.097 -0.461 -0.277 0.353 0.415 -0.191 -0.490.353 -0.097 -0.461 0.277 0.353 -0.415 -0.191 0.490.353 -0.277 -0.191 0.49 -0.353 -0.097 0.461 -0.4150.353 -0.415 0.191 0.097 -0.353 0.49 -0.461 0.2770.353 -0.49 0.461 -0.415 0.353 -0.277 0.191 -0.097
2.2. DCT by Matrix Multiplication2.2. DCT by Matrix Multiplication
Field Programmable Port Extender (FPX) 57
35 - Lower Left 63 - Lower Right
0 - Upper Left 28 - Upper Right
2-D Representations of the Basis Coveragefrom the DCT Corner Values
IncreasingHorizontalFrequency
IncreasingVertical
Frequency
The position of the values in the matrixafter the DCT relates to their spatialfrequencies.
DC
2.3. DCT Result Ranked by Frequency Perception
0 1 5 6 14 15 27 28
2 4 7 13 16 26 29 42
3 8 12 17 25 30 41 43
9 11 18 24 31 40 44 53
10 19 23 32 39 45 52 54
20 22 33 38 46 51 55 60
21 34 37 47 50 56 59 61
35 36 48 49 57 58 62 63
2.3. DCT Result Ranked by Frequency Perception
Field Programmable Port Extender (FPX) 58
The human eye functions like a lowpass filter, and so some of the high frequency informationcan be removed without perceiving any loss.
IncreasingHorizontalFrequency
IncreasingVertical
Frequency
Integer rounding is used for division. Q values (8 bits) increase with spatial frequency.
3.1. Divide by Q to Filter Out High Frequencies
16 11 10 16 24 40 51 61
12 12 14 19 26 58 60 55
14 13 16 24 40 57 69 56
14 17 22 29 51 87 80 62
18 22 37 56 68 109 103 77
24 35 55 64 81 104 113 92
49 64 78 87 103 121 120 101
72 92 95 98 112 100 103 99
IncreasingHorizontalFrequency
17 18 24 47 99 99 99 99
18 21 26 66 99 99 99 99
24 26 56 99 99 99 99 99
47 66 99 99 99 99 99 99
99 99 99 99 99 99 99 99
99 99 99 99 99 99 99 99
99 99 99 99 99 99 99 99
99 99 99 99 99 99 99 99
IncreasingVertical
Frequency
Luminance Q Table Chrominance Q Table
3.1. Divide by Q to Filter Out High Frequencies
Field Programmable Port Extender (FPX) 59
FDCT Quantizer JPEG entropy encoder
Table SpecificationsTable Specifications
SourceImageData
4.0. Entropy Encoding4. Entropy Encoding
Field Programmable Port Extender (FPX) 60
This pattern begins by mapping thethe value at the lowest spatialfrequency, the DC coefficient.
The first AC coefficient is next.
Now the Zig-Zag pattern
The last values to be coded are thosethat relate to the highest spatialfrequencies.
4.1. Follow Zig-Zag Coding Sequence4.1. Follow Zig-Zag Coding Sequence
0 1 5 6 14 15 27 28
2 4 7 13 16 26 29 42
3 8 12 17 25 30 41 43
9 11 18 24 31 40 44 53
10 19 23 32 39 45 52 54
20 22 33 38 46 51 55 60
21 34 37 47 50 56 59 61
35 36 48 49 57 58 62 63
Increasing Horizontal Frequency
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Field Programmable Port Extender (FPX) 61
After the DCT followed by quantization, theresult might look like the matrix shown to theleft.
The first value to be encoded in a block is theDC coefficient. This is the most importantvalue of the block, so it can have up to 12 bitssigned precision. It is coded as the differencefrom the DC value of the previous block.
4.1. Follow Zig-Zag Coding Sequence4.2. Encoding the DC coefficient
0
23 1 0 2 0 1 0 0
-8 0 0 0 1 0 1 0
5 1 -2 0 0 0 0 0
0 -1 0 0 -1 0 0 -1
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 1 1 0 0 0 0 0
0 0 0 0 0 0 0 0
Increasing Horizontal Frequency
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Field Programmable Port Extender (FPX) 62
Huffman entropy coding is used to describe thenumber of bits used for the integer. Thiscodeword precedes the integer and is called theVLC . The Huffman codes are kept in a tablesimilar to the one shown left.
4.1. Follow Zig-Zag Coding Sequence4.2.1 Encoding the DC VLC
Run/Sz Co_len Co_wrd0/0 2 00/1 3 20/2 3 30/3 3 40/4 3 50/5 3 60/6 4 e0/7 5 1e0/8 6 3e0/9 7 7e0/A 8 fe0/B 9 1fe
Sz Co_len Co_wrd0 2 01 3 22 3 33 3 44 3 55 3 66 4 e7 5 1e8 6 3e9 7 7eA 8 feB 9 1fe
Field Programmable Port Extender (FPX) 63
The Huffman table for theVLC describes therun-length pairs: the zero-run and the numberof zeros in the integer.
4.1. Follow Zig-Zag Coding Sequence4.3.1 Encoding the AC VLC
Run/Sz Co_len Co_wrd0/0 2 00/1 3 20/2 3 30/3 3 40/4 3 50/5 3 60/6 4 e0/7 5 1e0/8 6 3e0/9 7 7e0/A 8 fe0/B 9 1fe
Run/Sz Co_len Co_wrd0/0 4 a0/1 2 00/2 2 10/3 3 4
…F/6 16 fffaF/7 16 fffbF/8 16 fffcF/9 16 fffdF/A 16 fffe
Field Programmable Port Extender (FPX) 64
TheVLIs are encoded using the same representation. However, they range only from 0-10 bits.
4.1. Follow Zig-Zag Coding Sequence4.3.2 Encoding the AC coefficients
Integer Value-1,1
-3,-2, 2, 3-7..-4, 4..7
-15..-8, 8..15-31..-16, 16..31-63..-32, 32..63
-127..-64, 64..127-255..-128, 128..255-511..-256, 256..511
-1023..-512, 512..1023
Number of bits123456789
10
VLI Representation0, 1
00, 01, 10, 11000..011, 100..111
0000..0111, 1000..111100000..01111, 10000..11111
000000..011111, 100000..1111110000000..0111111, 1000000..1111111
00000000..01111111, 10000000..11111111000000000..011111111, 100000000..111111111
0000000000..0111111111, 1000000000..1111111111
Field Programmable Port Extender (FPX) 65
23
Next, theAC coeffientsare encoded inzig-zag order.
Only thenon-zerocoeffients are encoded, sotheir position is kept track of by recording therun-length of zeros in between.
4.1. Follow Zig-Zag Coding Sequence4.3. Encoding the AC coefficients
0
0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0 0 0
Increasing Horizontal Frequency
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11
1
1 1
-1-1-1
-215
-8
21
Field Programmable Port Extender (FPX) 66
The integer value, called theVLI , is coded as shown in this table. They range from 0-11 bits.
4.1. Follow Zig-Zag Coding Sequence4.2.2 Encoding the DC VLI
Integer Value-1,1
-3,-2, 2, 3-7..-4, 4..7
-15..-8, 8..15-31..-16, 16..31-63..-32, 32..63
-127..-64, 64..127-255..-128, 128..255-511..-256, 256..511
-1023..-512, 512..1023-2047..-1024, 1024..2047
Number of bits123456789
1011
VLI Representation0, 1
00, 01, 10, 11000..011, 100..111
0000..0111, 1000..111100000..01111, 10000..11111
000000..011111, 100000..1111110000000..0111111, 1000000..1111111
00000000..01111111, 10000000..11111111000000000..011111111, 100000000..111111111
0000000000..0111111111, 1000000000..111111111100000000000..01111111111, 10000000000..11111111111
Field Programmable Port Extender (FPX) 67
4.0. Entropy Encoding
IDCTJPEG entropy decoder
Table SpecificationsTable Specifications
CompressedImageData
Dequantizer
UncompressedImageData
JPEG “Thumbnail” Decoder
“Thumbnail” Size
DCValues
Field Programmable Port Extender (FPX) 68
4.0. Entropy EncodingJPEG Decoding Example – 0xFF Marker Codes
3EC1FFE0
Entropy-coded data:
00 DC55
SOI Marker Code
4E1FF923 00FF FF
Field Programmable Port Extender (FPX) 69
4.0. Entropy EncodingJPEG Decoding Example – Serial Bit Shifts
Entropy-coded data:
0011111011000001111111110100111000011111001001
111110001111111111110111000101010
VLC
DC value (Bits = 0)
AC value (Zero Run = 1, Bits = 4)AC value (Zero Run = 6, Bits = 4)
AC value (Zero Run = 10, Bits = 4)
VLI
0-15-15
-14
AC value (Zero Run = 14, Bits = 4) -13
EOB
SOI Marker Code