john howard ehci

June 12, 2002 2

EHCI Specificationand Testing

EHCI Specificationand Testing

John S. HowardJohn S. HowardEngineering ManagerEngineering Manager

Intel CorporationIntel Corporation

June 12, 2002 3

AgendaAgenda

!! EHCI Development OverviewEHCI Development Overview!! EHCI Architecture/Key FeaturesEHCI Architecture/Key Features!! Top 10 Developer Top 10 Developer FAQsFAQs!! USB2 Host Controller Compliance ProgramUSB2 Host Controller Compliance Program!! Top Issues Identified with Compliance TestsTop Issues Identified with Compliance Tests!! SummarySummary

June 12, 2002 4

What is The EHCI Spec.?What is The EHCI Spec.?

!! Enhanced Host Controller Specification for USBEnhanced Host Controller Specification for USB Defines the architecture for a USB 2.0 capable host Defines the architecture for a USB 2.0 capable host

controller, andcontroller, and Defines register (hardware/software) interfaceDefines register (hardware/software) interface

for a highfor a high--speed capable host controller speed capable host controller !! Revision 1.0 Released March 2002Revision 1.0 Released March 2002

June 12, 2002 5

What Is ItWhat Is It

!! Intel developed specification w/contributions: Intel developed specification w/contributions: NEC, Lucent (NEC, Lucent (AgereAgere), Philips, HP, Compaq), Philips, HP, Compaq

and Microsoft and Microsoft Licensees can also suggest contributionsLicensees can also suggest contributions

to specificationto specification!! License agreement with IntelLicense agreement with Intel

Intel provides reciprocal royalty free license to useIntel provides reciprocal royalty free license to usethe specification to manufacture compliantthe specification to manufacture compliantUSB 2.0 host controllers USB 2.0 host controllers "" both discrete and integrated implementationsboth discrete and integrated implementations

ContinuedContinued

June 12, 2002 6

Goals & RequirementsGoals & Requirements

!! Evolutionary approachEvolutionary approach!! Use best features from USB 1.1 ControllersUse best features from USB 1.1 Controllers!! Mix of OHCI and UHCI Mix of OHCI and UHCI !! ReRe--use existing technology where possibleuse existing technology where possible!! Learn from USB 1.1 Controller issuesLearn from USB 1.1 Controller issues!! Maintain maximum device support and controlMaintain maximum device support and control!! Support 32 & 64Support 32 & 64--bit addressingbit addressing!! Support PCI Power ManagementSupport PCI Power Management!! Explicit Mechanism for support of PreExplicit Mechanism for support of Pre--boot SW and OS boot SW and OS

ownership handownership hand--offoff

June 12, 2002 7

AgendaAgenda


June 12, 2002 8

USB 2.0 Host Controller ArchitectureUSB 2.0 Host Controller Architecture

!! Companion Controller(s) support FS/LS devices on root portsCompanion Controller(s) support FS/LS devices on root ports!! HighHigh--speed Host Controller support HS devices on root ports speed Host Controller support HS devices on root ports

Simpler design; optimized for highSimpler design; optimized for high--speed functionalityspeed functionality!! Reuses USB 1.1 Host Controller Designs (dropReuses USB 1.1 Host Controller Designs (drop--in)in)!! USB ports USB ports workwork independent of highindependent of high--speed capable softwarespeed capable software

USB 2.0 Host Controller (HC)USB 2.0 Host Controller (HC)

Port 1Port 1

Companion USB HCs for FS/LS Companion USB HCs for FS/LS

Port 1Port 1 Port 2Port 2

Port OwnerPort OwnerControl(s)Control(s)

Port 1Port 1 PortPort 22Port Routing LogicPort Routing Logic

Port NPort N

HC Control Logic/DataHC Control Logic/DataBufferingBuffering

Enhanced HC Control LogicEnhanced HC Control LogicEnhanced Data BufferingEnhanced Data Buffering

Port 2Port 2 Port NPort N

Port NPort N

HighHigh--SpeedSpeed(Enhanced Interface) USB HC(Enhanced Interface) USB HC

June 12, 2002 9

EHCI Ext. Caps.SW Hand-Off

EHCI Ext. Caps.EHCI Ext. Caps.SW HandSW Hand--OffOff

EHCI Interface Architecture EHCI Interface Architecture

CapabilityRegisters

CapabilityCapabilityRegistersRegisters

OperationalRegisters

OperationalOperationalRegistersRegisters

Memory-BasedI/O Registers

MemoryMemory--BasedBasedI/O RegistersI/O Registers

PCI ClassCode, etc.PCI ClassPCI ClassCode, etc.Code, etc.

USB Base Address

USB Base USB Base AddressAddress

PCI PowerManagement

Interface

PCI PowerPCI PowerManagementManagement

InterfaceInterface

PCI ConfigurationRegister

PCI ConfigurationPCI ConfigurationRegisterRegister Shared Memory Work SchedulesShared Memory Work SchedulesShared Memory Work Schedules

Periodic SchedulePeriodic SchedulePeriodic Schedule

Asynchronous ScheduleAsynchronous ScheduleAsynchronous Schedule

Debug Port& BAR

Debug PortDebug Port& BAR& BAR

Debug PortRegisters

Debug PortDebug PortRegistersRegisters

June 12, 2002 10

EHCI Registers EHCI Registers

!! EHCI CapabilitiesEHCI Capabilities Optional Feature Indicators and Optional Feature Indicators and

ParametersParameters Structural ParametersStructural Parameters

!! Operational SpaceOperational Space Command/ConfigurationCommand/Configuration Host Controller StatusHost Controller Status Interrupt EnablesInterrupt Enables Schedule Base ReferencesSchedule Base References

"" Periodic Schedule Base AddressPeriodic Schedule Base Address"" Next Asynchronous Queue HeadNext Asynchronous Queue Head

USB Hub Port Status and ControlUSB Hub Port Status and Control!! Debug Port Register Set **Debug Port Register Set **

!! PCI Power ManagementPCI Power Management!! EHCI Extended Capabilities (EECP)EHCI Extended Capabilities (EECP)

OS Handoff Registers **OS Handoff Registers **

I/O SpaceI/O Space PCI PCI ConfigConfig. Space. Space

** Optional** Optional

June 12, 2002 11

EECP: BIOS/OS HandoffEECP: BIOS/OS Handoff

!! Provides simple, reliable semaphoreProvides simple, reliable semaphore--based based mechanism for exchanging EHCI ownershipmechanism for exchanging EHCI ownership Semaphores are located in PCI Configuration SpaceSemaphores are located in PCI Configuration Space

"" Located via EHCILocated via EHCI--defined EECP pointerdefined EECP pointer

!! Semaphores can be Polled or Semaphores can be Polled or !! PrePre--Boot Software can enable Boot Software can enable SMIsSMIs to be notified to be notified

on ownership semaphore modificationson ownership semaphore modifications!! See Chapter 5 for detailsSee Chapter 5 for details

June 12, 2002 12

EHCI Data StructuresEHCI Data Structures

!! Small set of data structure primitivesSmall set of data structure primitives Supports all transfer types & speedsSupports all transfer types & speeds

!! TransferTransfer--oriented ( Bulk/Control/Interrupt ) oriented ( Bulk/Control/Interrupt ) Large* buffer per data structureLarge* buffer per data structure Queue semanticsQueue semantics

!! PacketPacket--oriented ( Isochronous )oriented ( Isochronous ) Frame (millisecond) basedFrame (millisecond) based Exposes per microExposes per micro--frame programmabilityframe programmability

!! 3232--bit and 64bit and 64--bit addressing supportbit addressing support!! Simple hardware support for Scatter/GatherSimple hardware support for Scatter/Gather!! Special Frame Span Traversal Node (FSTN)Special Frame Span Traversal Node (FSTN)

June 12, 2002 13

33

3.3. When transfer complete, HC writes When transfer complete, HC writes back source back source qTD qTD with results and with results and advances state to the next advances state to the next qTD qTD in in the chainthe chain

11

1.1. HC readsHC reads qTDqTD at top ofat top ofqueue and overlays it ontoqueue and overlays it ontoqHDqHD if marked Activeif marked Active

EHCI Queue HeadsEHCI Queue Heads!! Designed to reduce Designed to reduce

avgerageavgerage memory accessesmemory accesses!! Used for all nonUsed for all non--

Isochronous data flowsIsochronous data flows!! Provides FIFO orderingProvides FIFO ordering!! Execution Steps:Execution Steps:

qTDqTD11qTDqTD00

qHDqHD

22

2.2. HC executes bus transactionsHC executes bus transactionsfrom from qHD qHD till transfer is completetill transfer is complete

June 12, 2002 14

EHCI Interface SchedulesEHCI Interface Schedules

!! A Periodic ScheduleA Periodic Schedule Isochronous & InterruptIsochronous & Interrupt

!! An Asynchronous ScheduleAn Asynchronous Schedule Bulk & ControlBulk & Control

!! Each explicitly enabled via Each explicitly enabled via System softwareSystem software!! Execution RulesExecution Rules

Repeat each microRepeat each micro--frame:frame: Periodic schedule first, thenPeriodic schedule first, then Asynchronous scheduleAsynchronous schedule

Shared Memory Work SchedulesShared Memory Work SchedulesShared Memory Work Schedules

Periodic SchedulePeriodic SchedulePeriodic Schedule

Asynchronous ScheduleAsynchronous ScheduleAsynchronous Schedule

June 12, 2002 15

Periodic Schedule OverviewPeriodic Schedule Overview!! BinaryBinary--tree structuretree structure

Traversal from leaf level to rootTraversal from leaf level to root Frame ListFrame List is the Leaf levelis the Leaf level Each level in tree is a poll rate Each level in tree is a poll rate

interval interval

!! Objects linked relative to the Objects linked relative to the Frame Frame ListList, are at correct poll rate , are at correct poll rate

!! Transfer Types SupportedTransfer Types Supported HS Isochronous (HS Isochronous (iTDiTD),), HS Interrupt (HS Interrupt (Queue HeadsQueue Heads)) FS/LS Interrupt (FS/LS Interrupt (Queue HeadsQueue Heads),), FS Isochronous (FS Isochronous (siTDsiTD))

!! Other SupportOther Support Dynamic Rebalancing of FS/LSDynamic Rebalancing of FS/LS FrameFrame--Spanning Split Transactions Spanning Split Transactions

444

Poll Rate: N Poll Rate: N 11

Periodic Frame ListPeriodic Frame List

444

444

444

222

222

111

June 12, 2002 16

Periodic Frame ListPeriodic Frame List!! Array of schedule object pointersArray of schedule object pointers!! Represents a rolling windowRepresents a rolling window

of timeof time Each location is base pointer forEach location is base pointer for

one frames worth of workone frames worth of work(8 micro(8 micro--frames) frames)

Frame work for establishingFrame work for establishingtimetime--oriented oriented reachabilityreachability

!! HC builds an offset into the HC builds an offset into the Periodic Frame list from:Periodic Frame list from: Periodic frame list base addressPeriodic frame list base address Frame Index Register [12:3]Frame Index Register [12:3]

"" Increments once each frame (1ms)Increments once each frame (1ms)

Frame List BaseFrame List Base

12123131 1313 1212 33 00

Frame IndexFrame Index

3131 1212 1111 22

Periodic Frame List Periodic Frame List

To schedule graphTo schedule graph

Accesses same offset 8 microAccesses same offset 8 micro--frames before preceding to next frames before preceding to next locationlocation

Micro-frame select

June 12, 2002 17

High Speed IsochronousHigh Speed Isochronous

!! PacketPacket--oriented Data oriented Data StructureStructure!! 8 Transaction Records 8 Transaction Records

per per iTDiTD (one per Micro(one per Micro--Frame)Frame)

Transaction Record 0Transaction Record 0



Memory Pointers, addressing, Memory Pointers, addressing, transfer state, etc.transfer state, etc.

Isochronous Isochronous Transfer Descriptor Transfer Descriptor

((iTDiTD))

1313 1212 33 00

Frame IndexFrame Index

Selects Selects Transaction Transaction

RecordRecord

Selects Frame List Selects Frame List OffsetOffset

June 12, 2002 18

Periodic Split TransactionsPeriodic Split Transactions

!! Used to service data streams through TT periodic Used to service data streams through TT periodic pipeline(s)pipeline(s)!! Requirement on Host is to:Requirement on Host is to:

Execute starts and completes when they need to occurExecute starts and completes when they need to occur"" System software must budget execution footprint (starts/completeSystem software must budget execution footprint (starts/completes)s)"" Host controller must execute and track progress of split transacHost controller must execute and track progress of split transactiontion

!! Each endpoint data structure contains:Each endpoint data structure contains: MicroMicro--frame masks which encode which microframe masks which encode which micro--frames to frames to

execute Starts & Complete splitsexecute Starts & Complete splits MicroMicro--state to track progress (to detect lost data, etc.)state to track progress (to detect lost data, etc.)

!! Projection of coreProjection of core--spec bus frame boundaries into the spec bus frame boundaries into the host schedule created many scheduling boundary host schedule created many scheduling boundary conditions, soconditions, so

June 12, 2002 19

77 00 11 22 33 44 55 66 77 00 11 22 33 44 55 66 77 00 1100

CSCSCSCS CSCS CSCSSSSSCSCSCSCS CSCS CSCS

77 00 11 22 33 44 55 66 77 00 11 22 33 44 55 66 77 00 11 22

HS BusHS BusFramesFrames

HC Periodic HC Periodic Schedule Schedule

MicroMicro -- framesframes

HS/FS/LS Bus HS/FS/LS Bus Frame BoundariesFrame Boundaries

HC Periodic Schedule HC Periodic Schedule Frame BoundariesFrame Boundaries

SSSS

BB--Frame NFrame N BB--Frame N+1Frame N+1

Interface Data Interface Data StructureStructure

HH --Frame NFrame NInterface Data Interface Data

StructureStructure

HH --Frame N+1Frame N+1

Bus Frame View Vs. Host Frame ViewBus Frame View Vs. Host Frame View

!! In order to simplify host for TT periodic pipeline support we haIn order to simplify host for TT periodic pipeline support we had to offset the d to offset the Hosts view of frame boundaries by one microHosts view of frame boundaries by one micro--frame from Buss viewframe from Buss view

Full/Low-SpeedTransaction




June 12, 2002 20

FS Isochronous INFrame-Wrap ExampleFS Isochronous INFrame-Wrap Example

StartStart--MaskMask 08h08hCompleteComplete--MaskMask C3hC3h

siTDX siTDX+1

00 11 22 33 44 55 66 77 00 11 22HH--Frame XFrame X

00 11 22 33 44 55 66 77 00 11BB--Frame YFrame Y

77

SSSS CSCS00 CSCS11 CSCS22 CSCS33

HH--Frame X+1Frame X+1

BB--Frame Y+1Frame Y+1

Back PointerBack Pointer

June 12, 2002 21

FS/LS Interrupt INFrame-wrap ExampleFS/LS Interrupt INFrame-wrap Example

StartStart--MaskMask 40h40hCompleteComplete--MaskMask 03h03h

Must be reachable from Must be reachable from consecutive Frame list locations: consecutive Frame list locations: 0,1, 8,9, 16,17 (poll period of 8)0,1, 8,9, 16,17 (poll period of 8)

Queue HeadQueue Head

000 111 222 333 444 555 666 777 000 111 222

H-FrameHH--FrameFrame

000 111 222 333 444 555 666 777 000 111B-FrameBB--FrameFrame

777

SSSSSS CS0CSCS00 CS1CSCS11

Requires use Requires use of FSTNof FSTN

June 12, 2002 22

FSTN ExampleFSTN ExampleFSTNsFSTNs are specific routing data structures to are specific routing data structures to allow system software to describe alternate allow system software to describe alternate traversal on necessary frametraversal on necessary frame--wrap wrap boundariesboundaries

8A.08A.0

8B.08B.0

8C.08C.0

8D.08D.0

8F.08F.0

8G.08G.0

8H.08H.0

8I.08I.0

4A.04A.0 4A.14A.1 4A.24A.22A.02A.0

1A.01A.0

4B.04B.0 4B.14B.1 4B.24B.2

4C.04C.0 4C.14C.1

4D.04D.0 4D.14D.12B.02B.0

44

4400

11

22

33

44

55

66

77

88

88

88

88

88

88

88

88

44

44

44

44

22

22

11

44

44

44

44

NN--ptrptrBB--ptrptr

(push) (push) FSTNFSTN

NN--ptrptrBB--ptrptr

(pop)(pop)FSTNFSTN

Push FSTN, BPush FSTN, B--ptrptr is traversed (only inis traversed (only inMicroMicro--frame 0, 1). frame 0, 1).

Pop FSTN, HC returns to Push locationPop FSTN, HC returns to Push locationand follows Nand follows N--PtrPtr

June 12, 2002 23

FS/LS InterruptRebalance LockoutFS/LS InterruptRebalance Lockout

!! When there are changes in When there are changes in active endpoints below a TTactive endpoints below a TT System software recalculatesSystem software recalculates

TT budgetTT budget Active endpoints may require Active endpoints may require

rebalancingrebalancing"" New startNew start-- and completeand complete--split split

masksmasks!! Queue Head Queue Head II--BitBit Feature makes Feature makes

rebalancing easy to managerebalancing easy to manage Software sets Software sets II--BitBit in queue headin queue head

to a one, indicating HC must to a one, indicating HC must deactivate Queue Head before deactivate Queue Head before starting another split transactionstarting another split transaction

Very easy for system software to Very easy for system software to detect when data structure is safe detect when data structure is safe to update, then reactivateto update, then reactivate

Set ActiveSet Activeto zeroto zero

Do CompleteDo CompleteLast CSLast CS

No changeNo changeto Activeto Active

Do CompleteDo CompleteNot Last CSNot Last CS

Sets ActiveSets Activeto zeroto zero

Do StartDo Start

Queue Head State & Queue Head State & Transaction ResultTransaction Result

Side Effect to Queue Side Effect to Queue Head Active bitHead Active bit

June 12, 2002 24

Async. Schedule OverviewAsync. Schedule Overview

!! HS, FS, LS Bulk & ControlHS, FS, LS Bulk & Control Split transactions for FS/LSSplit transactions for FS/LS

!! Simple, circular linked list Simple, circular linked list Yields fair service of bus Yields fair service of bus

transactions via Roundtransactions via Round--RobinRobin Nominally, one bus Nominally, one bus

transaction per list element transaction per list element per traversal **per traversal **

!! Only Queue Heads allowed Only Queue Heads allowed in schedulein schedule!! HC stops traversal when HC stops traversal when

schedule is empty **schedule is empty **I/O Register:I/O Register:Asynchronous List PointerAsynchronous List Pointer

Current Current qHead qHead PointerPointer

HHH

June 12, 2002 25

Asynch. HS Park-ModeAsynch. HS Park-Mode!! Nominally, rules are one transaction per active queue head per Nominally, rules are one transaction per active queue head per

traversal of the Asynchronous scheduletraversal of the Asynchronous schedule!! Traversing data structures is pure overheadTraversing data structures is pure overhead

Large contributor to interLarge contributor to inter--transaction times on USBtransaction times on USB Reduces actual number of busReduces actual number of bus--transactions and effective throughputtransactions and effective throughput

!! Asynchronous ParkAsynchronous Park--Mode (optional) Mode (optional) Allows HC to execute more than one consecutive bus transaction (Allows HC to execute more than one consecutive bus transaction (max 3) max 3)

from a HS Queue Head before proceeding to next Schedule elementfrom a HS Queue Head before proceeding to next Schedule element May Improve performance of highMay Improve performance of high--speed Bulk & Control Transfers (depends speed Bulk & Control Transfers (depends

on HC implementation)on HC implementation) When implemented: default ON (possibly no SW support required)When implemented: default ON (possibly no SW support required) SW may turn off or set level via the USB Command RegisterSW may turn off or set level via the USB Command Register Only available for High Speed Queue Heads in Asynchronous ScheduOnly available for High Speed Queue Heads in Asynchronous Schedulele

June 12, 2002 26

Asynch. Split TransactionsAsynch. Split Transactions

!! Same execution model as Same execution model as HS Queue Head with:HS Queue Head with: MicroMicro--machine to track split machine to track split

transaction progresstransaction progress FS/LS transfer advancement FS/LS transfer advancement

occurs when entire split occurs when entire split transaction is complete transaction is complete "" e.g. All starte.g. All start--split and split and

completecomplete--split bussplit bustransactionstransactions

!! HC uses split transaction HC uses split transaction protocol if Queue Head protocol if Queue Head marked LS or FSmarked LS or FS

HH--Frame XFrame X22

11

00

77

11

00

SSSSACKACK

CS CS NYETNYET

CS CS ACKACK

CS CS NYETNYET

Frequency of service depends on number of active Queue HeadsHeads in Async. List

June 12, 2002 27

AgendaAgenda


June 12, 2002 28

Top 5 SW Developer FAQsTop 5 SW Developer FAQs

!! How do I add How do I add qTDsqTDs to a to a qHDqHD without stopping the without stopping the qHDqHD?? See foilSee foil

!! How do I map How do I map qHDqHD state to specific error conditions? state to specific error conditions? See foilSee foil

!! Getting horrible Bulk throughput, why?Getting horrible Bulk throughput, why? Ans(1): trying to do one packet per Ans(1): trying to do one packet per qTDqTD Ans(2): many inactive Ans(2): many inactive qHDsqHDs on on AsynchAsynch Schedule. Cut the fatSchedule. Cut the fat

!! How/when do I use these SHow/when do I use these S--mask/Cmask/C--mask mask thingysthingys AnsAns: use for FS/LS Interrupt. Used to implement budgeted : use for FS/LS Interrupt. Used to implement budgeted

execution footprint See Budgeting presentationexecution footprint See Budgeting presentation!! The specified operation of the Configured Bit causes The specified operation of the Configured Bit causes

OSsOSs to impose load ordering why did you do this?to impose load ordering why did you do this? Long storyLong story

June 12, 2002 29

Adding qTDs to qTD ChainAdding qTDs to qTD Chain

!! Dummy Dummy qHDqHD Always leave inactive Always leave inactive qTDqTD on on

qTDqTD chainchain When adding new work, use the When adding new work, use the

existing dummy existing dummy qTDqTD as the first as the first qTDqTD for next bufferfor next buffer

Add additional Add additional qTDsqTDs for for remaining bufferremaining buffer

Add new dummy Add new dummy qTDqTD Activate all Activate all qTDsqTDs (except (except

dummy)dummy) Alt.Next pointers always point Alt.Next pointers always point

to the new dummy to the new dummy qTDqTD

!! Manage Manage qTDsqTDs as a preas a pre--linked linked circular listcircular list Use software head & tail pointersUse software head & tail pointers Head pointer tells software which Head pointer tells software which

qTDqTD to use nextto use next Tail pointer tells software which Tail pointer tells software which

qTDqTD is next one to reap (transfer is next one to reap (transfer results)results)

When adding new work must make When adding new work must make Alt.Next pointers reference new Alt.Next pointers reference new Head Head qTDqTD

Requirement is to add work to a queue without hitting race condiRequirement is to add work to a queue without hitting race conditionstions

June 12, 2002 30

qHD State MappingqHD State Mapping

00

>0>0

>0>0

>0>0

>0>0

>0>0

CErrCErr

11

11

11

00

00

00

HaltedHalted

11

11

00

11

00

00

XactErrXactErr

>=0>=0

>0>0

>0>0

>= 0>= 0

>0>0

00

Bytes2XferBytes2Xfer

Three consecutive bus transactions errors Three consecutive bus transactions errors (any of bad (any of bad pidpid, timeout, data , timeout, data crccrc, etc.), etc.)

STALL response (same assumption) during STALL response (same assumption) during some bus transaction during the buffer a some bus transaction during the buffer a timeout, etc. was encounteredtimeout, etc. was encountered

Assuming no other status bits are set, this Assuming no other status bits are set, this was a STALL response.was a STALL response.

((nc nc or sp) with one or more retries for or sp) with one or more retries for XactErrors XactErrors detecteddetected

Short packet (sp)Short packet (sp)

Normal (Normal (ncnc))

ExplanationExplanation

June 12, 2002 31

Top 5 HW Developer FAQsTop 5 HW Developer FAQs!! What does Caching of data structures mean?What does Caching of data structures mean?

AnsAns: the model is more of a : the model is more of a prefetchprefetch buffer, with no impliedbuffer, with no impliedcoherency mechanismscoherency mechanisms

!! Is the Is the TypTyp field in a Queue Head Horizontal Pointer used in the field in a Queue Head Horizontal Pointer used in the Asynchronous Schedule? Asynchronous Schedule? AnsAns: NO: NO

!! Where is the counter for immediate retries on splitWhere is the counter for immediate retries on splitisochronous kept?isochronous kept? AnsAns: internal to HC, no room in : internal to HC, no room in siTDsiTD

!! When does the HC set/clear the When does the HC set/clear the AsynchAsynch & Periodic & Periodic SchedSched..Status bits? Status bits? AnsAns: They are essentially a hardware : They are essentially a hardware ackack that the HC has seen the enable at that the HC has seen the enable at

a 1, or has seen the enable at a 0a 1, or has seen the enable at a 0!! Must the Debug Port work on only one port?Must the Debug Port work on only one port?

AnsAns: It may optionally work on any port, but it MUST work on the: It may optionally work on any port, but it MUST work on theport indicated port indicated

June 12, 2002 32

AgendaAgenda


June 12, 2002 33

EHCI Compliance ProgramEHCI Compliance Program

!! Goal is to ensure uniform HC Goal is to ensure uniform HC functional behavior functional behavior

!! Eliminate need for Eliminate need for ImplementationImplementation--specificspecificHC Driver Software HC Driver Software

!! Provide tools to help HC Provide tools to help HC implementers get it rightimplementers get it right

!! Not a performance testNot a performance test!! SelfSelf--Test for EHCITest for EHCI

Functional Testing Functional Testing (not 3(not 3rdrd Party Test Houses)**Party Test Houses)**

USBUSB--IF IF Host/Systems Host/Systems

TestingTesting

USBUSB--IF IF 2.0 Hub (TT) 2.0 Hub (TT)

TestingTesting

EHCI Functional EHCI Functional TestingTesting

Enhanced Host Controller InterfaceEnhanced Host Controller InterfaceComplianceCompliance

June 12, 2002 34

EHCI Compliance Prog. EHCI Compliance Prog.

!! SelfSelf--Test for EHCI Compliance Test Suite for Functional Testing is Test for EHCI Compliance Test Suite for Functional Testing is not yet released, sonot yet released, so

!! Intel Labs is providing EHCI Functional Testing, as a conveniencIntel Labs is providing EHCI Functional Testing, as a convenience e to the USB2 industry until the Selfto the USB2 industry until the Self--Test Program is in placeTest Program is in place Must be an an Adopter of the EHCI Specification (e.g. a LicenseMust be an an Adopter of the EHCI Specification (e.g. a Licensee)e) A Corporate Non Disclosure Agreement (CNDA) must be in placeA Corporate Non Disclosure Agreement (CNDA) must be in place To submit products for testing at Intel Labs, must sign an EHCI To submit products for testing at Intel Labs, must sign an EHCI Testing Testing

Services AgreementServices Agreement Prior to release, EHCI software is being made available via RestPrior to release, EHCI software is being made available via Restricted Use ricted Use

License.License. Details, contacts and forms on these requirements available on: Details, contacts and forms on these requirements available on:

http://developer.intel.com/technology/usbhttp://developer.intel.com/technology/usb

ContinuedContinued

June 12, 2002 35

EHCI Test MethodologyEHCI Test Methodology!! Test Specification derived from EHCI SpecificationTest Specification derived from EHCI Specification

Test AssertionsTest Assertions"" Short, Short, conciseconcise, unambiguous statement. Derived from specification, unambiguous statement. Derived from specification

Test DescriptionsTest Descriptions"" Outlines test, pass/fail criteria and which assertions are exercOutlines test, pass/fail criteria and which assertions are exercisedised

!! Test SoftwareTest Software!! Special purpose test peripherals for the compliance testsSpecial purpose test peripherals for the compliance tests

Test Assertions

Test Test AssertionsAssertions

Test Descriptions

Test Test DescriptionsDescriptions

EHCI Specification

EHCI EHCI SpecificationSpecification

EHCI TestSpecificationEHCI TestEHCI Test

SpecificationSpecification EHCI

Comp

lianc

e

EHCI

Comp

lianc

e

Tests

Tests

June 12, 2002 36

EHCI Compliance SoftwareEHCI Compliance Software

!! Test ExecutiveTest Executive Console App w/Popup MenusConsole App w/Popup Menus

!! Test DLLsTest DLLs 1:1 correspondence to tests 1:1 correspondence to tests

defined in EHCI Test defined in EHCI Test SpecificationSpecification

!! Testing Services DLLTesting Services DLL Simplifies details of Simplifies details of

developing/maintaining testsdeveloping/maintaining tests!! SpecialSpecial--purpose host purpose host

controller drivercontroller driver EHCI Under TestEHCI Under TestEHCI Under Test

Compliance HCDCompliance HCD

Test ServicesTest ServicesTest Services

Test ExecutiveTest Executive

EHCI TestsEHCI Tests

Results Logs

Results Results Logs Logs

June 12, 2002 37

Compliance PeripheralsCompliance Peripherals

!! Special purpose test stack requires dedicated, Special purpose test stack requires dedicated, special purpose compliance peripherals special purpose compliance peripherals !! USB2 Compliance Device SpecificationUSB2 Compliance Device Specification!! Defines the interface and operational model for Defines the interface and operational model for

special purpose peripheral used with the EHCI and special purpose peripheral used with the EHCI and USBUSB--IF TT test software.IF TT test software.!! Implementations of compliance devices for all Implementations of compliance devices for all

speeds have been provided by Cypressspeeds have been provided by Cypress LS, FS Available from USBLS, FS Available from USB--IFIF

June 12, 2002 38

Peripheral InterfacePeripheral Interface!! Device exports list of endpoint capabilities and implements a Device exports list of endpoint capabilities and implements a

simple set of commandssimple set of commands!! Host can reconfigure individual endpoint characteristics to matcHost can reconfigure individual endpoint characteristics to match h

current test requirementscurrent test requirements All transfer types (** for enumerated speed) All transfer types (** for enumerated speed) HighHigh--bandwidth (highbandwidth (high--speed only devices)speed only devices) One or more Data loop back endpointsOne or more Data loop back endpoints

"" For all transfer types supported, incl. For all transfer types supported, incl. hbwhbw (not concurrently)(not concurrently) Data streaming with no Data streaming with no NaksNaks

"" Infinite sink, source, or loop backInfinite sink, source, or loop back"" Min to Max packetMin to Max packet

Always: Always: NakNak, Stall, Timeout and/or generate CRC, Stall, Timeout and/or generate CRC!! Host can command device to Disconnect, Delay, ReconnectHost can command device to Disconnect, Delay, Reconnect!! Host can command device to issue RemoteHost can command device to issue Remote--wakeup with a specific wakeup with a specific

delay (after it observes Suspend) delay (after it observes Suspend)

June 12, 2002 39

Focused Testing AreasFocused Testing Areas

!! Register OperationRegister Operation!! Transfer Streaming TestsTransfer Streaming Tests

Debug PortDebug Port

!! Test all event masks and correct operation with Test all event masks and correct operation with PMEStatusPMEStatusPCI Power Mgt. PCI Power Mgt.

!! Short PacketShort Packet!! Error Interrupt sources (Error Interrupt sources (siTDsiTD, , iTDiTD, Queue Head), Queue Head)!! Interop Interop w/Multiple Data Streamsw/Multiple Data Streams

TransfersTransfers

!! Scatter/Gather across ALL byte boundaries (Scatter/Gather across ALL byte boundaries (siTDsiTD, , iTDiTD, Queue Head), Queue Head)!! Split transaction normal, ALL MicroSplit transaction normal, ALL Micro--Frame boundaries and HFrame boundaries and H--frame/Bframe/B--Frame Frame

boundary conditions (boundary conditions (siTDsiTD, Queue Head), Queue Head)!! Nak Nak Counter, ICounter, I--bit, Data Toggle, PID sequencingbit, Data Toggle, PID sequencing!! FSTN Traversal, Asynchronous Schedule Service Order & Park ModeFSTN Traversal, Asynchronous Schedule Service Order & Park Mode!! PING, High Bandwidth (Interrupt & Isochronous)PING, High Bandwidth (Interrupt & Isochronous)

Data StructuresData Structures

!! Enumeration (HS, FS, LS), (Interaction with Status Register)Enumeration (HS, FS, LS), (Interaction with Status Register)!! Suspend, Resume, Ownership handSuspend, Resume, Ownership hand--offoff

Port OperationsPort Operations

!! Validate Capability RegistersValidate Capability Registers!! Control/Status Registers for proper operationControl/Status Registers for proper operation!! FRINDEX (HostFRINDEX (Host--frame to Busframe to Bus--Frame)Frame)

RegistersRegisters

June 12, 2002 40

AgendaAgenda


June 12, 2002 41

Top Errors IdentifiedTop Errors Identified

!! The Asynchronous schedule bus transaction execution is not fair The Asynchronous schedule bus transaction execution is not fair (I.e. not Round(I.e. not Round--Robin)Robin) Working hard to fit transactions at end of microWorking hard to fit transactions at end of micro--frameframe

!! Setting multiple change bits in the port status and control regiSetting multiple change bits in the port status and control registerssters!! FS Isochronous (FS Isochronous (siTDsiTD))

Incorrect traversal of Incorrect traversal of siTDsiTD back pointersback pointers"" Additional overhead and/or incorrect operationAdditional overhead and/or incorrect operation

Incorrect optimizations for Incorrect optimizations for siTDsiTD.Back Pointer traversal.Back Pointer traversal"" Conflicts with dynamic reprogramming of SConflicts with dynamic reprogramming of S--/C/C--MasksMasks

!! Incorrect Incorrect NakNak Counter implementation Counter implementation !! Using Reserved bits in interface data structures for VendorUsing Reserved bits in interface data structures for Vendor--

specific intermediate Statespecific intermediate State!! HighHigh--bandwidth bandwidth multmult sequencing incorrectsequencing incorrect!! IN Data not landing in Assigned BufferIN Data not landing in Assigned Buffer

June 12, 2002 42

SummarySummary

!! EHCI Specification, Rev 1.0 released March, 2002EHCI Specification, Rev 1.0 released March, 2002 Over 30 LicenseesOver 30 Licensees

!! Compliance program up and runningCompliance program up and running More than 4 Implementations have completed More than 4 Implementations have completed

Compliance Testing Compliance Testing Finding problems in time to get them fixedFinding problems in time to get them fixed Compliance Testing available @ Intel Labs untilCompliance Testing available @ Intel Labs until

SelfSelf--test is in placetest is in place Alpha Release of SelfAlpha Release of Self--test tools available early Q3, 2002test tools available early Q3, 2002

Note: all dates provided are for planning purposes only and are Note: all dates provided are for planning purposes only and are subject to changesubject to change

June 12, 2002 43

SummarySummary

!! Contacts/URLsContacts/URLs Questions on Specification and/or Licensing:Questions on Specification and/or Licensing:

"" ehcisupportehcisupport@@intelintel.com.com Specification, Documentation, ComplianceSpecification, Documentation, Compliance

Program, etc.Program, etc."" http://developer.http://developer.intelintel.com/technology/.com/technology/usbusb

ContinuedContinued

john howard ehci

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