Jlink User Guide V1.0

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CORTEX-M/R J-LINK USER GUIDE 1. GII THIUCortex-M/R J-Link l cng c debug h tr cho vic pht trin, lp trnh firmware cho cc loi vi iu khin ARM Cortex-M/R. Adapter Cortex-M/R J-Link c thit k s dng giao tip SWD v th n gin ha giao tip gia cable v target, vi ti thiu 3 ng CLK, SWDIO v GND chng ta c th thc hin vic download firmware v debug MCU, v hon ton lm c nh cch thc ca si cable JTAG thng thng.

2. S CHN

Rev 1.0

Created 2012 @ www.arm.vn

CORTEX-M/R J-LINK USER GUIDEAdapter c 4 chn ra bao gm CLK SWD 3V3 GND tng ng cho th t chn 1 2 3 4 ca pin header (xem hnh). ng ngun 3V3 (pin3) l option, c th cp ngun cho target board vi dng in khng vt qu nh mc 500mA. Trng hp target board c ngun cung cp sn 3V3, trnh xung t, ta khng c php kt ni vi pin3. i vi STM32 hoc ARM Cortex-M/R, c th kt ni n gin theo s sau:

Cc chip STM32 th chn JTAG TMS v CLK tng ng cho 2 tn hiu SWD v CLK. trn s ta thy kt ni kh n gin, adapter lin kt vi target board ch vi 2 ng tn hiu, v 1 ng GND. Ngay c tnh hiu RST cng khng cn thit y. V th, vic giao tip theo kiu SWD gip cho chng ta gim thiu ti a s ng lin kt so vi chun JTAG thng thng.

3. CI T DRIVERV driver, cc tool IDE thng dng iu h tr cho J-LINK, v d nh Keil, ta c th d dng tm thy n trong ng dn: C:\Keil\ARM\Segger\USBDriver

Rev 1.0

Created 2012 @ www.arm.vn

CORTEX-M/R J-LINK USER GUIDELn u tin cm u USB ca adapter vo, my tnh s thc hin enumerate v a ra thng bo yu cu ng dn cha driver, chng ta c th browse ti ng dn trn c th tin hnh ci t driver cho J-LINK.

4. S DNG J-FLASHJ-FLASH l cng c lp trnh firmware (standalone programmer) c Segger cung cp min ph, chng ta c th ln trang web sau y download v: http://www.segger.com/jflash.html Cc bc setup trc khi s dng c m t nh sau: u tin ta chy chng trnh J-Flash ARM V4.46.e, chn Options Settings, hp thoi Project Settings s c hin ra. Project

Rev 1.0

Created 2012 @ www.arm.vn

CORTEX-M/R J-LINK USER GUIDE tab Target Interface ta chn kiu giao tip SWD, cc xung clock c th chn gi tr c nh hoc auto.

tab CPU, chn radio button cho Device, n nt browse n chng loi MCU m board target ang dung.

Rev 1.0

Created 2012 @ www.arm.vn

CORTEX-M/R J-LINK USER GUIDE tab Production ta c th check vo cc mc cn thit thit lp cc tc v trong qu trnh np firmware.

Rev 1.0

Created 2012 @ www.arm.vn

CORTEX-M/R J-LINK USER GUIDETab Target cho chng ta 1 s la chn ca cc thao tc lp trnh , v d nh kt ni vi chip, check blank, earase flash, program flash

lp trnh flash, chng ta c th m cc file nh (bin, hex) sau c th np Image vo flash thng qua vic thc thi mc Program (F5) tab Target nh trn.

Rev 1.0

Created 2012 @ www.arm.vn

CORTEX-M/R J-LINK USER GUIDE 5. S DNG VI KEIL IDE 5.1 Cu hnh adapterKeil IDE l mi trng pht trin tch hp cao, bao gm C/C++, ASM stype editor, trnh bin dch RealView, Simulator, cc cng c ca cc hng thirdparty v d nh Silabs UDA, ST-Link, J-Link, Stelaris ICDISau y chng ta s tm hiu v s dng Cortex-M/R J-LINK nh th no. u tin ta to project mi trn Keil theo cc hng dn ca Wizard thng thng, sau khi bin dch thnh cng source code, ta c th cu hnh (ch thc hin 1 ln) giao tip vi cng c debug tin hnh download firmware, sa li Trn thanh menu chnh, ta chn Flash Configure Flash Tools

tab Utilities check nt radio Use Target Driver for Flash Programming, phn drop box bn di, chn loi adapter Cortex-M/R J-LINK/J-Trace. Dng chut click vo nt Settings bn phi, hp thoi target driver setup c hin th ln:

Rev 1.0

Created 2012 @ www.arm.vn

CORTEX-M/R J-LINK USER GUIDE

Ta c th check vo Reset and Run nhm thng bo vi tool thc hin reset h thng sau khi vic flash firmware kt thc thnh cng.

Rev 1.0

Created 2012 @ www.arm.vn

CORTEX-M/R J-LINK USER GUIDE tab Debug, chng ta chn Port l SWD, Max Clock t 5MHz tr xung . Cui cng ta add target CPU cho ph hp kt thc vic cu hnh.

n OK kt thc

Rev 1.0

Created 2012 @ www.arm.vn

CORTEX-M/R J-LINK USER GUIDE 5.2 Dowload firmware menu Flash (trn menu chnh) bao gm 3 mc Download, Erase v Configure Flash Tools ( thc hin phn trn), n gin click chut cho 2 mc cn li thc hin download firmware hoc erase chip.

Sau y l kt qu ca s output log: Target info: -----------Device: STM32F107RC VTarget = 3.300V State of Pins: TCK: 0, TDI: 0, TDO: 1, TMS: 0, TRES: 1, TRST: 1 Hardware-Breakpoints: 6 Software-Breakpoints: 8192 Watchpoints: 4 JTAG speed: 4000 kHz Erase Done. Programming Done. Verify OK. * JLink Info: Found SWD-DP with ID 0x1BA01477 * JLink Info: TPIU fitted. * JLink Info: ETM fitted. * JLink Info: FPUnit: 6 code (BP) slots and 2 literal slots * JLink Info: Found Cortex-M3 r1p1, Little endian. Application running ...

T kt qu trn cho thy tc download c 4Mb/s mt d chng ta config max CLK = 5 MHz.

Rev 1.0

Created 2012 @ www.arm.vn

CORTEX-M/R J-LINK USER GUIDE 5.3 Debug fimware debug , trc tin ta vo mc Options For Target, tab Debug, chn nt radio theo hnh sau:

Sau khi setup xong, ta c th tin hnh debug bnh thng: Menu Start/Stop Debug Session (Ctrl+F5).

Debug

Ti liu v cc tool lin quan c th download theo link sau: http://stm32jlink.googlecode.com/svn/trunk/

Rev 1.0

Created 2012 @ www.arm.vn