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TRANSCRIPT
JK, RS, T Flip-Flop Design
Design Practice - MyCAD
JK, RS, T Flip-Flop Design Practice - MyCAD 2
• Preface• NAND2 Design
– NAND2 schematic and symbol– NAND2 simulation– NAND2 layout and results of verification
• NAND3 Design– NAND3 schematic and symbol– NAND3 simulation– NAND3 layout and results of verification
• JK Flip-Flop Design– JK Flip-Flop schematic and symbol– JK Flip-Flop simulation– JK Flip-Flop layout and results of verification
• RS Flip-Flop Design– RS Flip-Flop schematic and symbol– RS Flip-Flop simulation– RS Flip-Flop layout and results of verification
• T Flip-Flop Design– T Flip-Flop schematic and symbol– T Flip-Flop simulation– T Flip-Flop layout and results of verification
Table of Contents
JK, RS, T Flip-Flop Design Practice - MyCAD 3
Preface
• This document provides the information on how to design JK, RS, T Flip-Flop schematic and layout.
• JK, RS, T Flip-Flop is designed based on MOSIS SCMOS layout rules.
• If you want to get more information, please refer to the related documents as below.
– MyCAD Tutorial :Learn how to use schematic and layout editor.
– MySpice Tutorial : Learn about simulating a circuit.
– MyChip Pro Verification Reference Manual :Look up specific verification commands.
Copyright © 1992 – 2006, SELOCO Incorporated.
JK, RS, T Flip-Flop Design Practice - MyCAD 4
NAND2 schematic and symbol
Logic Symbol
Truth Table Schematic011
101
110
100
OUTIN1IN0
JK, RS, T Flip-Flop Design Practice - MyCAD 5
NAND2 Simulation
OUT
IN0
IN1
JK, RS, T Flip-Flop Design Practice - MyCAD 6
NAND2 layout and results of verification
Layout
DRC result
LVS result
JK, RS, T Flip-Flop Design Practice - MyCAD 7
NAND3 schematic and symbol
Logic Symbol
Truth Table Schematic
0111
1011
1101
1001
1110
1010
1100
1000
OUTCBA
OutputInput
JK, RS, T Flip-Flop Design Practice - MyCAD 8
NAND3 Simulation
IN0 IN1
OUTIN2
JK, RS, T Flip-Flop Design Practice - MyCAD 9
NAND3 layout and results of verification
Layout
DRC result
LVS result
JK, RS, T Flip-Flop Design Practice - MyCAD 10
JK FF schematic and symbol
Logic Symbol
Truth Table Schematic
반전Qn'11
세트101
리셋010
불변Qn00
동작Qn+1KJ
OutputInput
JK, RS, T Flip-Flop Design Practice - MyCAD 11
JK FF Simulation
Q
Q_bar
J
K
CLK
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JK FF layout and results of verification
Layout
DRC result
LVS result
JK, RS, T Flip-Flop Design Practice - MyCAD 13
RS FF schematic and symbol
Logic Symbol
Truth Table Schematic사용불가11
세트101
리셋010
전 상태유지00
동작QRS
OutputInput
JK, RS, T Flip-Flop Design Practice - MyCAD 14
RS FF Simulation
Q
Q_bar
S
R
CLK
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RS FF layout and results of verification
Layout
DRC result
LVS result
JK, RS, T Flip-Flop Design Practice - MyCAD 16
T FF schematic and symbol
Logic Symbol
Truth Table Schematic
Q0'1
Q00
QT
OutputInput
JK, RS, T Flip-Flop Design Practice - MyCAD 17
T FF Simulation
Q
Q_bar
T
CLK
JK, RS, T Flip-Flop Design Practice - MyCAD 18
T FF layout and results of verification
Layout
DRC result
LVS result
The End