1

jFEX

Uli Schäfer

Uli

Intro / overview / issues

Draft, will change !!!!

Some questions flagged

2

Intro: L1Calo Phase-1 System / Jets

Uli Schäfer

CPM

JEMCMX

CMX

Hub

Hub

L1Topo

ROD

ROD

JMMPPR

From Digital Processing System

CPM

JEMCMX

CMX

Hub

Hub

L1Topo

ROD

ROD

JMMPPR

jFEX

CPM

JEMCMX

CMX

Hub

eFEXHub

Opt.

Plant

L1Topo

JMM

New at Phase 1

RTM

RTM

Jets

Phase-1: jet feature extractor jFEX• Finer granularity:• Improve on jet finding

(and MET measurement)• Jet size…

3

Baseline jFEX input data• Fibre bundles via patch panel / fibre re-bundling stage• Granularity .1×.1 (η×φ)• One electromagnetic, one hadronic tower per η×φ bin• Baseline 6.4 Gb/s line rate, 8b/10b encoding,

128 bit per BC • Up to 16bit energy per tower 8 towers per fibre

• LAr data from DPS • Tile … options…

Uli Schäfer

Stick to 6.4 ?

4

Sliding Window Algorithms

Uli SchäferPhase 0 Phase 1

Baseline ?

Jet elements (towers)ROIs environment

• Increase dynamic range• Improve granularity by factor of four, to 0.1×0.1 (η×φ)• Slightly increase environment (0.9 × 0.9 baseline)• Allow for flexibility in jet definition Fat jets to be

calculated from high granularity small jets ?• Optionally increase jet environment• Assume fat tau algorithm resides in same FPGAs

5

Data replicationSliding window algorithm requiring large scale replication of data• Forward duplication only (fan-out), no re-transmission• Baseline: no replication of any source into more than two sinks• Eta-strip / phi quadrant organisation:• Fan-out in phi handled at source only (DPS)

• Transmit “core” and “environment” data• Duplication at the parallel end (on-FPGA), using additional

Multi-Gigabit Transceivers• Allowing for differently composed

streams• Minimizing latency

• Fan-out in eta handled at destination only• Baseline “far end PMA loopback” • Looking into details and alternatives

Uli Schäfer

η

ϕ?

6

Rely on that ?

Enough?

jFEX module partitioning baseline

Algorithm requiring environment of 0.9×0.9 around each tower to be processed +/- 4 neighbours in eta and phi

Processor modules• Process strips along eta• Receive fully duplicated data in phi from DPS• 8 modules covering half of eta, phi quadrant each• Most cells duplicated in a regular way at both

source and sink• “Irregular” duplication at η=0• (Current) detector cabling has lower latency around

η=0 due to cable path• Benefit from this latency reserve

and use for additional optical fan-out(re-transmission)

Uli Schäfer

η

ϕ

η=0

7

jFEX baseline partitioning

Processor modules• Half eta × phi quadrant per module• Total of ~32 × 16 bins × 2 × 2 (upstream duplication, e/h)• ~256 incoming fibres @ 6.4Gb/s baseline• 22 × 12-way opto modules “MicroPOD” high density

receivers• Four 72-way fibre connectors (“MPO/MTP”)• Note: further connectivity required for duplication at η=0:

either front (re-transmission) or back (separate active optical fanout station)

Processor FPGAs• Core of up to 1.2×0.8 (η×ϕ), plus environment 0.8×0.8 • 20 × 16 bins 80 high speed links• 6 large FPGAs per module

Uli Schäfer

288 fibres enough ?

8

Baseline and options Phi quadrant baseline driven by need for a rock solid design:• Line rate limited to 6.4 Gb/s only• Avoid extremely dense module• Sufficient η ×ϕ coverage at module level to allow for increase

of environment » baseline of 0.9 × 0.9• Orientation along eta might better match Tilecal in phase 2

Backup• In case of problems with η=0 - duplication go for full eta,

phi octant scheme

Options• Continue work on higher link speed• Continue work on duplication schemes• Consider slightly larger/more FPGAs Increase environment beyond 0.9 × 0.9

Uli Schäfer

9

How to fit on a module ?• AdvancedTC A format

• 6 processors XC7VX690T

• 4 microPOD sockets each μ

• Opto connectors in Zone 3

• Fibre bundles from rear F

• fan-out via “far end PMA loopback” P

• Output to front panel

• Readout via backplane

• Maximise module payload: small-footprint ATCA power brick, tiny IPMC mini-DIMM

Uli Schäfer

rearfrontP in

out

μ

7V

F

Z3

ATC250 enough ?

10

jFEX system (baseline)• Need to handle both fine granularity and

large jet environment (minimum 0.9×0.9)• Require high density / high bandwidth to

keep input replication factor at acceptable level (~3/4 of all FPGA inputs are duplicates)

• Fit in 8 modules• Single ATCA shelf• Sharing infrastructure with eFEX

• Handling / splitting of fibre bundles• Some communalities in ROD design• Hub design• RTM

Uli Schäfer

η

ϕ

Hub

Hub

L1Topo

ROD

ROD

Optical inputs

Hub

Hub

L1Topo

ROD

ROD

jFEXHub

eFEXHub

Opt.

Plant

L1Topo

ROD

RODRTM

RTM

11

Some remarks on baseline • FPGA density reduced wrt previously presented phi ring scheme• Still very dense design, high power dissipation• FPGA count might grow again for larger jet option• Real-time circuitry has absolute precedence over non-real-time

components• Happy to see RODs move off module • Any TTC solution must be minimum footprint• Power and ATCA control minimized in floor-plan shown

• Baseline design would probably allow for low-latency direct output into L1Topo (48 fibres total)

• Output consolidation possible at some latency penalty• jFEX relies on “MicroPOD” high-density optical devices

• Aim at higher line rates (currently FPGAs support 13 Gb/s, MicroPOD 14 Gb/s)

• Allow for even finer granularity / larger jets / smaller FPGA devices

Uli Schäfer

12

• Questions and issues are dealt with in following slides. Since I am late, please have a look at them in unformatted shape in the .txt file. They will be added below asap…

Uli Schäfer

13

Issues / questions• Many issues that came up recently are common to both

FEXes. Concentrate on jFEX specific issues here.• The 6.4 Gb/s baseline is not quite what we want to build

• At module level there is enough environment for large jets

• With FPGAs available on the market that cannot be exploited (excessive on-board duplication)

• Is 6.4 Gb/s / 0.9 x 0.9 ok, assuming we will not actually build the baseline but rather increase input rates 2-fold ?

Uli Schäfer