jazio ™ incorporatedplatform2000 1 jazio ™ supplemental supplementalinformation
TRANSCRIPT
JAZiO™ Incorporated1
PlatformPlatform20002000
JAZiOJAZiO™™
Supplemental Supplemental InformationInformation
JAZiO™ Incorporated2
PlatformPlatform20002000
Alternating References
• Larger differential signal when signal changes
• Reduces signal slew rate to achieve the same differential swing
Instead of static VREF, JAZiO uses dynamic Voltage/Timing Reference (VTR)
VTR
DataInput
VREF
PseudoDifferential JAZiO
DataInput
JAZiO™ Incorporated3
PlatformPlatform20002000
Voltage to Time Domain Transposition
Change No Change
pp
D
D
Vref
Vol
Voh
Full Differential JAZiOPseudo Differential
JAZiO transposes the voltage domain to the time domain, since signal binary is defined in the time domain.
JAZiO binary margin is more dependent on transition time rather than voltage swing.
Change vs No Change GapPeak to Peak DifferenceAbove or Below Reference
JAZiO™ Incorporated4
PlatformPlatform20002000
Change /No Change ConceptComp A
Data In
VTR VTR
Data In Comp A
No Change
This band is based on process mismatch (device W, L, etc.), reflection or overshoot (discontinuity, termination, inductance, etc.).
3
• Case 3: Comp A remains High (weakly) while the Data Output retains the previous data
• Case 1: Comp A amplifies the change and the data passes through the Steering Logic
Change
1
Change
• The time gap is used by the steering logic to pass the change or block the no-change from reaching the data output
1
JAZiO™ Incorporated5
PlatformPlatform20002000
I/O Interface Power Comparison
The system can beoptimized to achieve:
Cost reduced package
and lower system cost
or
Higher integration: more pins for more performance.
0
500
1000
1500
2000
2500
3000
3500
4000
4500
5000
0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4
Giga Bytes/Second
Pow
er (
mW
)
I/O Power For 15pf & 30pf Load Cap. @ 1.8V Vtt
JAZiO-1000 JAZiO-2000
JAZiO™(x16)(x16)
Current Single Ended
Technologies
JAZiO™ Incorporated6
PlatformPlatform20002000
• Reduced noise
• Improved margins
• Improved scalability
I/O Interface Transition Time Comparison
Transition Time (nS)
Bit
s p
e r S
e con
d p
e r P
in (
b/S
)
10M
100M
1G
10G
00.20.40.81.63.26.4
EDO
SDRAMSDRAM-100
DDR
RDRAM
JAZiO™
DDR
Better
JAZiO™ Incorporated7
PlatformPlatform20002000
Noise• JAZiO works best with slow edges (use the
entire Bit Time!)• JAZiO works with small transition levels
(differential sensing)• Works with any Termination Scheme
(Series, Parallel, Single, Dual, Source and even none in some applications)
• JAZiO is entirely common-mode
JAZiO™ Incorporated8
PlatformPlatform20002000
VTTVTT
Signal
VTR
VTTVTT
Signal
VREF
1. VSSQ noise between signal and VREF2. VTT noise and/or VTT mismatch on either end3. VREF impedance to Signal impedance mismatch
Power Supply Noise Issues
JAZiO
Pseudo Differential
JAZiO™ Incorporated9
PlatformPlatform20002000
1. Slower transition generates less noise in JAZiO2. Smaller transition generates less noise in JAZiO3. VTRs are isolated by VSS to eliminate noise variations
Environmental Noise IssuesVTT
VTT
Signal
VTR
JAZiO
VTTVTT
Signal
VREF
Pseudo Differential
Board dimensions have not shrunk as rapidly as on-chip dimensions
JAZiO™ Incorporated10
PlatformPlatform20002000
OnHard
No Change (Low Victim)
0.8V
CASE 11
2JAZiO
SlowlyTurnOn
Change(High to Low Victim)
CASE 2
VREF2
1 PseudoDifferential
Noise (No Change) Noise (Change)
No Noise (Change)No Noise (No Change)
Environmental Noise Issues
Wider Band
Narrower Band
0.5V
Less Noise; More Signal
More Noise; Less Signal
JAZiO™ Incorporated11
PlatformPlatform20002000
DRAM Application ExampleJAZiO can be used between Controller and DRAM to achieve even greater than 2 GBit/pin/sec bandwidth
JAZiO’s signaling technology allows bus expansion in both depth and width. No restriction on bus protocol or definition
JAZiO is a low latency interface
JAZiO makes implementation easier and takes the burden off of meeting set-up time, hold time, and rise/fall times.
Single cycle power-up initialization allows user to fully utilize standby/sleep mode
Low power and wide operating frequency improves DRAM cost
JAZiO’s small voltage swing and slow transition time allows multiple slots with terminations at both ends. Easily adaptable for large memory systems (like servers)
Better performance and scalability
CPU
Controller
L2
DR
AM
DR
AM
JAZ
iO
JAZ
iO
JAZ
iO
JAZiO™ Incorporated12
PlatformPlatform20002000
ClockSource
UpperAddress &
Control Lines
LowerData Lines
VTR0VTR0
VTR1
VTR1
LowerAddress &
Control Lines
5 Bit Addr & Ctrl
5 Bit Addr & Ctrl
VTR0 & VTR0
Data
VTR1 & VTR1
Data
UpperData Lines
VTT
VTT
VTT
VTT
VTT VTT
VTT
C O N T R O L L E R
DRAMDRAMDRAM
Clock
JAZiO™ Incorporated13
PlatformPlatform20002000
Read Cycle 8-Bit Burst2ns 2ns 2ns 2ns 2ns 2ns 2ns 2ns 2ns 2ns 2ns 2ns 2ns 2ns 2ns 2ns 2ns
TRCD
2-Pins
2-Pins
1-Pin
1-Pin
8-Pins
18 Pins
VTR0
VTR1
CS/RAS
CAS/WE
ADR 0:7/ADR 8:15
I/O 0:17
CS
RAS
CS RAS
CAS WE
Rows0:7
Cols0:7
Cols8:15
TCAC
Rows8:15
TRCD ~20ns or 10 cyclesTCAC ~20ns or 10 cycles
CLK2-Pins
JAZiO™ Incorporated14
PlatformPlatform20002000
Write Cycle 8-Bit Burst2ns 2ns 2ns 2ns 2ns 2ns 2ns 2ns 2ns 2ns 2ns 2ns 2ns 2ns 2ns 2ns 2ns
TRCD
2-Pins
2-Pins
1-Pin
1-Pin
8-Pins
18 Pins
VTR0
VTR1
CS/RAS
CAS/WE
ADR 0:7/ADR 8:15
I/O 0:17
CS
RAS
CS RAS
CAS
WE
Rows0:7
Cols0:7
Cols8:15
Rows8:15
TRCD ~20ns or 10 cyclesTCWD ~20ns or 10 cycles
CLK
TCWD
2-Pins
JAZiO™ Incorporated15
PlatformPlatform20002000
Read, Read,Write, Read Burst
VTR0
VTR1
CS/RAS
CAS/WE
ADR 0:7/ADR 8:15
I/O 0:17
10 Cycles 10 Cycles 10 Cycles 10 Cycles
CLK
JAZiO™ Incorporated16
PlatformPlatform20002000
Data0:8
LowerAddress &
Control LinesData9:17
VTR0VTR0
ClockSource
VTT
VTT
VTR1
VTR1
VTT
VTT VTT
VTT
C O N T R O L L E R
DRAM
DRAMDRAM
VTR2
VTR2
Data
VTR2 & VTR2
Data
VTT
VTT VTT
VTT
5 Bit Addr & Ctrl
VTR0 & VTR0
Data
VTR1 & VTR1
Data
DRAMData18:26
Data27:35
VTT
5 Bit Addr & Ctrl
Clock
VTT
Clock
UpperAddress &
Control Lines
JAZiO™ Incorporated17
PlatformPlatform20002000
CPU to SRAM Application Example
JAZiO can be used between CPU and SRAM (L2) to achieve huge bandwidth and low latency
JAZiO bus can run at the same frequency as the internal CPU clockand include DDR (2 Gbit/sec per pin)
Might use no terminations due to slow transitions and short lengths
Control pin count on Back Side Bus
Easily adaptable to support multiple cache sizes
More external cache, less internal cache smaller CPU die sizes
No restriction and full differentiation on bus protocol and definition
Better performance and scalability
JAZiO
CPU
Controller
L2
DR
AM
DR
AM
JAZiO
JAZiO™ Incorporated18
PlatformPlatform20002000
Front Side Bus
JAZiO can be used in a proprietary bus between CPU and the Northbridge to achieve even greater than 16 GBytes/sec bandwidth.
JAZiO bus can essentially run at the same frequency as the internal CPU clock with DDR.
No restriction and full differentiation on bus protocol and definition.
Lower cost in packaging and heat sink requirements due to reduced pins and power.
Better performance and scalability.
JAZiO
CPU
JAZiO
Northbridge
L2
DR
AM
DR
AM
JAZiO™ Incorporated19
PlatformPlatform20002000
Front Side Bus
JAZiO can be used in a proprietary bus between CPU(s) and the Controller(s) to achieve many GBytes/sec bandwidth
No restriction and full differentiation on bus protocol and definition
MP snoopy bus or very high speed point-to-point
For point-to-point, JAZiO bus can run at the same frequency as the internal CPU clock and include DDR (2 Gbit/sec per pin)
Keep pin count growth and bus power under control
Lower cost in packaging and heat sink requirements due to reduced pins and power
Better performance and scalabilityController
DR
AM
DR
AM
CPU
L2
JAZiO
JAZiO
JAZiO™ Incorporated20
PlatformPlatform20002000
Internal Application Example (SOC, Embedded, Etc.)
JAZiO is well suited for large internal bus structures (SOC), which have greater than 2 pf/line loading. JAZiO uses ~0.3V swing with small transmitters and receivers to easily substitute traditional full swing buses. JAZiO also scales as the technology changes (process, voltage, etc.).
JAZiO makes implementation easier and takes the burden off of meeting set-up time, hold time, and rise/fall times. JAZiO requires no PLL or DLL or repeater circuitry.
JAZiO can support multiple frequencies on a given bus structure, it can be used synchronously or asynchronously, can support multiple supply voltages on the same bus, thus allowing the user flexibility in optimizing any implementation.
JAZ
iO
JAZiO
JAZiO