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JAY DESAI 965 E El Camino Real, Sunnyvale, CA 94087 | H:8582912176 | [email protected]
SUMMARY Focused, dependable and detail oriented Software Engineer offering exceptional programming skills and a talent for developing innovative solutions to unusual yet difficult problems
HIGHLIGHTS Programming Languages: Proficient in JAVA, C, C++ & MATLAB, Familiar with Objective C, Scripting Languages: Familiar with Python and Perl Web Development Languages: Familiar with JavaScript, CSS & HTML Operating Systems: Android, iOS & Linux
EDUCATION June 2015 Master of Science in Computational Science, University of California, San Diego, CA GPA 3.40/ 4.00 June 2013 Bachelor of Science in Electronics & Communication Engineering, L.D College of Engineering, Ahmedabad, India GPA 8.40/10.00
INDUSTRY EXPERIENCE Sep’ 15 Present Platform Infrastructure ASR9K Team, Cisco Systems, San Jose, CA Software Engineer II ● Working with the Core Software Group under Platform Infrastructure ASR9K Team on next generation low level device drivers for
ASICs/FPGAs and writing application layer software to handle software licensing. Working on next generation routing technology and
programming line cards with 64bit operating system alongside debugging and fixing software level bugs for various platform components. July Sept 2014 Amazon Web Services, Route53 Team, Seattle, WA Software Development Engineer Intern ● Trusted Advisor Rule : Wrote a Trusted Advisor Rule to warn customers of Problematic Configuration Resource Record sets for DNS Based
Health Checks. Wrote extensive 2K lines of Java Code to loop through millions of health checks to search for a faulty configuration taking into
consideration the performance and storage requirements. The code searches for problematic configurations such as CNAME records with either
source name or target name matching the FQDN of the health check. In addition to this, the code searches for the wildcard record sets, alias record
sets and a complex tree configuration containing weighted, latency or failover sets having health check with a different name associated with them
but same health check id as the health check under consideration. The rule warns customers about these faulty configurations along with the
details of the Problem. ● Health Check Search in Console : Used Google Web Toolkit to create a search functionality in the AWS Route53 console for the customer API
which enables customers to search for their active health checks which can be associated with a resource record set or a name server to check its
state which can be either healthy or unhealthy, and a failover set can be configured in case of an unhealthy instance. The search box takes in query
string and converts into a lower case query which successfully matches both uppercase and lowercase characters contained in the health checks
tags and returns the relevant predicted results. Aug ’12 May ’13 Indian Space Research Organization , Ahmedabad , India Receiver End Research Intern ● Microwave Hairpin Resonator: Designed a Microwave Hairpin Resonator for “Chandrayaan 2 Lander” & improved its Frequency response
substantially to gain an operating frequency of 3.972 GHz. Wrote extensive MATLAB code of 1K lines to design a 4th Order loop filter for
receiver section of Chandrayaan 2 lander. Improved noise performance of the filter considerably by 5% and designed a Digital Phase Locked
Loop using C. Worked on Ka Band Synthetic Aperture Radar (SAR) on board lander to achieve velocity Accuracy of 0.4 m/s & a height
estimation with 10 cm resolution. Digital Signal Processing Intern ● Image Filtering: Worked on Virtex 4 Field Programmable Gate Array & OBC Micro controller based On Board signal processor which was used
for storage and image processing of 1k x 1k monochromatic images in addition to 2 D filtering, 3 D DEM generation and 3 D Hazard Map
Generation. Analyzed the crater feature detection algorithm which involves processing of the initial Synthetic Aperture Radar (SAR) images of
the moon surface into an unsupervised segmentation image which is followed by a geometric check and elliptic characterization. Analyzed the
working of the hazard map algorithm which implemented the process of assigning a hazard score, which is a slope and roughness score, to each
pixel of the image which measures in both absolute and relative terms how risky it is for landing.
Feb Mar 2012 Bharat Sanchar Nigam Limited, Ahmedabad, India Telecoms Intern ● Internet Protocols and Routing Technologies: Worked on Internet Protocols such as IPV4, IPV6 & VoIP. Worked on FTP, SMTP, distributed hash
tables, cyclic redundancy, socket programming, creating web server using python & TCP congestion control. Analyzed Internet routing
technologies such as IntraAS routing: RIP, BGP & OSPF & worked on real time conversational applications such as RTP and SIP. Analyzed
working of 4G LTE Architecture, GSM, CDMA, Wi Fi & Wimax technology. ACADEMIC PROJECTS MULTIGRID IMPLEMENTATION OF 3 D POISSON’S EQUATION USING CUDA: (Parallel Computing)
● Obtained Numerical solution for 3 D Poisson’s Equation. Multigrid scheme was employed which involves solving the problem as a series of coarse
problems and accelerate the convergence of a basic iterative method like Jacobi by global correction. Interpolation between coarser and finer grids
was carried out. NAS Parallel Benchmark Code was adopted which carries out a series of cogent steps such as setting up of initial grids, residual
calculation at finest level followed by multigrid V Cycle execution which involves projecting the fine level residual to coarsest level, smoothing at
coarsest level and then for each coarser level interpolating the solution of finer level to current coarser level. Once the multigrid V cycle execution
halts, re instantiation of the grids is carried out. Finally L2 norm of residual is calculated for verification.
● Three Fundamental Memory accesses were optimized for GPUs designed by NVIDIA, such as Register Memory, Shared Memory and Global
Memory. In order to achieve good overall performance on the GPUs and to avoid high latency of memory accesses, hardware and the
multiprocessor were kept busy by exposing them to enough amount of parallelism. The parallelism was achieved by employing 2 techniques
which includes Increasing/Decreasing the number of concurrent threads on a multiprocessor OR the number of independent operations issued per
thread. For employing these techniques most accurate processor geometry was chosen.
IMPLEMENTING HIGH PERFORMANCE MATRIX MULTIPLICATION ON A GPU : (Parallel Computing)
● Block Matrix Algorithm was used which allowed multi threaded execution of smaller blocks(chunks) of large matrices in order to improve locality.
Utilized shared memory for communication between the various execution units (threads) to facilitate reuse. Performing coalesced memory
accesses to avoid bank conflicts between different threads. Shared Memory Technique removed global memory bandwidth as the major limiting
factor for matrix multiplication.
HARDWARE PREFETCHER: (Computer Architecture)
● Implemented a Prefetcher in which the system controller provided information about all load and store that were issued by the CPU. The provided
information included the effective memory address, Program counter of the memory instruction & whether the instruction was a load or a store.
During all cycles when the CPU is not issuing a request to the L2 cache, the system controller queries the pre fetcher for any memory requests that
it has. Prefetcher processes the requests that are queued internally, while the system services a maximum of 1 request per cycle. After the
prefetching request has been satisfied either from the L2 cache or main memory, the request is placed in the data cache. The memory hierarchy
was simulated using trace files generated by the Pin Binary Instrumentation tool.
TEACHING EXPERIENCE Oct Dec 2013 University of California, San Diego, CA Teaching Assistant Linear Algebra: Taught Linear Algebra and Matlab programming to 200 undergraduate students. Course included Matrix Algebra, Gaussian
elimination, Determinants, Linear and Affine Subspaces, Computing symbolic and graphical solutions using Matlab.
Jan Mar 2014 University of California, San Diego, CA Teaching Assistant Vector Calculus : Taught vector calculus to more than 150 undergraduate students. Course included Change of variable in multiple integrals,
Jacobian, Green’s theorem, Taylor series in Several Variables, Surface integrals, Stokes theorem, Gauss’ theorem and Conservative fields.
AWARDS ● Ranked in top 0.5% among 90,000 students in HSC board exams.
● Won Best Student award for two consecutive academic terms.
● School representative for the Science Quiz at Physical Research Laboratory
● IEEE certification for completing Image processing and Linux workshops.