january 9, 2013 ieee eds dl@vit, vellore, india · 2013-04-17 · dubai, uae (year 2010) 828 m...
TRANSCRIPT
Future of nano CMOS Technology
January 9, 2013
Hiroshi Iwai, Tokyo Institute of Technology
1
IEEE EDS DL@VIT, Vellore, India
1900 “Electronics” started.
Device: Vacuum tubeDevice feature size: 10 cm
1970 “Micro-Electronics” started.
Device: Si MOS integrated circuitsDevice feature size: 10 µm
Major Appl.: Amplifier (Radio, TV, Wireless etc.)
Major Appl.: Digital (Computer, PC, etc.)
Technology Revolution
Technology Revolution
2000 “Nano-Electronics” started.
Device: Still, Si CMOS integrated circuitsDevice feature size: 100 nmMajor Appi.: Digital (µ-processor, cell phone, etc.)
Technology Revolution??
Maybe, just evolution or innovation!
Now, 2012 “Nano-Electronics” continued.
Device: Still, Si CMOS integrated circuitsDevice feature size: 10 nmMajor Appl.: Digital (µ-processor, cell phone, etc.)
Future, “Nano-Electronics” still continued?
Device: Still, Si CMOS integrated circuits?Device feature size: ? nm, what is the limit?
Application: New application?
Technology Revolution?
Future, “Nano-Electronics” still continued?
Device: Still, Si CMOS integrated circuits?Device feature size: ? nm, what is the limit?
Application: New application?
Technology Revolution?
What is special or new for Nano-Electronics?
In 1990’s, people expected completely new mechanism or operational principle due the nano size, like quantum mechanical effects.
However, no fancy new operational principle was found.
At least for logic application, there is no success story for “Beyond CMOS devices” to replace Si-CMOS.
λ>>LDiffusive transport
λ<LBallistic transport
λ~LQuasi-Ballistic transport
Lλ :Mean free pathsource drain
RM
Back scatteringfrom drain
Ballistic transport will neverHappen for MOSFET because of back scattering
With decreasing channel length,Drain current increase continue.
Also, 1D quantum conduction, or ballistic conduction will not happen.
Ballistic conduction will not happeneven decreasing channel lengh.
(1D quantum conduction: 77.8µS regardless of the length and material).
First Computer Eniac: made of huge number of vacuum tubes 1946Big size, huge power, short life time filament
Today's pocket PCmade of semiconductor has much higher performance with extremely low power consumption
dreamed of replacing vacuum tube with solid‐state device
8
1960: First MOSFET by D. Kahng and M. Atalla
Top View
Al Gate
Source
Drain
Si
Si
Al
SiO2
Si
Si/SiO2 Interface is extraordinarily good
9
1970,71: 1st generation of LSIs
DRAM Intel 1103 MPU Intel 4004
10
Most Recent SD Card
128GB (Bite) = 128G X 8bit= 1T(Tera)bit
1T = 1012 = 1Trillion
Brain Cell:10~100 BillionWorld Population:7 Billion
Stars in Galaxy:100 Billion
In 2012
2.4cm X 3.2cm X 0.21cm
Volume:1. 6cm³ Weight:2g
Voltage:2.7 - 3.6V
Old Vacuum Tube:5cm X 5cm X 10cm, 100g, 50W
128 GB = 1Tbit
What are volume, weight, power consumption for 1Tbit
Old Vacuum Tube:5cm X 5cm X 10cm
1Tbit = 10,000 X 10,000 X 10,000 bitVolume = (5cm X 10,000) X (5cm X 10,000)
X (10cm X 10,000)= 0.5km X 0.5km X 1km
500 m
1,000 m
1Tbit
Burji KhalifaDubai, UAE(Year 2010)
828 m
Indian TowerMumbai, India(Year 2016)
700 m
700 m
Pingan IntenationalFinance CenterShanghai, China(Year 2016)
Old Vacuum Tube:100W
1Tbit = 1012bitPower = 0.05kWX1012=50 TW
Nuclear Power Generator1MkW=1BW We need 50,000 Nuclear Power Plant for
just one 128 GB memory
In Japan we have only 54 Nuclear Power Generator
Last summer Tokyo Electric Power Company (TEPCO) can supply only 55BW.
We need 1000 TEPCO just one 128 GB memory
Imagine how many memories are used in the world!
So progress of integrated circuits is extremely important for power saving.
Brain: Integrated Circuits
Hands, Legs:Power device
Stomach:PV device
Ear, Eye:Sensor
Mouth:RF/Opto device
16
17
Near future smart-society has to treat huge data.
Demand to high-performance and low power CMOS become much more stronger.
18
MemoryMemory[19%][19%]
MicrocompMicrocomp..[21%][21%]
Logic ICLogic IC[27%][27%]
Analog ICAnalog IC[15%][15%]
OthersOthers[18%][18%]
MemoryMemory[13%][13%]
MicrocompMicrocomp..[14%][14%]
Logic ICLogic IC[30%][30%]
Analog ICAnalog IC[10%][10%]
Emerging areasEmerging areas[33%][33%]
313 billion dollar (US) in 2011
1,528 billion dollar (US) in 2025
(Gartnerの市場予測)
Semiconductor Device Market will grow 5 times in 12 years, even though, it is very matured market!!
Gartner: By K. Kim, CSTIC 2012
Downsizing1. Reduce Capacitance
Reduce switching time of MOSFETsIncrease clock frequency
Increase circuit operation speed2. Increase number of Transistors
Parallel processingIncrease circuit operation speed
Thus, downsizing of Si devices is the most important and critical issue.19
Downsizing contribute to the performance increase in double ways
20
(1970) 10 µm 8 µm 6 µm 4 µm 3 µm 2µm 1.2 µm
0.8 µm 0.5 µm 0.35 µm 0.25 µm 180 nm 130 nm 90 nm
Averaged downsizing rate (in the past 42 years): ~ 0.7X every 3 years
Total reduction in 19 generations: Gate Length ~ 1/500, Area ~ 1/250,000
65 nm 45 nm 32 nm 22 nm (2012)
Feature Size/Technology Node
Gate oxide
Gate metal
Source Drain
1V 0V0V
Substrate 0V DepletionRegion (DL)
1V
0V 0V
tox and Vdd have to be decreased for betterchannel potential control IOFF Suppression
0V < Vdep<1V
0V
0V < Vdep<1VChannel
0V
0V
0V0V
0.5V
Large IOFF
Region governed By drain bias
Region governed by gate bias
tOX thinning
DL touch with SRegion (DL)
Large IOFF
No toxthinning
Vdd
Vdd
21
Problem for downsizing
LLgate gate and tand toxox(EOT) scaling trend(EOT) scaling trendA. Toriumi (Tokyo Univ), IEDM 2006, Short Course
t ox(
(
22
Gate oxideGate oxide
Small Cox Low inversion electron densitySmall ION
Large Cox High inversion electron densityLarge ION
Inversion layer Inversion layer
ttoxox thinningthinning
1V
1V
tOX thinning
23
Tunnelingdistance
3 nm
What would be the limit of downsizing!
Source DrainChannel
25
Vg
Id
Vth (Threshold Voltage)
Vg=0V
SubthreshouldLeakage Current
Subtheshold leakage current of MOSFET
Subthreshold CurrentIs OK at Single Tr. level
But not OKFor Billions of Trs.
ONOFF
Ion
Ioff
Subthresholdregion
26
Vg (V)1
0.3 V
0.5 V 1.0 V
Ion
Ioff
Id (A/µm)
10-7
10-5
10-11
10-9
Vd
Vth
0.15 V
0 0.5
Subthreshold leakage current will limit the downsizing
Electron EnergyBoltzmann statics
Exp (-qV/kT)
27
Subthreshold Leakage (A/µm)
Ope
ratio
n Fr
eque
ncy
(a.u
.)
e)
100
10
1
Source: 2007 ITRS Winter Public Conf.
The limit is deferent depending on application
How far can we go for production?
10µm 8µm 6µm 4µm 3µm 2µm 1.2µm 0.8µm 0.5µm
0.35µm 0.25µm 180nm 130nm 90nm 65nm 45nm 32nm
1970年
22nm 16nm 11.5 nm 8nm 5.5nm? 4nm? 2.9 nm?
Past 0.7 times per 3 years
Now
In 40 years: 18 generations,Size 1/500, Area 1/250,000
Future
・At least 4,5 generations to 8 ~ 5 nm
29
1V0V
0V
S
0V
0V <V<1V
1V0V
0V
0V
0VS D
G
G
G
Suppression of subthreshold leakage by surrounding gate structure
Planar Surrounding gate
Planar Fin Nanowire
Source DrainGate
Wdep
1
Leakage current
S D
Planar FETFin FET Nanowire FET
Because of off-leakage control,1V
0V
0V0V
0VS
D
GG
31
Fin Tri-gate Ω-gate All-around
G G G
G
GNanowire structures in a wide meaning
More Moore to More More MooreMore Moore to More More Moore
65nm 45nm 32nm
Technology node
M. Bohr, pp.1, IEDM2011 (Intel)P. Packan, pp.659, IEDM2009 (Intel)C. Auth et al., pp.131, VLSI2012 (Intel)T. B. Hook, pp.115, IEDM2011 (IBM)S. Bangsaruntip et al., pp.297, IEDM2009 (IBM)
Lg 35nm Lg 30nm
Main stream(Fin,Tri, Nanowire)
22nm 15nm, 11nm, 8nm, 5nm, 3nm
Alternative
Alternative (III-V/Ge) Channel FinFET
Emerging Devices 32
Tri-Gate
Now Future
Si channelSi
Others
(ETSOI)
Planar
Si is still main stream for future !! ET: Extremely Thin
HighHigh--k gate dielectricsk gate dielectrics
Continued research and development
SiO2 IL (Interfacial Layer) is used at Si interface to realize good mobility
Technology for direct contact of high-k and Si is necessary
Remote SiO2-IL scavengingHfO2 (IBM)
EOT=0.52 nm
Si
La-silicate
MG
Direct contact with La-silicate (Tokyo.Tech)
T. Ando, et al., p.423, IEDM2009, (IBM) T. Kawanago, et al., T-ED, vol. 59, no. 2, p. 269, 2012 (Tokyo Tech.)
K. Mistry, et al., p.247, IEDM 2007, (Intel)
TiN
HfO2
Si
SiO2
EOT=0.9nmHfO2/SiO2(IBM)
T.C. Chen, et al., p.8, VLSI 2009, (IBM)
Hf-based oxides
45nmEOT:1nm
32nmEOT:0.95nm
22nmEOT:0.9nm
15nm, 11nm, 8nm, 5nm, 3nm,
K. Kakushima, et al., p.8, IWDTF 2008, (Tokyo Tech.)
EOT=0.37nm EOT=0.40nm EOT=0.48nm
0.48 → 0.37nm Increase of Id at 30%
[1] C. Auth et al., pp.131, VLSI2012 (Intel).[2] K. Mistry et al., pp.247, IEDM2007 (Intel).[3] H.-J. Cho et al., pp.350, IEDM2011 (Samsung).[4] S. Saitoh et al., pp.11, VLSI2012 (Toshiba).[5] S. Bangsaruntip et al., pp.297, IEDM2009 (IBM).
[6] T. Yamashita et al., pp.14, VLSI2011 (IBM).[7] A. Khakifirooz et al., pp.117, VLSI2012 (IBM).
IIONON and Iand IOFFOFF benchmarkbenchmark
[8] G. Bidal et al., pp.240, VLSI2009 (STMicroelectronics).[9] S. Sato et al., pp.361, ESSDERC2010 (Tokyo Tech.)[10] K. Cheng et al., pp.419, IEDM2012 (IBM)
1
10
100
1000
10000
0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2ION [mA/µm]
I OFF
[nA
/µm
]NMOS
Intel [1]Bulk 32nmVDD=0.8V
Intel [1]Tri-Gate 22nmVDD=0.8V
Intel [2]Bulk 45nmVDD=1V
Toshiba [4]Tri-Gate NWVDD=1V
Samsung [3]Bulk 20nmVDD=0.9V
IBM [5]GAA NWVDD=1V
IBM [6]FinFET 25nmVDD=1V
IBM [7]ETSOIVDD=0.9V
IBM [7]ETSOIVDD=1V
STMicro. [8]GAA NWVDD=0.9V
STMicro. [8]GAA NWVDD=1.1V
Tokyo Tech. [9]Ω-gate NWVDD=1V
IBM [10]ETSOIVDD=0.9VIeff
1
10
100
1000
10000
0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6ION [mA/µm]
I OFF
[nA
/µm
]
PMOSIntel [1]Bulk 32nmVDD=0.8V
Intel [1]Tri-Gate 22nmVDD=0.8V
Intel [2]Bulk 45nmVDD=1V
IBM [7]ETSOIVDD=1VSamsung [3]
Bulk 20nmVDD=0.9V
IBM [5]GAA NWVDD=1V
IBM [6]FinFET 25nmVDD=1V
IBM [7]ETSOIVDD=0.9V
STMicro. [8]GAA NWVDD=1.1V
IBM [10]ETSOIVDD=0.9VIeff
・Lg and EOT are larger than ITRS requirements
・Implementation of Tri-gate and lower Vth/Vdd since 22nm
C. Auth et al., pp.131, VLSI2012 (Intel).
K. Mistry et al., pp.247, IEDM2007 (Intel).P. Packan et al., pp.659, IEDM2009 (Intel).
Comparison with ITRSComparison with ITRS
0
0.2
0.4
0.6
0.8
1
1.2
1.4
2006 2008 2010 2012 2014 2016 2018 20200
0.2
0.4
0.6
0.8
1
1.2
1.4
Year
VD
D(V
)
VDD
Vth
ITRS2007~2011
Intel
45nm 32nm
22nm
Intel45nm32nm
22nm
Multi-GateBulk Planar
Vth (V
)
0
5
10
15
20
25
30
35
40
2006 2008 2010 2012 2014 2016 2018 20200.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
Year
L g(n
m)
EO
T (nm)
Intel45nm32nm 22nm
ITRS2007~2011
Intel
45nm 32nm
22nmMulti-Gate
Bulk PlanarITRS2007
EOT
LgITRS2009~2011
<80
56/9
2.05/1.5
1.1
~0.5
-
HfZrO2
22/30 (nFET/pFET)
GAA NW
STMicro. (VLSI2008)
85
65/105
0.83/0.95
1
0.3~0.4
1.5
Hf-based
35/25 (nFET/pFET)
GAA NW
IBM (IEDM2009)
Intel(IEDM2007, 2009)
Intel (VLSI2012)
Toshiba (VLSI2012)
IBM (IEDM2012)
Samsung (IEDM2012)
Tokyo Tech (ESSDERC2010)
StructureBulk Planar Tri-Gate
22nm Tri-Gate NW ETSOI Bulk Planar Ω-gate NW45nm 32nm
Lg (nm) 35 30 30 14 22 20 65
Gate Dielectrics Hf-based Hf-based SiO2 HfO2 HfO2 ? SiO2
EOT (nm) 1 0.95 0.9 3 ~1 - 3
Vth (V) ~0.4 ~0.3 ~0.2 -0.15 (nFET) 0.3~0.4 ~0.3 -0.2 (nFET)
VDD (V) 1 1 0.8 1 0.9 0.9 1
ION (mA/um) nFET/pFET 1.36/1.07 1.53/1.23 1.26/1.1 0.83 (nFET) 0.59/0.62 (Ieff) 1.2/1.05 1.32 (nFET)
DIBL (mV/V)
nFET/pFET~150 ~200 46/50 <50 - 104/115 62
SS (mV/dec) - ~100 ~70 <80 - 87 70<80
56/9
2.05/1.5
1.1
~0.5
-
HfZrO2
22/30 (nFET/pFET)
GAA NW
STMicro. (VLSI2008)
85
65/105
0.83/0.95
1
0.3~0.4
1.5
Hf-based
35/25 (nFET/pFET)
GAA NW
IBM (IEDM2009)
Intel(IEDM2007, 2009)
Intel (VLSI2012)
Toshiba (VLSI2012)
IBM (IEDM2012)
Samsung (IEDM2012)
Tokyo Tech (ESSDERC2010)
StructureBulk Planar Tri-Gate
22nm Tri-Gate NW ETSOI Bulk Planar Ω-gate NW45nm 32nm
Lg (nm) 35 30 30 14 22 20 65
Gate Dielectrics Hf-based Hf-based SiO2 HfO2 HfO2 ? SiO2
EOT (nm) 1 0.95 0.9 3 ~1 - 3
Vth (V) ~0.4 ~0.3 ~0.2 -0.15 (nFET) 0.3~0.4 ~0.3 -0.2 (nFET)
VDD (V) 1 1 0.8 1 0.9 0.9 1
ION (mA/um) nFET/pFET 1.36/1.07 1.53/1.23 1.26/1.1 0.83 (nFET) 0.59/0.62 (Ieff) 1.2/1.05 1.32 (nFET)
DIBL (mV/V)
nFET/pFET~150 ~200 46/50 <50 - 104/115 62
SS (mV/dec) - ~100 ~70 <80 - 87 70
Benchmark of device characteristicsBenchmark of device characteristics
The down scaling of MOSFETs is still possible for at least another 10 years!
2. Thinning of high-k gate oxide thicknessbeyond 0.5 nm
3. Metal(Silicide) S/D
1. Wire channel
4 important technological items for down scaling.New structures
New materials
4. III-V/Ge channel, for the moment, however, very difficult to replace Si
These technologies are very difficult and not every company can success in the development timely.
In the past, technology comes with the purchase of equipment, but any more.
Thus, some of the companies are in the threat of dropping off.
There are so many rooms for the universities to contribute to the development of Si world.
Wire channel
40
Si nanowire FET as a strong candidate
1. Compatibility with current CMOS process
2. Good controllability of IOFF
3. High drive current
1D ballisticconduction
Multi quantumChannel High integration
of wires
k
E
量子チャネル
量子チャネル量子チャネル量子チャネル
バンド図
Quantum channelQuantum channel
Quantum channelQuantum channel
k
E
量子チャネル
量子チャネル量子チャネル量子チャネル
バンド図
Quantum channelQuantum channel
Quantum channelQuantum channel
Off電流のカットオフ
Gate:OFFDrain Source
cut-off
Gate: OFFdrainsource
Off電流のカットオフ
Gate:OFFDrain Source
cut-off
Gate: OFFdrainsource
Wdep
1
Leakage current
S D
Increase the Number of quantum channels
Energy band of Bulk Si
Eg
By Prof. Shiraishi of Tsukuba univ.
Energy band of 3 x 3 Si wire
4 channels can be used
Eg
41
Compact modeling of nanowire MOSFETs is very difficult
43By Profs. Oshiyama and Iwata, U. of Tokyo
Diameter dependence
By Profs. Oshiyama and Iwata, U. of Tokyo
Wire cross section dependence.
What cross section gives best solution forSCE suppression and drive current?.
45
λ>>LDiffusive transport
λ<LBallistic transport
λ~LQuasi-Ballistic transport
Lλ :Mean free pathsource drain
Mobility Theory
Real nanoscaleMOSFETs
Compact model for circuit designer is very important
Prof. K. Natori of TIT
46
0
10
20
30
40
50
0 0.1 0.2 0.3 0.4 0.5 0.6
300K VG-Vt=0.1V
300K VG-Vt=0.4V
300K VG-Vt=0.7V
300K VG-Vt=1.0V
4K VG-Vt=0.1V
4K VG-Vt=0.4V
4K VG-Vt=0.7V
4K VG-Vt=1.0V
Current (
µA)
Drain Bias (V)
Prof. K. Natori of TIT
47
F(x)/h は、正速度フラックス
G(x)/h は、負速度フラックス( )
( )
0
0
2 ( ) ( ) ( ) 0
2 ( ) ( ) ( ) 0
BdF xqEx F x G xm dx qEx
BdG xqEx G x F xm dx qEx
εε
εε
+ + − =+
− + + − =+
( )
( )
0 0
0 0
22 ( ) ( ) ( ) ( ) 0
22 ( ) ( ) ( ) ( ) 0
B DdF xqEx F x G x F xm dx qEx qEx
B DdG xqEx G x F x G xm dx qEx qEx
εε ε ε
εε ε ε
∗
∗
+ + − + =+ + −
− + + − + =+ + −
( )0
00 0 0 0 0
2( )
2 ln
D qET
qExB D D qE mD Bε
εε
=+⎛ ⎞+ + + ⎜ ⎟
⎝ ⎠
弾性散乱域
光学フォノン放出域
ソースからドレインへの透過確率(エネルギー εに対して)
散乱の導入に係る計算式散乱の導入に係る計算式
物理パラメータB0の値は移動度対応した値
物理パラメータD0の光学フォノンエネルギー緩和時間に対応した値
Prof. K. Natori of TIT
48
0
5
10
15
20
25
30
35
40
0 0.1 0.2 0.3 0.4 0.5
VG-Vt=0.1V, Bal.
VG-Vt=0.1V, Q-Bal.
VG-Vt=0.4V, Bal.
VG-Vt=0.4V, Q-Bal.
VG-Vt=0.7V, Bal.
VG-Vt=0.7V, Q-Bal.
VG-Vt=1.0V, Bal.
VG-Vt=1.0V, Q-Bal.
Current [µA]
Drain Bias [V]
Prof. K. Natori of TIT
49
0.E+00
2.E-05
4.E-05
6.E-05
8.E-05
0.0 0.5 1.0Vd (V)
Id (A
)
Vg – Vth = 1V
0.8V
0.6V
0.4V
0.2V
ExperimentQuasi ballistic
Lg=65nm, Tox=3nm
1.E-12
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
-1.5 -1.0 -0.5 0.0 0.5 1.0
0.E+00
1.E-05
2.E-05
3.E-05
4.E-05
5.E-05
6.E-05
7.E-05
-1.0 -0.5 0.0 0.5 1.00
10 20 30 40 50 60 70
Dra
in C
urre
nt (µ
A)
Drain Voltage (V)
Vg-Vth=1.0 V
Vg-Vth= -1.0 V
0.8 V
0.6 V
0.4 V
0.2 V
(a)
10-12
Gate Voltage (V)
pFET nFET
(b)
10-11
10-10
10-9
10-8
10-7
10-6
10-5
10-4
10-3
Dra
in C
urre
nt (A
)
Vd=-50mV
Vd=-1V
Vd=50mV
Vd=1V
1.E-12
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
-1.5 -1.0 -0.5 0.0 0.5 1.0
0.E+00
1.E-05
2.E-05
3.E-05
4.E-05
5.E-05
6.E-05
7.E-05
-1.0 -0.5 0.0 0.5 1.00
10 20 30 40 50 60 70
Dra
in C
urre
nt (µ
A)
Drain Voltage (V)
Vg-Vth=1.0 V
Vg-Vth= -1.0 V
0.8 V
0.6 V
0.4 V
0.2 V
(a)
10-12
Gate Voltage (V)
pFET nFET
(b)
10-11
10-10
10-9
10-8
10-7
10-6
10-5
10-4
10-3
Dra
in C
urre
nt (A
)
Vd=-50mV
Vd=-1V
Vd=50mV
Vd=1V
On/Off>106、60uA/wire
Recent results to be presented by ESSDERC 2010 next week in Sevile
Wire cross-section: 20 nm X 10 nm
010203040506070
1 10 100 1000Gate Length (nm)
I ON
(µA
/ w
ire)
nMOSpMOS
(5)
(5)
(10)
(10)(12)
(12x19)
(12)
(12x19)
(13x20)
(9x14)(10)
(10)
(10)
(8)
(8)
(16)
(13)
(34)
(3)(3)
(30)
(19)
VDD: 1.0~1.5 V
括弧内は寸法を示す
010203040506070
1 10 100 1000Gate Length (nm)
I ON
(µA
/ w
ire)
nMOSpMOS
010203040506070
1 10 100 1000Gate Length (nm)
I ON
(µA
/ w
ire)
nMOSpMOS
(5)
(5)
(10)
(10)(12)
(12x19)
(12)
(12x19)
(13x20)
(9x14)(10)
(10)
(10)
(8)
(8)
(16)
(13)
(34)
(3)(3)
(30)
(19)
VDD: 1.0~1.5 V
括弧内は寸法を示す
(12)
010203040506070
1 10 100 1000Gate Length (nm)
I ON
(µA
/ w
ire)
nMOSpMOS
(5)
(5)
(10)
(10)(12)
(12x19)
(12)
(12x19)
(13x20)
(9x14)(10)
(10)
(10)
(8)
(8)
(16)
(13)
(34)
(3)(3)
(30)
(19)
VDD: 1.0~1.5 V
括弧内は寸法を示す
010203040506070
1 10 100 1000Gate Length (nm)
I ON
(µA
/ w
ire)
nMOSpMOS
010203040506070
1 10 100 1000Gate Length (nm)
I ON
(µA
/ w
ire)
nMOSpMOS
(5)
(5)
(10)
(10)(12)
(12x19)
(12)
(12x19)
(13x20)
(9x14)(10)
(10)
(10)
(8)
(8)
(16)
(13)
(34)
(3)(3)
(30)
(19)
VDD: 1.0~1.5 V
括弧内は寸法を示す
010203040506070
1 10 100 1000Gate Length (nm)
I ON
(µA
/ w
ire)
nMOSpMOS
(5)
(5)
(10)
(10)(12)
(12x19)
(12)
(12x19)
(13x20)
(9x14)(10)
(10)
(10)
(8)
(8)
(16)
(13)
(34)
(3)(3)
(30)
(19)
VDD: 1.0~1.5 V
括弧内は寸法を示す
010203040506070
1 10 100 1000Gate Length (nm)
I ON
(µA
/ w
ire)
nMOSpMOS
010203040506070
1 10 100 1000Gate Length (nm)
I ON
(µA
/ w
ire)
nMOSpMOS
(5)
(5)
(10)
(10)(12)
(12x19)
(12)
(12x19)
(13x20)
(9x14)(10)
(10)
(10)
(8)
(8)
(16)
(13)
(34)
(3)(3)
(30)
(19)
VDD: 1.0~1.5 V
括弧内は寸法を示す
(12)
本研究で得られたオン電流
(10x20)102µA
Our Work
Bench Mark
Y. Jiang, VLSI 2008, p.34H.-S. Wong, VLSI 2009, p.92S. Bangsaruntip, IEDM 2009, p.297C. Dupre, IEDM 2008, p. 749S.D.Suk, IEDM 2005, p.735G.Bidel, VLSI 2009, p.240
Si nanowireFET
Planer FETS. Kamiyama, IEDM 2009, p. 431P. Packan, IEDM 2009, p.659
1.2~1.3V
1.0~1.1V
Lg=500~65nm
IIONON/I/IOFF OFF Bench markBench mark
This work
53
0
2
4
0
2
40
5
10
15
x 1019
x (nm)y (nm)
Electron density (/cm3)
024681012
02
46
810
120
5
10
15
x 1019
x (nm)y (nm)
Electron density (/cm3)
(a) (b) width=12nmwidth=4nm
0
2
4
0
2
4500
550
600
650
x (nm)y (nm)
Mobility (cm2/Vs)
024681012
02
46
810
12700
750
800
850
900
x (nm)y (nm)
Mobility (cm2/Vs)
(a) (b) width=12nmwidth=4nm
0
2
4
0
2
4500
550
600
650
x (nm)y (nm)
Mobility (cm2/Vs)
024681012
02
46
810
12700
750
800
850
900
x (nm)y (nm)
Mobility (cm2/Vs)
(a) (b) width=12nmwidth=4nm
0 .E + 0 0
1 .E + 1 9
2 .E + 1 9
3 .E + 1 9
4 .E + 1 9
5 .E + 1 9
6 .E + 1 9
0 2 4 6 8Distance from SiNW Surface (nm)
6543210
角の部分
平らな部分
電子濃度(x1019cm-3)Electron Density
Edge portion
Flat portion
0
2000
4000
6000
8000
10000
12000
2008 2010 2012 2014 2016 2018 2020 2022 2024 2026
Year
I ON
(µA/
µm)
SiNW (12nm×19nm)
MGFDbulk
ION∝Lg-0.5×Tox
-1(20)
(11)
(33)
(15)
(26)
今回用いたIONの仮定
1µm当たりの本数
コンパクトモデルの完成
S/D寄生抵抗低減技術
pMOSの高性能化
低EOT実現技術
Compact model
Small EOT for high-k
P-MOS improvement
Low S/D resistance
# of wires /1µm
Assumption
ITRSNan
owire
Primitive estimation !
HP MP SP
TOX,E (nm) 0.9 0.9 0.9
LGATE (nm) 30 34 34
IOFF (nA/um) 20-100 5-20 1-5
Tri-gate has been implemented at 22nm node, enabling further scaling
C. Auth et al., pp.131, VLSI2012 (Intel)
TriTri--gate implementation for transistors gate implementation for transistors
57
PMOS channel under the gate
S/D region showing the SiGe epitaxy
A fin width of 8nm to balance SCE and Rext
A fin height of 34nm to balance drive current vs. capacitance
C. Auth et al., pp.131, VLSI2012 (Intel)
TriTri--gate width/height optimizationgate width/height optimization
58
C. Auth et al., pp.131, VLSI2012 (Intel)
TriTri--gate Igate Idd--VVgg characteristics and Vcharacteristics and Vthth
・SS of 69 and 72mV/dec for NMOS and PMOS, respectively
・DIBL of 46 and 50mV/V for NMOS and PMOS, respectively
・Vth of 22nm is about 0.1V lower than that of 32nm
59
A. Khakifirooz et al., pp.117, VLSI2012 (IBM)
・Lg = 22nm ETSOI
・Si channel thickness of 6 nm
・DIBL of 75 mV/V and 130mV/V for NFET and PFET
Extremely Thin SOI (ETSOI)Extremely Thin SOI (ETSOI)
RSDwith silicide
RSDwith silicide
ETSOI 6nmBOX
Poly-Si Metal/high-k
60
TriTri--gate Igate IONON and Iand IOFFOFF characteristicscharacteristics
HP SP LP ULP
ION (mA/um) NMOS/PMOS 1.08/0.91 0.71/0.59 0.41/0.37 0.35/0.33
IOFF 100nA/um 1 nA/um 30 pA/um 15 pA/um
ION/IOFF ~105 ~106 ~108 ~108
Vdd = 0.75 V
C.-H. Jan et al ., pp.44, IEDM2012 (Intel)
NMOS PMOS
ION/IOFF > 105
S. Saitoh et al., pp.11, VLSI2012 (Toshiba)
・Lg = 14nm Tri-Gate NW
・High SCE immunity at Lg of 14nm
・Vth tuning by applying Vsub with thin BOX of 20nm
TriTri--Gate NanowireGate Nanowire
Vsub
H.-J. Cho et al., pp.350, IEDM2011 (Samsung)
・Lg = 20nm bulk planar CMOS
・Gate last integration
・In-situ doped S/D for better SCE
Bulk PlanarBulk Planar
Extremely Thin SOI (ETSOI)Extremely Thin SOI (ETSOI)
・Hybrid CMOSSi Channel nFETStrained SiGe Channel pFET・RO delay improvement over FinFET with FO = 2
K. Cheng et al., pp.419, IEDM2012 (IBM)
S. Bangsaruntip et al., pp.297, IEDM2009 (IBM)
・Lg = 25~35nm GAA NW
・Hydrogen anneal provide smooth channel surface
・Competitive with conventional CMOS technologies
・Scaling the dimensions of NW leads to suppressed SCE
Gate All Around Nanowire (GAA NW)Gate All Around Nanowire (GAA NW)
65
G. Bidal et al., pp.240, VLSI2009 (STMicroelectronics)
SiNHMTop Gate
Bottom Gate
Channel
iPtSi
・Gate all around structure
・Lg of 22~30nm
・Bulk wafer-based integration
・High drive currents by special stress and channel orientation design
Gate All Around Nanowire (GAA NW)Gate All Around Nanowire (GAA NW)
ΩΩ--gate Si Nanowiregate Si NanowireS. Sato et al., pp.361, ESSDERC2010 (Tokyo Tech.)
19 nm
12 nm
1.E-12
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
-1.5 -1.0 -0.5 0.0 0.5 1.010-12
Gate Voltage (V)
pFET nFET
10-11
10-10
10-9
10-8
10-7
10-6
10-5
10-4
10-3
Dra
in C
urre
nt (A
)
Vd=-50mV
Vd=-1V
Vd=50mV
Vd=1V
1.E-12
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
-1.5 -1.0 -0.5 0.0 0.5 1.010-12
Gate Voltage (V)
pFET nFET
10-11
10-10
10-9
10-8
10-7
10-6
10-5
10-4
10-3
Dra
in C
urre
nt (A
)
Vd=-50mV
Vd=-1V
Vd=50mV
Vd=1V
0 0.5 1 1.5 2ION (mA/µm)
Lg=65nm
0 0.5 1 1.5 2ION (mA/µm)
Lg=65nm
Lg=65nm
Poly-Si
SiO2
SiNSiN
SiO2
NW
・Conventional CMOS process
・High drive current
(1.32 mA/µm @ IOFF=117 nA/µm)
・DIBL of 62mV/V and SS of 70mV/dec for nFET
ShortShort--channel effectchannel effectT. Skotnicki, IEDM 2009 Short Course (STMicroelectronics)
S. Bangsaruntip et al., pp.297, IEDM2009 (IBM), K. Tachi et al., pp.313, IEDM2009 (CEA-LETI)
Decreasing the diameter of NW
Problems in MultiProblems in Multi--gategate
Improvedshort-channel control
Severe mobility degradation
69
K. Uchida et al., pp.47, IEDM2002 (Toshiba)
Problems in SOIProblems in SOI
Mobility is also decreased with decreasing the Si thickness of SOI transistor similar to the NW transistor.
70
When wire diameter becomes less than 10 nm, sudden drop of Id
Problem for nanowire
IdDiameter
10 nm2. Decrease of DOS
1. Electron Scattering of every surface
If diameter cannot be scaled, SCE cannot be suppressed.
Then, again aggressive EOT scaling of high-k is necessary.
K. Kim, pp.1, IEDM2010 (Samsung) 1.21.1
1
0.9
0.8
0.7
0.6
0.5
EO
T [n
m]
202020152010Year
12
10
8
6
4
2
0
Body Thickness [nm
]
Multi-Gate
Planar
ITRS2011
Fin width
Trend 1
Trend 2Trend 3 ?
EOT Scaling TrendsEOT Scaling Trends
Wire/fin mitigates EOT thinning trend (Trend 1 Trend 2)Because of better SCE control.
However, ION severely degrade with wire/fin width reduction
Therefore, EOT trend will become accelerated again(Trend 2 Trend 3) Thus, high-k becomes important again.72
High-k beyond 0.5 nm
Limit in tLimit in toxox thinningthinning
R.Chau, et al., (Intel) IWGI 2003
74
Gate oxide should be thicker than mono atomic layer
0.8 nm gate oxide thickness MOSFETs operate0.8 nm Distance of 3 Si atoms 2 mono layers
Limit in tLimit in toxox thinningthinningR.Chau, et al., (Intel) IWGI 2003
1 0.010.1
1
10
100
1000
0.1
0.01
0.001
Pow
er D
ensi
ty [W
/cm
2 ]
Gate Length [µm]
Active Power
Passive PowerGate
Leakage
Gate Leakage Power Density becomes significantly large with Lg reduction, and thus, with tox thinning!!
W.F.Clark, (IBM) VLSI 2007 Short Course
75
To use high‐k dielectrics
Thin SiO2
Thick high‐k dielectrics
Almost the same electric characteristics
However, very difficult and big challenge!
K: Dielectric Constant
5 times thicker
Small leakageCurrent
K=4K=20
SolutionSolution
SiO2 High‐k
76
Equivalent Oxide Thickness (EOT)Equivalent Oxide Thickness (EOT)
Silicon Substrate
S D
Silicon Substrate
S D
SiO2
Poly-Si
C Poly
COX
CSi
High-kCOX
CSi
Equivalent Oxide Thickness (EOT): gate dielectrics itself, Cox
Capacitance Equivalent Thickness (CET): entire gate stack,
Metal gate can eliminate the poly-Si depletion.
Inversion CET = Tinv ≈ EOT + 0.4nm with metal gate electrode
Metal
Cmetal
Poly-Si(1020cm-3)
K. Natori, et al., (Tsukuba Univ) SSDM 2005, p.286
CMetal(EOT: 0.1 nm)
Depletion
Cmetal is finite because of quantum effect. In other words electron is not a point charge located at the interface but distributed charge.
(EOT: 0.3 nm)
Combination of high-k and metal gate is important
77
Si-sub.
Metal
SiO2-IL
High-kSmall interfacial state density at high-k/Si
Oxygen diffusion control for prevention of EOT increase and oxygen vacancy formation in high-k
Thinning or removal of SiO2-IL for small EOT
Flat metal/high-k interface for better mobility
O
Workfunction engineering for Vth control
Interface dipole control for Vth tuning
Suppression of oxygen vacancy formation
Control of interface reaction and Si diffusion to high-k
Oxygen concentration control for prevention of EOT increase and oxygen vacancy formation in high-k
Suppression of metal diffusion
Endurance for high temperature process
Remove contaminationintroduced by CVD
Reliability: PBTI, NBTI, TDDB
Suppression of gate leakage current
Suppression of FLP
78
Issues in high-k/metal gate stack
0 10 20 30 40 50Dielectric Constant
4
2
0
-2
-4
-6
SiO2
Ban
d D
isco
ntin
uity
[eV]
Si
XPS measurement by Prof. T. Hattori, INFOS 2003
Conduction band offset vs. Dielectric Constant
Band offset
Oxide
Leakage Current by Tunneling
79
R. Hauser, IEDM Short Course, 1999Hubbard and Schlom, J Mater Res 11 2757 (1996)
Gas or liquidat 1000 K
H
Radio activeHe
Li BeB C N O F Ne
① Na Mg Al Si P S Cl Ar
② ① ① ① ① ① ① ① ① ① ① K Ca Sc Ti V Cr Mn Fc Co Ni Cu Zn Ga Ge As Se Br Kr ① ① ① ① ① ① ① ① ① ① Rh Sr Y Zr Nb Mo Tc Ru Rb Pd Ag Cd In Sn Sb Te I Xe ③ ① ① ① ① ① ① ① Cs Ba
HfTa W Re Os Ir Pt Au Hg Tl Pb Bi Po At Rn
Fr Ra Rf Ha Sg Ns Hs Mt
La Ce Pr Nd PmSmEu Gd Tb Dy Ho Er TmYb Lu Ac Th Pa U Np Pu Am Cm Bk Cf Es Fm Md No Lr
Candidates
Na Al Si P S Cl Ar
② ① ① ① ① ① ① ① ① ① K Sc Ti V Cr Mn Fc Co Ni Cu Zn Ga Ge As Se Br Kr ① ① ① ① ① ① ①
Ac Th Pa U Np Pu Am Cm Bk Cf Es Fm Md No Lr
②
③
Unstable at Si interfaceSi + MOX M + SiO2①
Si + MOX MSiX + SiO2
Si + MOX M + MSiXOY
Choice of High-k elements for oxide
HfO2 based dielectrics are selected as the first generation materials, because of their merit in1) band-offset, 2) dielectric constant3) thermal stability
La2O3 based dielectrics are thought to be the next generation materials, which may not need a thicker interfacial layer
80
SiO2-ILHfSix (k~4)
VO
IO
IOVO
VO
IOIO
VOHfO2
Si substrate SiO2-IL(k~4)
LaSix
VO
IOVO
IO
VO
IOLa2O3silicate
La-rich Si-rich
Si substrate
High PO2Low PO2 High PO2Low PO2
SiO2 IL formation
Si substrate
silicate formation
Si substrate
HfO2 case La2O3 case
Direct contact can be achieved with La2O3 by forming silicate at interfaceControl of oxygen partial pressusre is the key for processing.
Our approach
K. Kakushima, et al., VLSI2010, p.69
Direct high-k/Si by silicate reaction
82
1837184018431846Binding energy (eV)
Inte
nsity
(a.u
)
Si sub.
Hf SilicateSiO2
500 oC
1837184018431846Binding energy (eV)
Inte
nsity
(a.u
)
Si sub.
Hf SilicateSiO2
500 oC
SiOx-IL
HfO2
W
1 nm
k=4
k=16
SiOx-IL growth at HfO2/Si Interface
HfO2 + Si + O2→ HfO2 + Si + 2O*→HfO2+SiO2
Phase separator
SiOx-IL is formed after annealingOxygen control is required for optimizing the reaction
Oxygen supplied from W gate electrode
XPS Si1s spectrum
D.J.Lichtenwalner, Tans. ECS 11, 319
TEM image 500 oC 30min
H. Shimizu, JJAP, 44, pp. 6131
83
La-Silicate Reaction at La2O3/Si
La2O3
La-silicate
W
500 oC, 30 min
1 nm
k=8~14
k=23
1837184018431846Binding energy (eV)
Inte
nsity
(a.u
)
as depo.
300 oC
La-silicate
Si sub.
500 oC
1837184018431846Binding energy (eV)
Inte
nsity
(a.u
)
as depo.
300 oC
La-silicate
Si sub.
500 oC
La2O3 + Si + nO2→ La2SiO5, La2Si2O7,
La9.33Si6O26, La10(SiO4)6O3, etc.
La2O3 can achieve direct contact of high-k/Si
XPS Si1s spectraTEM image
Direct contact high-k/Si is possible
84Year
Pow
er p
er M
OSF
ET (P
)
P∝L
g 3
(Scaling)
EOT Limit0.7~0.8 nm
EOT=0.5nm
TodayEOT=1.0nm
Now
45nm node
One order of Magnitude
Si
HfO2
Metal
SiO2/SiON
Si
High-k
Metal
Direct ContactOf high-k and Si
Si
MetalSiO2/SiON
0.5~0.7nm
Introduction of High-kStill SiO2 or SiONIs used at Si interface
For the past 45 yearsSiO2 and SiON
For gate insulator
EOT can be reduced further beyond 0.5 nm by using direct contact to SiBy choosing appropriate materials and processes.
85
Substrate
Moving Mask
SourceElectron Beam
Flux
Deposited thin film
準備室
絶縁膜堆積室フラッシュランプアニール室
金属膜堆積室
ロボット搬送室
ALD室
RTA室
Robot
EB Evaporation Flash Lamp Anneal
ALD
RTA
Sputter
EB Evaporation
Flash Lamp Anneal
ALDRTAEntrance
Entrance
Sputter
High-k/metal gate stackfilm deposition cluster tool
87
L=0.5~100µm (8 kinds)W=10, 20, 50, 100µm(4 kinds)
30 different Trs
26 c
hips
1cm
1cm
1cm×1cm
p-Si
S Dn+ Sn+SiO2
88
Shutter movement
Chip
Si Si SiSi
Metal Metal Metal Metal
Thin Thick
high-k
15cm
0.0E+00
5.0E-04
1.0E-03
1.5E-03
2.0E-03
2.5E-03
3.0E-03
3.5E-03
0 0.2 0.4 0.6 0.8 1
Vg=0VVg=0.2VVg=0.4VVg=0.6VVg=0.8VVg=1.0VVg=1.2V
0 0.2 0.4 0.6 0.8 1
Vg=0VVg=0.2VVg=0.4VVg=0.6VVg=0.8VVg=1.0VVg=1.2V
0 0.2 0.4 0.6 0.8 1
Vg=0VVg=0.2VVg=0.4VVg=0.6VVg=0.8VVg=1.0VVg=1.2VI d
(V)
Vth=-0.04VVth=-0.05VVth=-0.06V
1.E-05
1.E-04
1.E-03
1.E-02
1.E-01
1.E+00
1.E+01
0 0.5 1 1.5 2 2.5 3
EOT ( nm )
Cur
rent
den
sity
( A
/cm
2 )Al2O3HfAlO(N)HfO2HfSiO(N)HfTaOLa2O3Nd2O3Pr2O3PrSiOPrTiOSiON/SiNSm2O3SrTiO3Ta2O5TiO2ZrO2(N)ZrSiOZrAlO(N)
Gate Leakage vs EOT, (Vg=|1|V)
La2O3
HfO2
89
90
2
1.5
1
0.5
0
Cap
acita
nce
[µF/
cm2 ]
-1 -0.5 0 0.5 1Gate Voltage [V]
10kHz 100kHz 1MHz
20 x 20µm2 1.5
1
0.5
0
Cap
acita
nce
[µF/
cm2 ]
-1.5 -1 -0.5 0 0.5Gate Voltage [V]
20 x 20µm2
10kHz 100kHz 1MHz
2
1.5
1
0.5
0
Cap
acita
nce
[µF/
cm2 ]
-1.5 -1 -0.5 0 0.5Gate Voltage [V]
20 x 20µm2
10kHz 100kHz 1MHz
FGA500oC 30min FGA700oC 30min FGA800oC 30min
A fairly nice La-silicate/Si interface can be obtained with high temperature annealing. (800oC)
However, high-temperature anneal is necessary for the good interfacial property
91
① silicate-reaction-formedfresh interface
metal
Si sub.
metal
Si sub.
La2O3 La-silicateSi Si
Fresh interface with silicate reaction
J. S. Jur, et al., Appl. Phys. Lett., Vol. 87, No. 10, (2007) p. 102908
② stress relaxation at interface by glass type structure of La silicate.
La atomLa-O-Si bonding
Si sub.
SiO4tetrahedron network
FGA800oC is necessary to reduce the interfacial stress
S. D. Kosowsky, et al., Appl. Phys. Lett., Vol. 70, No. 23, (1997) pp. 3119
Physical mechanisms for small DitPhysical mechanisms for small Dit
92
No interfacial layer can be confirmed with Si/TiN/W
MIPSW TiN/W
Kav ~ 8 Kav ~ 12 Kav ~ 16
Si 2nm2nm2nm
HK
MG
La2O3Si/TiN/W
La2O3/silicate/n-Si CV
-0.5-1.0-1.5 0.0 0.5Gate voltage (V)
3
2
1
0
Cap
acita
nce
dens
ity (µ
F/cm
2 )
W/La2O3(4nm)/n-Si600oC, 30min
∆Vfb
Cfb
1MHz
1kHz
0.0E+00
5.0E-07
1.0E-06
1.5E-06
2.0E-06
2.5E-06
3.0E-06
1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07
Gp/ω
(F/c
m2 )
0.0
0.5
1.0
2.0
2.5
(×10-6)3.0
ω (rad/s)
1.5
10 103 104 105 106 107102
400
500
600
Dit, Dslow(FG anneal)
Dit
, Dsl
ow(c
m-2
/eV
)
1014
1013
1012
1011
Annealing temperature (oC)as 200 400 600 800 1000
Dit
Dslow
Dit
Dslow
Annealing temperature (oC)
10-11
σ it,
σ slo
w(c
m2 )
10-12
10-13
10-14
10-15
∆Vfb
(V)
-0.1
-0.2
-0.3as 200 400 600 800 1000
0.0
Dslow=2.8x1013cm-2/eV
∆Vfb=CLa2O3/qDslow
⎟⎠⎞
⎜⎝⎛−=
λσσ silicate
slowtexp0 (λ=0.8nm)
Slow trap state
σslow
σit
La2O3
silicate (tsilicate)
Dit
DslowVg
Ef
n-Si
CLa2O3
It is important to change the La2O3 to La-silicate completely
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
600 700 800 900 1000As depo
~ ~
Annealing temperature (oC)
EOT
(nm
)
Annealed for 2 sLa2O3(3.5 nm)
W(60 nm)
TiN/W(12 nm)
TiN/W(6 nm)
TiN(45nm)/W(6nm)
00.5
11.5
22.5
33.5
44.5
-1 -0.5 0 0.5
Vg (V)
Cg
(uF/
cm2 )
Experiment
Cvc fittingTheory
EOT=0.55nm
TaN/(45nm)/W(3nm)900oC, 30min
EOT=0.55nm
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.5 0.55 0.6 0.65 0.7
Flat
-ban
d vo
ltage
(V)
EOT(nm)
TaN(45nm)/W(3nm)
900oC, 30min
Qfix=1×1011 cm-2
Fixed Charge density: 1×1011 cm-2
0
20
40
60
80
100
120
140
160
180
0 0.5 1 1.5 2
EOT = 0.53nm
L/W = 20/20µm
T = 300K
Nsub = 3×1016cm-3
Eeff [MV/cm]
Elec
tron
Mob
ility
[cm
2 /Vse
c]Si-sub
SiO2S D
Si-sub
Si-sub
La2O3W AlTaN/ 熱処理
151cm2/VsEeff=1MV/cm150cm2/Vs
0 0.2 0.4 0.6 0.8 1.0
Drain Voltage (V)
5010
015
020
025
0
Dra
in C
urre
nt (µ
A)
Vg= 0.4V
Vg= 0.6V
Vg= 0.8V
Vg= 1.0V
Vg= 0.2VVg= 0 V
L/W = 20/20µm
T = 300K
Nsub = 3×1016cm-3
300
EOT = 0.53nm
EOT=0.53nm
10-5
10-4
10-3
10-2
10-1
100
101
103
104
0.0 0.2 0.4 0.6 0.8 1.0 1.2
Gate voltage (V)
Gat
e cu
rrent
(A/c
m2 )
102
ITRSの要求値
x1/100
Wg/Lg=20/20µmEOT=0.55nm
TaN/W/LaSiOx/nFET
0 0.2 0.4 0.6 0.8 1.0
Drain Voltage (V)
0.2
0.4
0.6
0.8
1.0
Dra
in C
urre
nt (m
A)
Vg= 0.4V
Vg= 0.6V
Vg= 0.8V
Vg= 1.0V
Vg= 0.2V
Vg= 0 V
L/W = 5/20µm
T = 300K
Nsub = 3×1016cm-3
0
20
40
60
80
100
120
140
0 0.5 1 1.5 2 2.5
EOT = 0.40nm
L/W = 5/20µm
T = 300K
Nsub = 3×1016cm-3
Eeff [MV/cm]El
ectr
on M
obili
ty [c
m2 /V
sec]
EOT=0.40nm
1.E-02
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
0.3 0.4 0.5 0.6 0.7 0.8
ITRS requirement
J gat
1 V
(A/c
m2 )
EOT (nm)
Benchmark of LaBenchmark of La--silicate dielectricssilicate dielectrics
Gate leakage is one order of magnitude lower than that of ITRS.
Electron mobility is comparable to record mobility with Hf-based oxides.
T. Ando, et al., (IBM) IEDM 2009, p.423
0
50
100
150
200
250
300
0.3 0.4 0.5 0.6 0.7 0.8 0.9 1EOT (nm)
Mob
ility
(cm
2 /Vse
c)
at 1 MV/cm
Open : Hf-based oxidesSolid : La-silicate oxide
L.-Å. Ragnarsson, et al., (IMEC) Microelectron. Evol. 88, no. 7, pp. 1317–1322, Jul. 2011.
T. Kawanago, et al., (Tokyo Tech.) T-ED, vol. 59, no. 2, p. 269, 2012
Si benchmark (nMOSFET)Si benchmark (nMOSFET)
102
EOT Mobility Vth SS DIBLGate stack Ref.
0.45nmTiN/Cap/HfO2 115cm2/Vs
(at 1x1013cm-2)IMEC
MEE20110.3V
(Lg=10um)
0.52nmTiN/Cap/HfO2 110cm2/Vs
(at 1x1013cm-2)IBM
VLSI2011~0.4V
(Lg=24nm) 90mV/dec 147mV/V
0.59nmMetal/HfO2 130cm2/Vs
(at 1MV/cm)0.45V
(Lg=1um) 75mV/decSematechVLSI2009
0.65nmMetal/Hf-basedSamsungVLSI2011
0.3~0.4V(Lg=~30nm) 90mV/dec 100mV/V
0.95nmMetal/Hf-basedIntel
IEDM2009~0.3V
(Lg=30nm) 100mV/dec ~200mV/V
0.62nmW/La-silicateTokyo Tech.T-ED2012
-0.08V(Lg=10um) ~70mV/dec
155cm2/Vs (at 1MV/cm)
0.55nmTiN/Cap/HfO2 140cm2/Vs
(at 1MV/cm)IBM
VLSI2009
0 0.2 0.4 0.6 0.8 1.0
Drain Voltage (V)
5010
015
020
025
0
Dra
in C
urre
nt (µ
A)
Vg= 0.4V
Vg= 0.6V
Vg= 0.8V
Vg= 1.0V
Vg= 0.2VVg= 0 V
L/W = 20/20µm
T = 300K
Nsub = 3×1016cm-3
300
EOT = 0.53nm
0
20
40
60
80
100
120
140
160
180
0 0.5 1 1.5 2
EOT = 0.53nm
L/W = 20/20µm
T = 300K
Nsub = 3×1016cm-3
Eeff [MV/cm]El
ectr
on M
obili
ty [c
m2 /V
sec]
Recent results by my group.
substrate
①La gas feed ②Ar purge ③H2O feed ④Ar purge
Laligand H
O
substrate substrate substrate
1 cycle
La
C 3H7
3
L a
C 3H7
3
L a
C 3H7
3
CLaN
NH
C3H7
C3H7
La(iPrCp)3 La(FAMD)3
Precursor (ligand)
ALD is indispensable from the manufacturing viewpoint- precise control of film thickness and good uniformity
K. Ozawa, et al., (Tokyo Tech. and AIST) Ext. Abstr. the 16th Workshop on Gate Stack Technology and Physics., 2011, p.107.
104
ALD of La2O3
S D
1) High injection Velocity of carriers
2) High mobility of carriers
Both 1) and 2) are important
Arming higher performance at lower supply voltage
Problems: Technologies and CostInterfacial properties at the gate insulator/semiconductor
Contact resistance at Source/Drain and semiconductor
Different semiconductors for n- and p- channel FETs
Integration on Si wafer
vinj
III-V (n-channel) or Ge (p-channel)
105
Why high mobility channel materials?
Ge,IIIGe,III--V bulk properties V bulk properties
S. Takagi., IEDM2011, Short course (Tokyo Uni)106
Metal S/D InGaAs‐OILch= 55nm, EOT 3.5nmVDS=0.5V(Tokyo Uni.)[5]
InGaAs NanowireLg= 200nm, Tox 14.8nmVDS=0.5V(Hokkaido Uni.)[4]
InGaAs FinFETLch=130nmEOT 3.8nmVDS=0.5V (NUS)[3]
InGaAs Tri‐gateLg=60 nm,EOT 12AVDS=0.5V (Intel) [2]
InGaAs GAALch=50nm, Dielectric: 10nm Al2O3VDS=0.5V (Purdue Uni.) [1]
Ge Tri‐gateLg=183nm, EOT 5.5nmVD=‐1V (NNDL Taiwan)[9]
Ge GAA Lg= 300nm, dielectric: GeO2(7nm)‐HfO2(10nm)VD= ‐0.8V (ASTAR Singapore)[8]
Ge FinFETLg=4.5 mm, Dielectric: SiON, VDS=‐1V(Stanford Uni.)[7]
GOI Tri‐gateLg: 65nm. EOT 3.0nmVD=‐1V (AIST Tsukuba)[6]
Si‐bulk 45nmIntel VDD=1V
I OFF(A/µm)
ION (mA/µm)
nMOS pMOS
ION (mA/µm)[1] J. J. Gu et al., pp.769, IEDM2011 (Purdue).[2] M. Radosavljevic et al., pp.765, IEDM201(Intel).[3] H. –C. Chin et al., EDL 32, 2 (2011) (NUS)[4] K. Tomioka et al., pp.773, IEDM2011 (Hokkaido Uni).
[6] K. Ikeda et al., pp.165, VLSI2012 (AIST, Tsukuba).[7] J. Feng et al., IEEE EDL 28(2007)637 (Stanford Uni)[8] J. Peng et al., pp.931, IEDM2009 (ASTAR Singapore)[9] S. Hsu et al., pp.825, IEDM2011 (NNDL Taiwan)
[5] S. H. Kim et al., pp.177, VLSI2012 (Tokyo Uni)
Si‐bulk 45nmIntel VDD=1V[11]
Si‐FinFET 32nmIntel VDD=0.8V [10]
Si‐FinFET 32nmIntel VDD=0.8V [10]
[10] C. Auth et al., pp.131, VLSI2012 (Intel).
[11] K. Mistry et al., pp.247, IEDM2007 (Intel).
Si‐FinFET 22nmIntel VDD=0.8V [10]
Si‐FinFET 22nmIntel VDD=0.8V [10]
MultiMulti--gate IIIgate III--V and Si benchmarkV and Si benchmark
107
ION/IOFF Benchmark of Ge pMOSFET
108
Planar(metal S/D, Strain, Buffer…)
FinFET Tri‐gateGate‐all‐around
MOSFETNanowire
material InGaAs Ge InGaSn InGaAs Ge InGaAs Ge InGaAs Ge InGaAs(multishell)
Ge
Dieletric/EOT
Al2O3/ 3.5 nm
7.6 Ao
HfO2+ Al2O3+GeO2
5nm ALDAl2O3
5nm ALD Al2O3
SiON 1.2 nm5.5 nm(Al2O3+GeO2)
10nm‐ALD Al2O3
HfO2:11nm
HfAlO14.8 nm
3.0 nm(ALD Al2O3)
Mobility ‐ ~600(cm2/Vs)
e: 200h: 400
~700(µS/µm)
‐ ‐ ‐ 701(µS/µm)
‐ ~500(µS/µm)
~850(cm2/Vs)
Lch (nm) 55W/L=
30/5 µm50 µm 100 4.5 µm 60 183 50 200 200 65
DIBL(mV/V)
84 ‐ ‐ 180 ‐ ~50 ‐ 210 ‐ ‐ ‐
SS(mV/dec)
105 ‐61pMOS33nMOS
145 750 90 130 150 160 ‐ ‐
ION(µA/µm)
278(VD=0.5V)
3(VD=‐0.2V)
4 (n,p)(VD=0.5V)
‐ 10(VD=0.5V)
400(VD=0.5V)
235(VD=‐1V)
180(VD=0.5V)
604(VD=‐0.5V)
100(VD=0.5V)
731(VD=‐1V)
ResearchGroup
Tokyo UniVLSI 2012
Tokyo UniVLSI 2012
Stanford Uni VLSI 2012
Purdue Uni IEDM 2009
Stanford Uni ELD 2007
IntelIEDM 2011
NNDL Taiwan
IEDM 2011
Purdue Uni IEDM 2011
ASTARSingapore IEDM 2009
Hokkaido Uni, IEDM
2011
AIST Tsukuba VLSI 2012
150K
120K
(cm2/Vs)
Ns: 5e12
III-V/Ge benchmark for various structures
109
2012 2016 2018 2020 2022
Lg (nm)
Vdd (V)
EOT (nm)
Mobility enhancementfactor due to strain
CV/I (ps)
BulkFD SOI∗1: MG
Year of Production
∗1: Thicker EOT for MG(Multiple gate : Fin/Tri gate, nanowire)
2024 2026
Cg Ideal(fF/µm)
BulkFD SOI
MGBulk
FD SOIMGBulk
FD SOIMG
Vt,sat (mV)
2014
22 18 15.3 12.8 10.6 8.9 7.4 5.9
0.87 0.82 0.77 0.73 0.68 0.64 0.61 0.570.84 0.73 0.61
0.8 0.72 0.63 0.540.76 0.68 0.62 0.56 0.50 0.45
1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8
0.658 0.611 0.576
0.57 0.47 0.380.38 0.30 0.24 0.20
0.29 0.24 0.19 0.16 0.13 0.10
289 302 310222 227 234 242
217 223 225 228 231 237
0.529 0.429 0.3930.455 0.409 0.362 0.320 0.284 0.238
NMOS
Manufacturing solutionsexist or is being optimized
Manufacturing solutionsare known
Manufacturing solutionsare NOT known110
ITRS 2011 for Si (HP: High Performance Logic)
2012 2016 2018 2020 2022
Lg (nm)Equivalent
Injection velocity Vinj (107 cm/s)
BulkFD SOI
MG
Year of Production 2024 2026
Id,sat(mA/µm)
BulkFD SOI
MG
BulkFD SOI
MGBulk
FD SOIMG
Rsd (Ω-µm)
2014
CV2
(fJ/µm)
Isd,leak (nA/µm)
22 18 15.3 12.8 10.6 8.9 7.4 5.91.09 1.18 1.33
1.37 1.51 1.63 1.831.68 1.82 2.05 2.26 2.38 2.67
1.685 1.805 1.916 2.030 2.152 2.308
1.6701.367 1.4961.654 1.791 1.9421.530
100 100 100 100 100 100 100 100232 183 149
274 228 187 153257 218 186 160 133 104
0.47 0.38 0.32 0.260.38 0.31 0.25 0.21 0.17 0.14
0.490.68 0.57
Manufacturing solutionsexist or is being optimized
Manufacturing solutionsare known
Manufacturing solutionsare NOT known
111
ITRS 2011 for Si (HP),contd
2018 2022 2024 2026
Lg (nm)
Vdd (V)
EOT (nm)Mobility enhancement
factor due tochannel material
Year of Production 2020
14 11.7 9.3 7.4 5.80.63 0.61 0.58 0.56 0.540.68 0.62 0.56
8 8 8 8 80.50 0.45
4 4 4 4 4GeIII-V
0.28 0.24 0.20 0.16 0.130.41 0.36 0.30 0.25 0.21Ge
III-VCg Ideal(fF/µm)
229 230 238 245 251230 231 241 249 254Ge
III-VVt,sat (mV)
0.13 0.11 0.09 0.07 0.060.21 0.17 0.13 0.10 0.08Ge
III-VCV/I (ps)
Manufacturing solutionsare NOT known
112
ITRS 2011 for III-V/Ge
2018 2022 2024 2026
Lg (nm)
Year of Production 2020
14 11.7 9.3 7.4 5.84.29 4.58 5.32 5.93 6.642.26 2.44 2.86 3.19 3.63Ge
III-V
2.200 2.343 2.523 2.703 2.8841.769 1.932 2.121 2.330 2.555Ge
III-V
131 113 96 82 70149 126 105 85 72Ge
III-V
0.18 0.15 0.13 0.11 0.090.23 0.20 0.16 0.14 0.11Ge
III-V
Equivalent Injection velocity
Vinj (107 cm/s)
Id,sat(mA/µm)
Isd,leak (nA/µm) 100 100 100 100 100Rsd
(Ω-µm)
CV2
(fJ/µm)
Manufacturing solutionsare NOT known
113
ITRS 2011 for III-V/Ge, Contd
Carbon‐based FET
Gate length (nm)10010Cu
t‐off frequ
ency ( GHz)
L. Liao, et al., Nature ,Vol.467 p.305.
F. Schwlerz, Nature Nano ,Vol.5 p.487.
GaAs mHEMT(20nm) SiMOSFET
(29nm)GaAs pHEMT(100nm)
100
1000
10
CNT
Graphene
J. P. Colinge et al., Nature Nano. 5(2010)225
A. D. Franklin et al., pp.525, IEDM2011 (IBM)
J. P. Colinge et al., Nature Nano. 5(2010)266
Junctionless Transistor
All‐spin logic device
1000
M. Lemme, Nanotech workshop ,2012
Input and output related via Spin-coherent channel
Emerging devices(future scaling trends)Emerging devices(future scaling trends)Carbon nanotube Graphene
A. Seabaugh, IEDM 2011 Short Course (University of Notre Dame)
Low IOFF, Low VDD, SS<60mV/decade
Tunnel FETTunnel FET
Band to band tunneling
VDD 0.3~0.35VTFET 8x faster at the same power“parameter variation is not a significant factor for differentiation between MOSFET and TFET”
A. Seabaugh, IEDM 2011 Short Course (University of Notre Dame)
TFET vs. MOSFET at low VTFET vs. MOSFET at low VDDDD
116
A. Villalon, pp.49, VLSI 2012 (CEA-LETI)
190mV/dec
Tunnel FET (Si)Tunnel FET (Si)
X in Si1-xGex is optimized to allow for efficient BTBT
Gate Voltage (V)
Reducing SiGe Body thickness improvesSubthreshold swing.
LG= 200nm
130mV/dec
ION/IOFF~105
117
VDS=1V
K. Tomioka et al., pp.47, VLSI2012 (Hokkaido University)
SS=110mV/decSS=21mV/dec
VDS= 1V
HfAlOx
Gate
NW Diameter= 30nmSS of TFET is function of VG due to Zener tunnel current
Tunnel FET (IIITunnel FET (III--V)V)
Conventional FET limitSS= 60 mV/dec
Minimum SS= 21 mV/dec is reached due to optimized series resistance of contact, undoped InAs and InAs/SiION/IOFF~106 at VDS= 1.0V (ION= 1Aµ/µm) 118
K. Tomioka et al., pp.47, VLSI2012 (Hokkaido University)
A. Seabaugh, IEDM 2011 Short Course (University of Notre Dame)
Device structureDevice structure
119
A. Seabaugh, IEDM 2011 Short Course (University of Notre Dame)
measured III-V channel TFETs
Tunnel FET performance comparisonTunnel FET performance comparison
Is the average swing when VTH=VDD/2VOFF=0
Most common SS which is the inverse of ID-VGS slopeat the steepest part
SMIN:
SEFF:
VGS
I D
Ith
IOFF
VTHVoff
Average SS:
VTH=VDD/2
Effective SS:
VOFF=0
120
Near-ideal subthreshold slope, close to 60 mV/dec at room temperature, and extremely low leakage currents
ION/IOFF~1x106Silicon nanowire is uniformly doped
J. P. Colinge et al., Nature Nano. 5(2010)225
Gate material is oppositepolarity polysilicon
Lg= 1µm
10nm
30.5nm
Lg= 1µmWwire= 30nm
Nanowire Junctionless TransistorNanowire Junctionless Transistor
(-1<Vg<1)IOFFis smaller than 10-15 A
K. Banerjee, UC Santa Barbara, G-COE PICE International Symposium on Silicon Nano Devices in 2030
Carbon nanotube and GrapheneCarbon nanotube and Graphene
SWCNT : single wall carbon nanotubeGNR : graphene nano ribbon
Carbon materials for FET applications ・ an ultra-thin body for aggressive channel length scaling・ excellent intrinsic transport properties similar to carbon nanotubes・ pattern the desired device structures
A. D. Franklin et al., pp.525, IEDM2011 (IBM)
SubSub--10nm carbon nanotube transistor10nm carbon nanotube transistor
Transistor operation with Lch of 9nm
Z. Chen et al., pp.509, IEDM2008 (IBM)
Graphene FieldGraphene Field--effect Transistoreffect TransistorJ. B. Oostinga et al., Nature Materials 7 (2008) 151
・Ambipolar Characteristics
・Bi-layer graphene and double gates can open the gap
H. Wang et al., pp.88, IEDM2012 (MIT)
2D material : single layer MoS2D material : single layer MoS22
・Mobility of 190 cm2/Vsec・Ion of 1 µA/µm at VDD = 1V
Candidate : MoS2, MoSe2, WS2, WSe2, MoTe2, WTe2
Advantage Issues
TFETLower Vdd
Lower IOFF
Integrationhigher ION
CNT FETHigher transport velocity
Lg scaling
High density and alignment, reproducibility,
integration
Graphene FETRF application
Large area manufacturingNOT a direct replacement
for Silicon logic
MEMS Extremely low leakage Ultra-low digital logic
EnduranceSlow speed, scalability
Junctionless FET CMOS process compatibility
Worse gate control in short-channel
Spin FETLow power, suitable for
memory (nonvolatile info storage)
Low efficiency of spin injection
Summary of Emerging Technology pro/consSummary of Emerging Technology pro/cons
T. Marukame et al., pp.215, IEDM2009 (Toshiba)
Magnetic tunnel junction on S/D
Read/write are enabled by using ferromagnetic electrodes and Spin-polarized current
Lg = 1µm
Spin transfer Torque Switching MOSFETSpin transfer Torque Switching MOSFET
[1] G. Zhou et al., pp. 782, vol. 33, no. 6, EDL 2012 (University of Notre Dame)
IIONON and Iand IOFFOFF of TFETsof TFETs
C. Auth et al., pp.131, VLSI2012 (Intel).K. Mistry et al., pp.247, IEDM2007 (Intel).
0.01
0.1
1
10
100
1000
10000
0.01 0.1 1 10ION [mA/µm]
I OFF
[nA
/µm
]
TFET VDS=1V
Si MOSFET
IntelBulk 32nmVDD=0.8V
IntelTri-Gate 22nmVDD=0.8V
Intel Bulk 45nmVDD=1V
TFET VDS=0.75V
TFET VDS=1.05V
128
ION/IOFF of ~1010
T. K. Liu et al., pp. 43, VLSI2012 (UC Berkeley)
ON
-sta
te re
sist
ance
[Ohm
]
Number of Operation Cycles
Ultra-low-power digital logic applications.
Frequency of 1, 5, 25kHz under operation
Mechanical Switch: MEMS relayMechanical Switch: MEMS relay
129
Metal (Silicide) S/D
Extreme scaling in MOSFET Lphy
Dop
antC
onc. δ δGate
σ σ
Met
al C
onc.
Gate
Lphy = Leff- Atomically abrupt junction- Lowering S/D resistances- Low temperature process for S/D
Metal Schottky S/D junctions
- Dopant abruptness at S/D- Vt and ION variation- GIDL
Schottky Barrier FET is a strong candidate for extremely scaled MOSFET S DChannel
S DChannel
n+-Sin+-Si
Metal Silicide
Metal Silicide
132
Surface or interface controlDiffusion species:
metal atom (Ni, Co)Rough interface at silicide/Si- Excess silicide formation- Different φBn presented
at interface- Process temperature
dependent composition
Diffusion species: Si atom (Ti)Surface roughness increases- Line dependent
resistivity change
Line widthof 0.1 µm
H. Iwai et al., Microelectron. Eng., 60, 157 (2002).
Top view
Epitaxial NiSi2
O. Nakatsuka et al., Microelectron. Eng.,83, 2272 (2006).
Si(001) sub.Annealing: 650 oC
133
Si substrate
Ni-silicide
Si substrate
Si substrate
Ni-silicide
Si substrate
Deposition of Ni film
Deposition fromNiSi2 source Annealing Flat interface
Roughinterface
No Si substrateconsumption
Annealing
Deposition of Ni-Si mixed films from NiSi2 source
- No consumption of Si atoms from substrate- No structural size effect in silicidation process- Stable in a wide process temperature range
134
SEM views of silicide/Si interfaces
NiSi2 source
Ni source (50nm)
rough
rough
rough flat
flat
flat
STI 500nm
NiSi2 source (50nm)
500nm
500nm
STI
500nmSTI STI
500nmSTI500nmSTI600oC , 1min
700oC , 1min
800oC , 1min
- Rough interfaces- Consumed Si substrate - Thickness increase ~100 nm
Ni source
- Atomically flat interfaces- No Si consumption- Temperature-independent
Si substrate
Ni-silicide
Ni source
Ni-silicide
Si substrate
NiSi2 source
STI
135
Ideal characteristics (n = 1.00, suppressed leakage current)
Suppressed reverse leakage current- Flat interface and No Si substrate consumption- No defects in Si substrate
Ni
NiSi2
-0.8 -0.6 0.0 0.2Diode voltage (V)
-0.4 -0.210-5
10-4
10-3
10-2
Dio
de c
urre
nt (A
/cm
2 )
1.001.08
n
0.659NiSi2
0.676NiφBn (eV)Source
1.001.08
n
0.659NiSi2
0.676NiφBn (eV)Source
Generation current
RTA:500oC, 1min
Schottky diode structures
Leakage currentAl contact
Ni source
Al contact
NiSi2 source
Si substrate
Si substrate
NiSi2 source Applied Voltage (V)
Cur
rent
den
sity
(A/c
m2 )
136
Ni silicide Ni
200nm
Si Fin
Fins width:20nm50nm
Si Fin Ni silicide
Growth length
SiO2
NWs width:20nm
SiO2 Ni silicide
Ni silicide
Si NW
50nm
200nmGrowthlength
(a) (b)
137
Conclusions
Si-MOSFET is the most fundamental and smallest functional device available for manufacturing.
It is really amazing to keep the evolution for so many generations without being replaced by any other device.
138
The device downsizing of Si-MOSFET will be ended within 10 ~ 20 years because Ioffincrease at the size of sub-5nm.
In order to reach the limit, R&D for nanowire, high-k for sub-5nm EOT, silicide S/D are necessary.
There are many rooms for the universities to contribute to the development.
139
Finally, even after the end of Si-MOSFET downsizing, Si-CMOS technology will still be the mainstream IC technology for a long period, as no other device technology seems to be developed into a comparable integration scale as the present CMOS technology in foreseeable future.
However, new device research other thanSi-CMOS is also very important.
140
1900 1970 2000 2020
ElectronicsMicro-Electronics
Nano-Electronics
Vacuum tube Si MOS IC Si CMOS IC
2100
Leap
Bio device (brain, even insect): 4 Billion Years from single cell. Difference of history
MOS IC: only 40 Years Bio device
Thank you for your attention!
141