january 2009 ddr-ii (burst of 4) cio synchronous srams · ddr-ii (burst of 4) cio synchronous srams...

Integrated Silicon Solution, Inc. — 1-800-379-4774 1Rev. D01/19/09

I36 Mb (1M x 36 & 2M x 18)DDR-II (Burst of 4) CIO Synchronous SRAMs

Features• 1M x 36 or 2M x 18.

• On-chip delay-locked loop (DLL) for wide data valid window.

• Common I/O read and write ports.

• Synchronous pipeline read with late write opera-tion.

• Double data rate (DDR-II) interface for read and write input ports.

• Fixed 4-bit burst for read and write operations.

• Clock stop support.

• Two input clocks (K and K) for address and con-trol registering at rising edges only.

• Two input clocks (C and C) for data output con-trol.

• Two echo clocks (CQ and CQ) that are delivered simultaneously with data.

• +1.8V core power supply and 1.5, 1.8V VDDQ, used with 0.75, 0.9V VREF.

• HSTL input and output levels.

• Registered addresses, write and read controls, byte writes, and data outputs.

• Full data coherency.

• Boundary scan using limited set of JTAG 1149.1 functions.

• Byte write capability.

• Fine ball grid array (FBGA) package- 15mm x 17mm body size - 1mm pitch- 165-ball (11 x 15) array

• Programmable impedance output drivers via 5x user-supplied precision resistor.

Description

The 36Mb IS61DDB41M36 and IS61DDB42M18are synchronous, high-performance CMOS staticrandom access memory (SRAM) devices. TheseSRAMs have a common I/O bus. The rising edge ofK clock initiates the read/write operation, and allinternal operations are self-timed. Refer to the Timing Reference Diagram for Truth Table on p.8for a description of the basic operations of theseDDR-II (Burst of 4) CIO SRAMs.

Read and write addresses are registered on alter-nating rising edges of the K clock. Reads and writes are performed in double data rate. The following are registered internally on the rising edge of the K clock:

• Read and write addresses• Address load • Read/write enable• Byte writes for burst addresses 1 and 3• Data-in for burst addresses 1 and 3

The following are registered on the rising edge of the K clock:

• Byte writes for burst addresses 2 and 4

• Data-in for burst addresses 2 and 4

Byte writes can change with the corresponding data-in to enable or disable writes on a per-byte basis. An internal write buffer enables the data-ins to be regis-tered one cycle later than the write address. The first data-in burst is clocked one cycle later than the write command signal, and the second burst is timed to the following rising edge of the K clock. Two full clock cycles are required to complete a write opera-tion.

During the burst read operation, at the first and third bursts the data-outs are updated from output regis-ters off the second and fourth rising edges of the C clock (starting 1.5 cycles later). At the second and fourth bursts, the data-outs are updated with the third and fifth rising edges of the corresponding C clock (see page 9). The K and K clocks are used to time the data-outs whenever the C and C clocks are tied high. Two full clock cycles are required to complete a read operation

The device is operated with a single +1.8V power supply and is compatible with HSTL I/O interfaces.

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JANUARY 2009

2 Integrated Silicon Solution, Inc. — 1-800-379-4774Rev. D

01/19/09

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®36 Mb (1M x 36 & 2M x 18)DDR-II (Burst of 4) CIO Synchronous SRAMs

x36 FBGA Pinout (Top View)

1 2 3 4 5 6 7 8 9 10 11

A CQ VSS/SA* SA R/W BW2 K BW1 LD SA VSS/SA* CQ

B NC DQ27 DQ18 SA BW3 K BW0 SA NC NC DQ8

C NC NC DQ28 VSS SA SA0 SA1 VSS NC DQ17 DQ7

D NC DQ29 DQ19 VSS VSS VSS VSS VSS NC NC DQ16

E NC NC DQ20 VDDQ VSS VSS VSS VDDQ NC DQ15 DQ6

F NC DQ30 DQ21 VDDQ VDD VSS VDD VDDQ NC NC DQ5

G NC DQ31 DQ22 VDDQ VDD VSS VDD VDDQ NC NC DQ14

H Doff VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ

J NC NC DQ32 VDDQ VDD VSS VDD VDDQ NC DQ13 DQ4

K NC NC DQ23 VDDQ VDD VSS VDD VDDQ NC DQ12 DQ3

L NC DQ33 DQ24 VDDQ VSS VSS VSS VDDQ NC NC DQ2

M NC NC DQ34 VSS VSS VSS VSS VSS NC DQ11 DQ1

N NC DQ35 DQ25 VSS SA SA SA VSS NC NC DQ10

P NC NC DQ26 SA SA C SA SA NC DQ9 DQ0

R TDO TCK SA SA SA C SA SA SA TMS TDI

• The following pins are reserved for higher densities: 2A for 144Mb, 10A for 72Mb.

• BW0 controls writes to DQ0–DQ8; BW1 controls writes to DQ9–DQ17; BW2 controls writes to DQ18–DQ26; BW3 controls writes to DQ27–DQ35.

x18 FBGA Pinout (Top View)

1 2 3 4 5 6 7 8 9 10 11

A CQ VSS/SA* SA R/W BW1 K NC/SA LD SA SA CQ

B NC DQ9 NC SA NC/SA K BW0 SA NC NC DQ8

C NC NC NC VSS SA SA0 SA1 VSS NC DQ7 NC

D NC NC DQ10 VSS VSS VSS VSS VSS NC NC NC

E NC NC DQ11 VDDQ VSS VSS VSS VDDQ NC NC DQ6

F NC DQ12 NC VDDQ VDD VSS VDD VDDQ NC NC DQ5

G NC NC DQ13 VDDQ VDD VSS VDD VDDQ NC NC NC

H Doff VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ

J NC NC NC VDDQ VDD VSS VDD VDDQ NC DQ4 NC

K NC NC DQ14 VDDQ VDD VSS VDD VDDQ NC NC DQ3

L NC DQ15 NC VDDQ VSS VSS VSS VDDQ NC NC DQ2

M NC NC NC VSS VSS VSS VSS VSS NC DQ1 NC

N NC NC DQ16 VSS SA SA SA VSS NC NC NC

P NC NC DQ17 SA SA C SA SA NC NC DQ0

R TDO TCK SA SA SA C SA SA SA TMS TDI

• The following pin is reserved for higher densities: 2A for 72Mb, 7A for 144Mb, 5B for 288Mb.

• BW0 controls writes to DQ0–DQ8; BW1 controls writes to DQ9–DQ17


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Pin Description

Symbol Pin Number Description

K, K 6B, 6A Input clock.

C, C 6P, 6R Input clock for output data control.

CQ, CQ 11A, 1A Output echo clock.

Doff 1H DLL disable when low.

SA0, SA1 6C, 7C Burst count address inputs.

SA 9A, 4B, 8B, 5C, 5N, 6N, 7N, 4P, 5P, 7P, 8P, 3R, 4R, 5R, 7R, 8R, 9R 1M x 36 address inputs.

SA 3A, 9A, 4B, 8B, 5C, 5N, 6N, 7N, 4P, 5P, 7P, 8P, 3R, 4R, 5R, 7R, 8R, 9R 2M x 18 address inputs.

DQ0–DQ8DQ9–DQ17DQ18–DQ26DQ27–DQ35

11P, 11M, 11L, 11K, 11J, 11F, 11E, 11C, 11B10P, 11N, 10M, 10K, 10J, 11G, 10E, 11D, 10C3B, 3D, 3E, 3F, 3G, 3K, 3L, 3N, 3P2B, 3C, 2D, 2F, 2G, 3J, 2L, 3M, 2N

1M x 36 DQ pins

DQ0–DQ8DQ9–DQ17

11P, 10M, 11L, 11K, 10J, 11F, 11E, 10C, 11B2B, 3D, 3E, 2F, 3G, 3K, 2L, 3N, 3P

2M x 18 DQ pins

R/W 4A Read/write control. Read when active high.

LD 8A Synchronizes load. Loads new address when low.

BW0, BW1, BW2, BW3 7B, 7A, 5A,5B 1M x 36 byte write control, active low.

BW0, BW1 7B, 5A 2M x 18 byte write control, active low.

VREF 2H, 10H Input reference level.

VDD 5F, 7F, 5G, 7G, 5H, 7H, 5J, 7J, 5K, 7K Power supply.

VDDQ 4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L Output power supply.

VSS2A, 10A, 4C, 8C, 4D, 5D, 6D, 7D, 8D, 5E, 6E, 7E, 6F, 6G, 6H, 6J, 6K, 5L, 6L, 7L, 4M, 8M, 4N, 8N Power supply.

ZQ 11H Output driver impedance control.

TMS, TDI, TCK 10R, 11R, 2R IEEE 1149.1 test inputs (1.8V LVTTL lev-els).

TDO 1R IEEE 1149.1 test output (1.8V LVTTL level).


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SRAM Features

Read Operations

The SRAM operates continuously in a burst-of-four mode. Read cycles are started by registering R/W in active high state at the rising edge of the K clock. R/W can be activated every other cycle because two full cycles are required to complete the burst-of-four read in DDR mode. A second set of clocks, C and C, are used to control the timing to the outputs. A set of free-running echo clocks, CQ and CQ, are produced inter-nally with timings identical to the data-outs. The echo clocks can be used as data capture clocks by the receiver device.

When the C and C clocks are connected high, the K and K clocks assume the function of those clocks. In this case, the data corresponding to the first address is clocked 1.5 cycles later by the rising edge of the K clock. The data corresponding to the second burst is clocked 2 cycles later by the following rising edge of the K clock. The third data-out is clocked by the subsequent rising edge of the K clock, and the fourth data-out is clocked by the subsequent rising edge of the K clock.

Whenever LD is low, a new address is registered at the rising edge of the K clock. A NOP operation (LD is high) does not terminate the previous read. The output drivers disable automatically to a high state.

Write Operations

Write operations can also be initiated at every other rising edge of the K clock whenever R/W is low. The write address is also registered at that time. When the address needs to change, LD needs to be low simulta-neously to be registered by the rising edge of K. Again, the write always occurs in bursts of four.

Block Diagram

1M x 36(2M x 18)Memory

Array

Writ

e/R

ead

Dec

ode

Sen

se A

mps

Write Driver

Select Output Control

DataReg

Add Reg &

ControlLogic

ClockGen

Out

put R

eg

Out

put S

elec

t

Out

put D

river72

(or 36)72

(or 36)

36 (or 18)

DQ (Data-Out

CQ, CQ

(Echo Clock Out)

Address

LD

R/W

BWx

K

K

C

C

4 (or 2)

18 (or 19) 18 (or 19)

36 (or 18)

& Data-In)

A0, A1Burst

Control

36 (or 18)


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The write data is provided in a ‘late write’ mode; that is, the data-in corresponding to the first address of the burst, is presented 1 cycle later or at the rising edge of the following K clock. The data-in corresponding to the second write burst address follows next, registered by the rising edge of K. The third data-out is clocked by the subsequent rising edge of the K clock, and the fourth data-out is clocked by the subsequent rising edge of the K clock.

The data-in provided for writing is initially kept in write buffers. The information on these buffers is written into the array on the third write cycle. A read cycle to the last two write address produces data from the write buffers. The SRAM maintains data coherency.

During a write, the byte writes independently control which byte of any of the four burst addresses is written (see X18/X36 Write Truth Tables on page 9 and Timing Reference Diagram for Truth Table on page 8).

Whenever a write is disabled (R/W is high at the rising edge of K), data is not written into the memory.

RQ Programmable Impedance

An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to enable the SRAM to adjust its output driver impedance. The value of RQ must be 5x the value of the intended line impedance driven by the SRAM. For example, an RQ of 250Ω results in a driver impedance of 50Ω. The allowable range of RQ to guarantee impedance matching is between 175Ω and 350Ω, with the tolerance described in Programmable Impedance Output Driver DC Electrical Characteristics on page 15. The RQ resistor should be placed less than two inches away from the ZQ ball on the SRAM module. The capacitance of the loaded ZQ trace must be less than 3 pF.

The ZQ pin can also be directly connected to VDDQ to obtain a minimum impedance setting. ZQ must never be connected to VSS.

Programmable Impedance and Power-Up Requirements

Periodic readjustment of the output driver impedance is necessary as the impedance is greatly affected by drifts in supply voltage and temperature. At power-up, the driver impedance is in the middle of allowable impedances values. The final impedance value is achieved within 1024 clock cycles.

Clock Consideration

This device uses an internal DLL for maximum output data valid window. It can be placed in a stopped-clock mode to minimize power and requires only 1024 cycles to restart.

No clocks can be issued until VDD reaches its allowable operating range.

Single Clock Mode

This device can be also operated in single-clock mode. In this case, C and C are both connected high at power-up and must never change. Under this condition, K and K control the output timings.

Either clock pair must have both polarities switching and must never connect to VREF, as they are not differ-ential clocks.


01/19/09

36 Mb (1M x 36 & 2M x 18)DDR-II (Burst of 4) CIO Synchronous SRAMs

Depth Expansion

The following figure depicts an implementation of four 2M x 18 DDR-II SRAMs with common I/Os. In this appli-cation example, the second pair of C and C clocks is delayed such that the return data meets the data setup and hold times at the bus master.

Application Example

2M x 18

SA LD R/W BW0 BW1 C C K K

DQ0–17

ZQ

SRAM #4R=250Ω

Vt

Data-In/Data-Out

Address 0–79

LD

R/W

BW0–7

MemoryController

Return CLK

Source CLK

Return CLK

Source CLK

SA LD R/W BW0 BW1 C C K K

DQ0–17

ZQ

SRAM #1R=250Ω

Vt

R

Vt

Vt

R=50Ω Vt=VREF

R

0–71

Power-Up and Power-Down Sequences

The following sequence is used for power-up:

1. The power supply inputs must be applied in the following order while keeping Doff in LOW logic state:

1) VDD 2) VDDQ 3) VREF

2. Start applying stable clock inputs (K, K, C, and C).3. After clock signals have stabilized, change Doff to HIGH logic state. 4. Once the Doff is switched to HIGH logic state, wait an additional 1024 clock cycles to lock the DLL.

NOTES:1. The power-down sequence must be done in reverse of the power-up sequence. 2. VDDQ can be allowed to exceed VDD by no more than 0.6V. 3. VREF can be applied concurrently with VDDQ.


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The Timing Reference Diagram for Truth Table on page 8 is helpful in understanding the clock and write truth tables, as it shows the cycle relationship between clocks, address, data-in, data-out, and controls. All read and write commands are issued at the beginning of cycles t and tw, respectively.

State Diagram

Linear Burst Sequence Table

Burst SequenceCase 1 Case 2 Case 3 Case 4

SA1 SA0 SA1 SA0 SA1 SA0 SA1 SA0

First Address 0 0 0 1 1 0 1 1

Second Address 0 1 1 0 1 1 0 0

Third Address 1 0 1 1 0 0 0 1

Fourth Address 1 1 0 0 0 1 1 0

Power Up

DDR-II Write

NOP

DDR-II Read

Write

Write

Notes: 1. Internal burst counter is fixed as four-bit linear; that is, when first address is A0+0, next internal burst address is A0+1.

2. Read refers to read active status with R/W = high.

4. Load refers to read new address active status with LD = low.

3. Write refers to write active status with R/W = low.

Load New Address

Load

Load

Read LoadLoad

Load

5. Load is read new address inactive status with LD = high.

IncrementIncrement

AlwaysAlwaysWriteRead

Read Address Write Address

Dcount = 1Dcount = 1

Dcount = 0Dcount = 2Load

Dcount = 2

Dcount = Dcount + 1 Dcount = Dcount + 1


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Timing Reference Diagram for Truth Table

Clock Truth Table (Use the following table with the Timing Reference Diagram for Truth Table.)

ModeClock Controls Data Out / Data In

K LD

t t+1 t+2 tW

A

QA QA+1

K Clock

K Clock

LD

Clock

Cycle tW+1

DB DB+1

NOPRead A

B

Write B

tW+2

DB+2 DB+3

Clock

LD

R / W

BW 0,1,2,3

Address

Data-In/Out (DQ)

C Clock

C

t t+1 t+2 tW

A

QA QA+1

K Clock

K

BW 0,1,2,3

Address

Data-In/Out (DQ)

C Clock

C

B

Write B

t t+1 t+2 tW

A

QA QA+1

K Clock

K

0,1,2,3

Address

Data-In/Out (DQ)

C Clock

C

tW+1

DB DB+1

NOPRead A

tW+2

DB+2 DB+3QA+2 QA+3

0,1,2,3

Address

Data-In/Out (DQ)

C Clock

C Clock

CQ Clock

CQ Clock

Cycle

Timing Reference Diagram for Truth Table

Clock Truth Table (Use the following table with the Timing Reference Diagram for Truth Table.)

ModeClock Controls Data Out / Data In

K LD R/W QA / DB QA+1 / DB+1 QA+2 / DB+2 QA+3 / DB+3

Stop Clock Stop X X Previous State Previous State Previous State Previous State

No Operation (NOP) L→ H H H High-Z High-Z High-Z High-Z

Read B L→ H L HDout at C (t +

1.5)Dout at C

(t + 2)Dout at C (t + 2.5)

Dout at C(t + 3)

Write A L→ H L LDB

(tW + 1)DB

(tW + 1.5)DB

(tW + 2)DB

(tW + 2.5)

Notes:1. The internal burst counter is always fixed as two-bit.

2. X = don’t care; H = logic “1”; L = logic “0”.

3. A read operation is started when control signal R/W is active high.

4. A write operation is started when control signal R/W is active low. 5. Before entering into the stop clock, all pending read and write commands must be completed.

6. For timing definitions, refer to the AC Characteristics on page 16. Signals must have AC specifications at timings indicated in parenthesis with respect to switching clocks K, K, C, and C.


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X36 Write Truth Table Use the following table with the Timing Reference Diagram for Truth Table on page 8.

OperationK

(tW+1)K

(tW+1.5)K

(tW+2)K

(tW+2.5)BW0 BW1 BW2 BW3 DB DB+1 DB+2 DB+3

Write Byte 0 L→ H L H H H D0-8 (tW+1)

Write Byte 1 L→ H H L H H D9-17 (tW+1)

Write Byte 2 L→ H H H L H D18-26 (tW+1)

Write Byte 3 L→ H H H H L D27-35 (tW+1)

Write All Bytes L→ H L L L L D0-35 (tW+1)

Abort Write L→ H H H H H Don’t care

Write Byte 0 L → H L H H H D0-8 (tW+1.5)

Write Byte 1 L→ H H L H H D9-17 (tW+1.5)

Write Byte 2 L→ H H H L H D18-26 (tW+1.5)

Write Byte 3 L→ H H H H L D27-35 (tW+1.5)

Write All Bytes L→ H L L L L D0-35 (tW+1.5)


Write Byte 0 L→ H L H H H D0-8 (tW+2)

Write Byte 1 L→ H H L H H D9-17 (tW+2)

Write Byte 2 L→ H H H L H D18-26 (tW+2)

Write Byte 3 L→ H H H H L D27-35 (tW+2)

Write All Bytes L→ H L L L L D0-35 (tW+2)


Write Byte 0 L→ H L H H H D0-8 (tW+2.5)

Write Byte 1 L→ H H L H H D9-17 (tW+2.5)

Write Byte 2 L→ H H H L H D18-26 (tW+2.5)

Write Byte 3 L→ H H H H L D27-35 (tW+2.5)

Write All Bytes L→ H L L L L D0-35 (tW+2.5)


Notes;1. For all cases, R/W needs to be active low during the rising edge of K occurring at time tW2. For timing definitions refer to the AC Characteristics on page 16. Signals must have AC specifications with respect to switching

clocks K and K.


01/19/09

I ®36 Mb (1M x 36 & 2M x 18)DDR-II (Burst of 4) CIO Synchronous SRAMs

X18 Write Truth Table Use the following table with the Timing Reference Diagram for Truth Table on page 8.

OperationK

(tW+1)K

(tW+1.5)K

(tW+2)K

(tW+2.5)BW0 BW1 DB DB+1 DB+2 DB+3

Write Byte 0 L→ H L H D0-8 (tW+1)

Write Byte 1 L→ H H L D9-17 (tW+1)

Abort Write L→ H H H Don’t care

Write Byte 0 L→ H L H D0-8 (tW+1.5)

Write Byte 1 L→ H H L D9-17 (tW+1.5)

Write All Bytes L→ H L L D0-17 (tW+1.5)


Write Byte 0 L→ H L H D0-8 (tW+2)

Write Byte 1 L→ H H L D9-17 (tW+2)

Write All Bytes L→ H L L D0-17 (tW+2)


Write Byte 0 L→ H L H D0-8 (tW+2.5)

Write Byte 1 L→ H H L D9-17 (tW+2.5)

Write All Bytes L→ H L L D0-17 (tW+2.5)


Notes;1. For all cases, R/W needs to be active low during the rising edge of K occurring at time tW2. For timing definitions refer to the AC Characteristics on page 16. Signals must have AC specifications with respect to switching

clocks K and K.


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Absolute Maximum Ratings

Item Symbol Rating Units

Power supply voltage VDD -0.5 to 2.6 V

Output power supply voltage VDDQ -0.5 to 2.6 V

Input voltage VIN -0.5 to 2.6 V

Data out voltage VDOUT -0.5 to 2.6 V

Operating temperature TA 0 to 70 ° C

Junction temperature TJ 110 ° C

Storage temperature TSTG -55 to +125 ° C

Note: Stresses greater than those listed in this table can cause permanent damage to the device. This is a stress rating only and func-tional operation of the device at these or any other conditions above those indicated in the operational sections of this datasheet is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.


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Recommended DC Operating Conditions (TA = 0 to +70° C)

Parameter Symbol Minimum Typical Maximum Units Notes

Supply voltage VDD 1.8 - 5% 1.8 + 5% V 1

Output driver supply voltage VDDQ 1.4 1.9 V 1

Input high voltage VIH VREF +0.1 VDDQ + 0.2 V 1, 2

Input low voltage VIL -0.2 VREF - 0.1 V 1, 3

Input reference voltage VREF 0.68 0.95 V 1, 5

Clocks signal voltage VIN - CLK -0.2 VDDQ + 0.2 V 1, 4

1. All voltages are referenced to VSS. All VDD, VDDQ, and VSS pins must be connected.2. VIH(Max) AC = See 0vershoot and Undershoot Timings.3. VIL(Min) AC = See 0vershoot and Undershoot Timings.4. VIN-CLK specifies the maximum allowable DC excursions of each clock (K, K, C, and C).5. Peak-to-peak AC component superimposed on VREF may not exceed 5% of VREF.

0vershoot and Undershoot Timings

PBGA Thermal Characteristics

Item Symbol Rating Units

Thermal resistance junction to ambient (airflow = 1m/s) RΘJA TBD ° C/W

Thermal resistance junction to case RΘJC TBD ° C/W

Thermal resistance junction to pins RΘJB TBD ° C/W

VDDQ

20% Min Cycle Time

VDDQ+0.6V

GND-0.6V

GND

20% Min Cycle TimeOvershoot Timing

Undershoot Timing

VIH(Max) AC

VIL(Min) AC

Integrated Silicon Solution, Inc. — 1-800-379-4774 13Rev. D

01/19/09

ISSI


Capacitance (TA = 0 to + 70oC, VDD = 1.8V -5%, +5%, f = 1MHz)

Parameter Symbol Test Condition Maximum Units

Input capacitance CIN VIN = 0V 4 pF

Data-in/Out capacitance (DQ0–DQ35) C

C

DQ VDIN = 0V 4 pF

Clocks Capacitance (K, K, C, C) CLK VCLK = 0V 4 pF

DC Electrical Characteristics (TA = 0 to + 70oC, VDD = 1.8V -5%, +5%)

Parameter Symbol Minimum Maximum Units Notes

x36 average power supply operating current(IOUT = 0, VIN = VIH or VIL)

IDD30

IDD40

IDD50

IDD30

IDD40

IDD50

———

mA 1

x18 average power supply operating current(IOUT = 0, VIN = VIH or VIL)

———

mA 1

Power supply standby current(R = VIH, W = VIH. All other inputs = VIH or VIH, IIH = 0) ISBSS — 200 mA 1

Input leakage current, any input (except JTAG)(VIN = VSS or VDD) ILI -2 +2

Output leakage current(VOUT = VSS or VDDQ, Q in High-Z) ILO -5 +5 uA

uA

uA

Output “high” level voltage (IOH = -6mA) VOH VDDQ VDDQ

Output “low” level voltage (IOL = +6mA) VOL VSS VSS V

V

JTAG leakage current(VIN = VSS or VDD) ILIJTAG

1. IOUT = chip output current.2. Minimum impedance output driver.3. JEDEC Standard JESD8-6 Class 1 compatible.4. For JTAG inputs only.5. Currents are estimates only and need to be verified.

600550500

600550500

2, 3

2, 3

4

-0.4

+0.4

-100 +100


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Typical AC Input Characteristics

Item Symbol Minimum Maximum Notes

AC input logic high VIH (ac) VREF + 0.4 1, 2, 3, 4

AC input logic low VIL (ac) VREF - 0.4 1, 2, 3, 4

Clock input logic high (K, K, C, C) VIH-CLK (ac) VREF + 0.4 1, 2, 3

Clock input logic low (K, K, C, C) VIL-CLK (ac) VREF - 0.4 1, 2, 3

1. The peak-to-peak AC component superimposed on VREF may not exceed 5% of the DC component of VREF.2. Performance is a function of VIH and VIL levels to clock inputs.3. See the AC Input Definition diagram.4. See the AC Input Definition diagram. The signals should swing monotonically with no steps rail-to-rail with input signals never ring-

ing back past VIH (AC) and VIL (AC) during the input setup and input hold window. VIH (AC) and VIL (AC) are used for timing pur-poses only.

AC Input Definition

Programmable Impedance Output Driver DC Electrical Characteristics (TA = 0 to +70° C, VDD = 1.8V -5%, +5%, VDDQ = 1.5, 1.8V)


Output “high” level voltage VOH VDDQ / 2 VDDQ V 1, 3

Output “low” level voltage VOL VSS VDDQ / 2 V 2, 3

1. IOH = ± 15% @ VOH = VDDQ / 2 For: 175Ω ≤ RQ ≤ 350Ω.

2. IOL = ± 15% @ VOL = VDDQ / 2 For: 175Ω ≤ RQ ≤ 350Ω.

3. Parameter tested with RQ = 250Ω and VDDQ = 1.5V.

VIH (AC)

VREF

VIL (AC)

SetupTime

HoldTime

VREF

K

K

VRAIL

V-RAIL

VDDQ2

------------------ RQ

5--------

⁄

VDDQ2

------------------ RQ

5--------

⁄


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AC Test Conditions (TA = 0 to +70° C, VDD = 1.8V -5%, +5%, VDDQ = 1.5, 1.8V)

Parameter Symbol Conditions Units Notes

Output driver supply voltage VDDQ 1.5, 1.8 V

Input high level VIH VREF+0.5 V

Input Low Level VIL VREF-0.5 V

Input reference voltage VREF 0.75, 0.9 V

Input rise time TR 0.35 ns

Input fall time TF 0.35 ns

Output timing reference level VREF V

Clocks reference level VREF V

Output load conditions 1, 2

1. See AC Test Loading.2. Parameter tested with RQ = 250Ω and VDDQ = 1.5V.

AC Test Loading

Q50 Ω

50 Ω

5pF

0.75, 0.9V

0.75, 0.9V

Test Comparator


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ISSI


AC Characteristics (TA = 0 to + 70oC, VDD = 1.8V -5%, +5%)

Parameter Symbol

30(333MHz) Units Notes

Min Max

Clock

Cycle time (K, K, C, C) tKHKH 3.0 3.6 ns

Clock phase jitter (K, K, C, C) tKC-VAR 0.12 ns

Clock high pulse (K, K, C, C) tKHKL 1.2 ns

Clock low pulse (K, K, C, C) tKLKH 1.2 ns

Clock to clock (KH>KH, CH>CH) tKHKH 1.3 ns

Clock to data clock (KH>CH, KH>CH) tKHCH 0.0 1.3 ns

DLL lock (K, C) tKC-lock 1024 cycle

K static to DLL reset tKC-reset 30 cycle

Output Times

C, C high to output valid tCHQV 0.27 ns 1, 3

C, C high to output hold tCHQX -0.27 ns 1, 3

C, C high to echo clock valid tCHCQV 0.25 ns 3

C, C high to echo clock hold tCHCQX -0.25 ns 3

CQ, CQ high to output valid tCQHQV 0.27 ns 1, 3

CQ, CQ high to output hold tCQHQX -0.27 ns 1, 3

C high to output high-Z tCHQZ 0.27 ns 1, 3

C high to output low-Z tCHQX1 -0.27 ns 1, 3

Setup Times

Address valid to K, K rising edge tAVKH 0.33 — ns 2

Control inputs valid to K rising edge tIVKH 0.33 — ns 2

Data-in valid to K, K rising edge tDVKH 0.30 — ns 2

Hold Times

K rising edge to address hold tKHAX 0.33 — ns 2

K rising edge to control inputs hold tKHIX 0.33 — ns 2

K, K rising edge to data-in hold tKHDX 0.30 — ns 2

1. See AC Test Loading on page 15.

2. During normal operation, VIH, VIL, TRISE, and TFALL of inputs must be within 20% of VIH, VIL, TRISE, and TFALL of clock.

3. If C, C are tied high, then K, K become the references for C, C timing parameters.


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AC Characteristics (TA = 0 to + 70oC, VDD = 1.8V -5%, +5%)

Parameter Symbol

40(250MHz)

50(200MHz) Units Notes

Min Max Min Max

Clock

Cycle time (K, K, C, C) tKHKH 4.0 5.85 5.0 6.3 ns

Clock phase jitter (K, K, C, C) tKC-VAR 0.2 0.2 ns

Clock high pulse (K, K, C, C) tKHKL 1.6 2.0 ns

Clock low pulse (K, K, C, C) tKLKH 1.6 2.0 ns

Clock to clock (KH>KH, CH>CH) tKHKH 1.8 2.2 ns

Clock to data clock (KH>CH, KH>CH) tKHCH 0.0 1.8 0.0 2.3 ns

DLL lock (K, C) tKC-lock 1024 1024 cycle

K static to DLL reset tKC-reset 30 30 cycle

Output Times

C, C high to output valid tCHQV 0.35 0.38 ns 1, 3

C, C high to output hold tCHQX -0.35 -0.38 ns 1, 3

C, C high to echo clock valid tCHCQV 0.33 0.36 ns 3

C, C high to echo clock hold tCHCQX -0.33 -0.36 ns 3

CQ, CQ High to output valid tCQHQV 0.35 0.36 ns 1, 3

CQ, CQ high to output hold tCQHQX -0.35 -0.36 ns 1, 3

C High to output high-Z tCHQZ 0.35 0.38 ns 1, 3

C High to output low-Z tCHQX1 -0.35 -0.38 ns 1, 3

Setup Times

Address valid to K, K rising edge tAVKH 0.4 — 0.5 — ns 2

Control inputs valid to K rising edge tIVKH 0.4 — 0.5 — ns 2

Data-in valid to K, K rising edge tDVKH 0.35 — 0.4 — ns 2

Hold Times

K rising edge to address hold tKHAX 0.4 — 0.5 — ns 2

K rising edge to Control Inputs Hold tKHIX 0.4 — 0.5 — ns 2

K, K rising edge to data-in hold tKHDX 0.35 — 0.4 — ns 2


2. During normal operation, VIH, VIL, TRISE, and TFALL of inputs must be within 20% of VIH, VIL, TRISE, and TFALL of clock.

3. If C, C are tied high, then K, K become the references for C, C timing parameters.


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Read, Write, and NOP Timing Diagram

tKLKHtKHKLtKHKH

tCHQZ

tCHQXtCHQX

tCHQV

tKHCH

tKHDXtDVKH

tKHAXtAVKH

tKHIXtIVKH

tKHKHtKLKH

tKHKHtKHKL

NOP Read(burst of 4)

1 2 3 4 5 6 7 8 9 10 11 12

NOPRead(burst of 4)

A0 A1 A2 A3

NOP(Note 3)

Read(burst of 4)

Write(burst of 4)

Q01 Q03 Q11 Q13 Q14Q12Q04Q02 D21 D24D23D22 Q31 Q33Q32

K

K

tKLKHtKHKLtKHKH

tCHQZ

tCHQXtCHQX

tCHQV

tKHCH

tKHDXtDVKH

tKHAXtAVKH

tKHIXtIVKH

tKHKHtKLKH

tKHKHtKHKL


1 2 3 4 5 6 7 8 9 10 11 12

NOPRead(burst of 4)

A0 A1 A2 A3

NOP(Note 3)

Read(burst of 4)

Write(burst of 4)


K

K

tKLKHtKHKLtKHKH

tCHQZ

tCHQXtCHQX

tCHQV

tKHCH

tKHDXtDVKH

tKHAXtAVKH

tKHIXtIVKH

tKHKHtKLKH

tKHKHtKHKL


1 2 3 4 5 6 7 8 9 10 11 12

NOPRead(burst of 4)

A0 A1 A2 A3

NOP(Note 3)

Read(burst of 4)

Write(burst of 4)


K

K

LD

tKLKHtKHKLtKHKH

tCHQZ

tCHQXtCHQX

tCHQV

tKHCH

tKHDXtDVKH

tKHAXtAVKH

tKHIXtIVKH

tKHKH

LD

R/W

tKLKHtKHKLtKHKH

tCHQZ

tCHQXtCHQX

tCHQV

tKHCH

tKHDXtDVKH

tKHAXtAVKH

tKHIXtIVKH

tKHKHtKLKH

tKHKHtKHKL


1 2 3 4 5 6 7 8 9 10 11 12

NOPRead(burst of 4)

A0 A1 A2 A3

NOP(Note 3)

Read(burst of 4)

Write(burst of 4)


K

K

R/W

SA

DQ

C

C

tKLKHtKHKLtKHKH

tCHQZ

tCHQXtCHQX

tCHQV

tKHCH

tKHDXtDVKH

tKHAXtAVKH

tKHIXtIVKH

tKHKHtKLKH

tKHKHtKHKL


1 2 3 4 5 6 7 8 9 10 11 12

NOPRead(burst of 4)

A0 A1 A2 A3

NOP(Note 3)

Read(burst of 4)

Write(burst of 4)


K

K

SA

DQ

C

C

tCHQV

tKLKHtKHKLtKHKH

tCHQZ

tCHQXtCHQX

tCHQV

tKHCH

tKHDXtDVKH

tKHAXtAVKH

tKHIXtIVKH

tKHKH

SA

DQ

C

C

tCHQV

tCQHQZtCQHQX

tCQHQV

tCHCQHtKHKH

tKLKHtKHKLtKHKH

tCHQZ

tCHQXtCHQX

tCHQV

tKHCH

tKHDXtDVKH

tKHAXtAVKH

tKHIXtIVKH

tKHKH

SA

DQ

C

C

tCQHQZtCQHQX

tCQHQV

tCHCQHtKHKH

tKLKHtKHKLtKHKH

tCHQZ

tCHQXtCHQX

tCHQV

tKHCH

tKHDXtDVKH

tKHAXtAVKH

tKHIXtIVKH

tKHKH

CQ

CQ

tCQHQZtCQHQX

tCQHQV

tCHCQHtKHKH

CQ

CQ

Don’t Care Undefined

Notes:1. Q01 refers to the output from address A. Q02 refers to the output from the next internal burst address following A.2. Outputs are disabled (high impedance) one clock cycle after a NOP.3. The second NOP cycle is not necessary for correct device operation, however, at high clock frequencies, it might be required to prevent bus contention.


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IEEE 1149.1 TAP and Boundary Scan

The SRAM provides a limited set of JTAG functions to test the interconnection between SRAM I/Os and printed circuit board traces or other components. There is no multiplexer in the path from I/O pins to the RAM core.

In conformance with IEEE Standard 1149.1, the SRAM contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register.

The TAP controller has a standard 16-state machine that resets internally on power-up. Therefore, a TRST signal is not required.

Signal List

• TCK: test clock• TMS: test mode select• TDI: test data-in• TDO: test data-out

JTAG DC Operating Characteristics (TA = 0 to +70° C)Operates with JEDEC Standard 8-5 (1.8V) logic signal levels

Parameter Symbol Minimum Typical Maximum Units Notes

JTAG input high voltage VIH1 1.3 — VDD+0.3 V 1

JTAG input low voltage VIL1 -0.3 — 0.5 V 1

JTAG output high level VOH1 VDD-0.4 — VDD V 1, 2

JTAG output low level VOL1 VSS — 0.4 V 1, 3

1. All JTAG inputs and outputs are LVTTL-compatible.2. IOH1 ≥ -|2mA|3. IOL1 ≥ +|2mA|.

JTAG AC Test Conditions (TA = 0 to +70° C, VDD = 1.8V -5%, +5%)

Parameter Symbol Conditions Units

Input pulse high level VIH1 1.3 V

Input pulse low level VIL1 0.5 V

Input rise time TR1 1.0 ns

Input fall time TF1 1.0 ns

Input and output timing reference level 0.9 V


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JTAG AC Characteristics (TA = 0 to +70° C, VDD = 1.8V -5%, +5%)


TCK cycle time tTHTH 20 — ns

TCK high pulse width tTHTL 7 — ns

TCk low pulse width tTLTH 7 — ns

TMS setup tMVTH 4 — ns

TMS hold tTHMX 4 — ns

TDI setup tDVTH 4 — ns

TDI hold tTHDX 4 — ns

TCK low to valid data tTLOV — 7 ns 1


JTAG Timing Diagram

TCK

TMS

TDI

TDO

tTHTL tTLTH tTHTH

tTHMX

tTHDX

tTLOV

tMVTH

tDVTH


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Scan Register Definition

Register Name Bit Size x18 or x36

Instruction 3

Bypass 1

ID 32

Boundary Scan 109

ID Register Definition

Part

Field Bit Number and Description

Revision Number(31:29)

Part Configuration (28:12)

JEDEC Code (11:1)

Start Bit (0)

2M x 18 000 00def0wx0t0q0b0s0 000 101 001 00 1

1M x 36 000 00def0wx0t0q0b0s0 000 101 001 00 1

Part Configuration Definition:def = 010 for 36Mbwx = 11 for x36, 10 for x18t = 1 for DLL, 0 for non-DLLq = 1 for QUADB4, 0 for DDR-IIb = 1 for burst of 4, 0 for burst of 2s = 1 for separate I/0, 0 for common I/O


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List of IEEE 1149.1 Standard Violations

• 7.2.1.b, e• 7.7.1.a-f• 10.1.1.b, e• 10.7.1.a-d• 6.1.1.d

Instruction Set

Code Instruction TDO Output Notes

000 EXTEST Boundary Scan Register 2,6

001 IDCODE 32-bit Identification Register

010 SAMPLE-Z Boundary Scan Register 1, 2

011 PRIVATE Do not use 5

100 SAMPLE Boundary Scan Register 4



111 BYPASS Bypass Register 3

1. Places Qs in high-Z in order to sample all input data, regardless of other SRAM inputs.2. TDI is sampled as an input to the first ID register to allow for the serial shift of the external TDI data.3. BYPASS register is initiated to VSS when BYPASS instruction is invoked. The BYPASS register also holds the last serially loaded

TDI when exiting the shift-DR state.4. SAMPLE instruction does not place DQs in high-Z.5. This instruction is reserved. Invoking this instruction will cause improper SRAM functionality.6. This EXTEST is not IEEE 1149.1-compliant. By default, it places Q in high-Z. If the internal register on the scan chain is set high,

Q will be updated with information loaded via a previous SAMPLE instruction. The actual transfer occurs during the update IR state after EXTEST is loaded. The value of the internal register can be changed during SAMPLE and EXTEST only.

JTAG Block Diagram

Bypass Register (1 bit)

Identification Register (32 bits)

Instruction Register (3 bits)

TAP Controller

Control Signals

TDI

TMS

TCK

TDO


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TAP Controller State Machine

Test Logic Reset

Run Test Idle Select DR

Capture DR

Shift DR

Exit1 DR

Pause DR

Exit2 DR

Update DR

Select IR

Capture IR

Shift IR

Exit1 IR

Pause IR

Exit2 IR

Update IR

11

1

00

0

0

1

0

1

1

0

1

1

1

0

01

1

1

0

1

0

0

0

1

1

0

00

0

1


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Boundary Scan Exit Order The same length is used for x18 and x36 I/O configuration.

Order Pin ID Order Pin ID Order Pin ID

1 6R 37 10D 73 2C

2 6P 37 9E 74 3E

3 6N 39 10C 75 2D

4 7P 40 11D 76 2E

5 7N 41 9C 77 1E

6 7R 42 9D 78 2F

7 8R 43 11B 79 3F

8 8P 44 11C 80 1G

9 9R 45 9B 81 1F

10 11P 46 10B 82 3G

11 10P 47 11A 83 2G

12 10N 48 10A 84 1H

13 9P 49 9A 85 1J

14 10M 50 8B 86 2J

15 11N 51 7C 87 3K

16 9M 52 6C 88 3J

17 9N 53 8A 89 2K

18 11L 54 7A 90 1K

19 11M 55 7B 91 2L

20 9L 56 6B 92 3L

21 10L 57 6A 93 1M

22 11K 58 5B 94 1L

23 10K 59 5A 95 3N

24 9J 60 4A 96 3M

25 9K 61 5C 97 1N

26 10J 62 4B 98 2M

27 11J 63 3A 99 3P

28 11H 64 2A 100 2N

29 10G 65 1A 101 2P

30 9G 66 2B 102 1P

31 11F 67 3B 103 3R

32 11G 68 1C 104 4R

33 9F 69 1B 105 4P

34 10F 70 3D 106 5P

35 11E 71 3C 107 5N

36 10E 72 1D 108 5R

109 Internal

1) NC pins as defined on FBGA pinouts on page 2 are read as “don’t cares”. 2) State of Internal pin (#109) is loaded via JTAG.


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11 x 15 FBGA Dimensions


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ORDERING INFORMATION

Commercial Range: 0°C to +70°C

Speed Order Part No. Organization Package

250 MHz IS61DDB41M36-250M3 1Mx36 165 BGAIS61DDB42M18-250M3 2Mx18 165 BGAIS61DDB42M18-250M3L 2Mx18 165 BGA, Lead-free

january 2009 ddr-ii (burst of 4) cio synchronous srams · ddr-ii (burst of 4) cio synchronous srams...

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