jan 4-8, 2008 vlsi design conference 1 total power minimization in glitch-free cmos circuits...

Jan 4-8, 2008Jan 4-8, 2008 VLSI Design ConferenceVLSI Design Conference 11

Total Power Minimization in Glitch-Free Total Power Minimization in Glitch-Free CMOS Circuits Considering Process CMOS Circuits Considering Process

VariationVariation

Yuanlin LuYuanlin LuIntel Corporation, Folsom, CA 95630Intel Corporation, Folsom, CA 95630

Vishwani D. AgrawalVishwani D. AgrawalDepartment of ECE, Auburn University, Auburn, AL 36849Department of ECE, Auburn University, Auburn, AL 36849

22Jan 4-8, 2008Jan 4-8, 2008 VLSI Design ConferenceVLSI Design Conference

OutlineOutlineMotivationMotivationProblem StatementProblem StatementBackgroundBackgroundProposed TechniqueProposed Technique Statistical reduction of leakage and glitch Statistical reduction of leakage and glitch

power under process variationpower under process variation

ResultsResultsConclusionConclusion


MotivationMotivation

Leakage power has become a dominant contributor to Leakage power has become a dominant contributor to the total power consumption the total power consumption

65nm, leakage is ~ 50% of total power consumption65nm, leakage is ~ 50% of total power consumption

Glitches consume 20%-70% of dynamic powerGlitches consume 20%-70% of dynamic power

Variation of process parameters increases with Variation of process parameters increases with technology scalingtechnology scaling

both average and standard deviation of leakage power increaseboth average and standard deviation of leakage power increase Glitch elimination technique of path balancing becomes Glitch elimination technique of path balancing becomes

ineffective ineffective Power yield and timing yield are degradedPower yield and timing yield are degraded


One Example: Process Variation One Example: Process Variation Effect on Leakage and PerformanceEffect on Leakage and Performance

too slow

too leaky

[Ref] S. Borkar, et. al., DAC 2003.

0.18um CMOS process 20X leakage variation 30% frequency

variation high frequency but too

leaky chips must be discarded

low leakage chips with too low frequency must also be discarded


Nominal

0.00

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

0.45

0.50

Pro

bab

ilit

y

10% delay variation 20% delay variation

30% delay variation

0.000.050.10

0.150.200.250.300.35

0.400.450.50

Prob

abili

ty

10% Leff variation

20% Leff variation 30% Leff variation

Comparison of Dynamic and Leakage Power Variation of Un-Optimized C432 (1,000 Samples)

Normalized Leakage Power

Normalized Dynamic Power

LLeffeff

variationvariation

(mean-(mean-nominal)/ nominal)/ nominalnominal

STD / STD / meanmean

10%10% 3.10%3.10% 6.1%6.1%

20%20% 8.75%8.75% 30.7%30.7%

30%30% 25.17%25.17% 112.9%112.9%

DelayDelayvariationvariation

(mean-(mean-nominal)/ nominal)/ nominalnominal

STD / STD / meanmean

10%10% -0.05%-0.05% 0.65%0.65%

20%20% -0.07%-0.07% 1.12%1.12%

30%30% -0.16%-0.16% 1.50%1.50%


Process Variation and Dynamic PowerProcess Variation and Dynamic PowerDynamic power is normally much Dynamic power is normally much less sensitive to the process less sensitive to the process variation due to its approximately variation due to its approximately linear relation to process linear relation to process parameters. parameters.

Deterministic path balancing Deterministic path balancing becomes ineffective under becomes ineffective under process variation because the process variation because the perfect hazard filtering conditions perfect hazard filtering conditions can easily be corrupted with a can easily be corrupted with a very slight variation in process very slight variation in process parameters.parameters. 0.00

0.020.040.060.080.100.120.140.160.180.20

1.00

1.04

1.08

1.12

1.16

1.20

1.24

1.28

1.32

1.36

1.40

1.44

1.48

Normalized Dyanmic Power

Pro

babi

lity

10% delay variation 20% delay variation 30% delay variation

0.00

0.10

0.20

0.30

0.40

0.50


Prob

abili

ty

10% delay variation 20% delay variation 30% delay variation

C432 unoptimized for glitchesC432 unoptimized for glitches

C432 optimized by path balancingC432 optimized by path balancing

Nominal


Previous Work and Problem StatementPrevious Work and Problem StatementPrevious Work: Mixed integer linear program (MILP) for optimum Dual-Vth and delay buffer assignment for

Minimum leakage Glitch elimination Overall delay specification Lu and Agrawal, “CMOS Leakage and Glitch Minimization

for Power-Performance Tradeoff,” JOLPE, vol. 2, no. 3, pp. 1-10, December 2006.

Lu and Agrawal, “Statistical Leakage and Timing Optimization for Submicron Process Variation,” Proc. 20th Int. Conf. VLSI Design, Jan. 2007, pp. 439-444.

Problem Statement: Minimize leakage and glitch power considering process variation.


Techniques to Eliminate GlitchesTechniques to Eliminate Glitches

Hazard Filtering Hazard Filtering (Gate/Transistor Sizing)(Gate/Transistor Sizing)

Increase gate inertial delayIncrease gate inertial delay Sizing gate to change gate delaySizing gate to change gate delay

Path BalancingPath Balancing Decrease path delay differenceDecrease path delay difference Insert delay elements on the Insert delay elements on the

shorter delay signal pathshorter delay signal path

path delay difference < gate inertial delay path delay difference < gate inertial delay [1][1]

1

2

2→3

1

2

2

1.5

→0.5

?

[1] V. D. Agrawal, International Conference on VLSI Design, 1997


Glitch EliminationGlitch Elimination

For every gate i:For every gate i: Without process variation: | Ti – ti | Without process variation: | Ti – ti | ≤ Di≤ Di

With process variation: Prob{ With process variation: Prob{ | Ti – ti | | Ti – ti | ≤ Di } ≥ ≤ Di } ≥ ηη

Inertial delayDi

Signal arrival time windowSignal arrival time window[ ti, Ti][ ti, Ti]

Di = Xi Di(low Vth) + (1 – Xi) Di(high Vth), Xi = [0,1]Di = Xi Di(low Vth) + (1 – Xi) Di(high Vth), Xi = [0,1]Leakage(i) = Xi Leajage(low Vth) + (1 – Xi) Leakage (high Vth)Leakage(i) = Xi Leajage(low Vth) + (1 – Xi) Leakage (high Vth)


A Mixed Integer Linear ProgramA Mixed Integer Linear Programfor Leakage and Glitch Power Reductionfor Leakage and Glitch Power Reduction

Objective function (linear approximation):Objective function (linear approximation):

Minimize {CMinimize {C11··Total leakageTotal leakage + C + C22··Total glitchTotal glitch

suppressing delayssuppressing delays}}


MILP Formulation MILP Formulation (Deterministic vs. Statistical)(Deterministic vs. Statistical)

Deterministic ApproachThe delay and subthreshold current of every gate are assumed to be fixed and without any effect of the process variation.

Basic MILP– Minimize total leakage while keeping the circuit performance unchanged.

Minimize i gate number

Subject to k PO

i

isubnomI ,

maxTTPOk

Statistical ApproachTreat delay and timing intervals as random variables with normal distributions; leakage as random variable with lognormal distribution

Basic MILP – Minimize total nominal leakage while keeping a certain timing yield (η).

Minimize i gate number

Subject to k PO

i

isubnomI ,

maxTTP POk


Delay Distribution without Considering Delay Distribution without Considering Process VariationProcess Variation

Gate delay di

Timingwindow

Ti - ti

di >= Ti-tiglitch free

di <= Ti-tiwith glitch

di = Ti-ti

Gate delay di

Timingwindow

Ti - ti



di = Ti-ti

Circuits unoptimized for glitchCircuits unoptimized for glitch Circuits optimized for glitch Circuits optimized for glitch by path balancingby path balancing


Delay Distribution under Process VariationDelay Distribution under Process Variation

Gate delay di

Timingwindow

Ti - ti



di = Ti-ti

Gate delay di

Timingwindow

Ti - ti



di = Ti-ti

Circuits unoptimized for glitchCircuits unoptimized for glitch Circuits optimized for glitch Circuits optimized for glitch by path balancingby path balancing

Glitch power of unoptimized circuits is not sensitive to process variation;Glitch power of unoptimized circuits is not sensitive to process variation;Glitch power of circuits optimized by path balancing is sensitive to process variation.Glitch power of circuits optimized by path balancing is sensitive to process variation.


Technique of Enhancing the Resistance Technique of Enhancing the Resistance

of Glitch Power to Process Variationsof Glitch Power to Process Variations

Leave a relaxed margin for process variation resistance in advanceLeave a relaxed margin for process variation resistance in advance

Gate delay di

Timingwindow

Ti - ti



di =Ti-ti

iii tTD )3()3(3iiiiii ttTTDD


Results for C432Results for C432

0.00

0.10

0.20

0.30

0.40

0.50

0.95

0.97

0.99

1.01

1.03

1.05

1.07

1.09

1.11 1.13

1.15

1.17

1.19

1.21

1.23


Prob

abili

ty

statistical µ=1.04 3σ/µ=2.82% (µ-N)/N=3.63%

determistic µ=1.14 3σ/µ=5.13% (µ-N)/N=13.53%

0.00

0.05

0.10

0.15

0.20

0.50

0.65

0.80

0.95

1.10

1.25

1.40

1.55

1.70

1.85

2.00

2.15

2.30

2.45

2.60

2.75

2.90

Normalized Leakage

Pro

babi

lity

statistical N2=1.94 µ=2.25 σ/µ=10.24% (µ-N1)/N1=16.97%

deterministic N1=1.00 µ=1.17 σ/µ=6.64% (µ-N2)/N2=15.22%

Monte Carlo Simulation (15% local process variation)

C432 optimized by the statistical MILP with greater emphasis on glitch power to process variation (blue)

C432 optimized by the deterministic MILP (Purple)

Subthreshold LeakageSubthreshold Leakage(Spice simulation)(Spice simulation)

Dynamic PowerDynamic Power(logic simulation)(logic simulation)


0.00

0.05

0.10

0.15

0.20

0.25

Leakage Power (uW)

Pro

babi

lity

C7552_d

C7552_p99

C7552_p95

Results of MILP:Results of MILP: Leakage Power Distribution Leakage Power Distribution of Optimized Dual-of Optimized Dual-VVthth C7552 C7552

Mean and Standard Deviation of leakage power are reduced by the statistical method.


ConclusionConclusionCircuits optimized of glitch suppression can Circuits optimized of glitch suppression can be seriously degraded by process variation.be seriously degraded by process variation.

Overdesign (3Overdesign (3σσ variation) variation) may reduce may reduce sensitivity to process variation.sensitivity to process variation.

Statistical design (specified yields) can give Statistical design (specified yields) can give improved tradeoffs between leakage power, improved tradeoffs between leakage power, glitch power and timing.glitch power and timing.


Future WorkFuture Work Timing violations were found

The interdependency of delays of gates was neglected for simplicity in our MILP formulation.

If any timing violation is found, the new delays for all LVT cells are extracted from the current dual-Vth

design and the MILP formulation is updated correspondingly. A different optimal solution is then given by the CPLEX solver with fewer timing violations. We continue iterations until all timing violations are eliminated.

FF FF

2 2 3

2 3 3.2

132

8ns

LVT design

dual-Vth design

+ +

++

=

=8.2ns

7ns

gate delay

Iterative MILP Iterative MILP

for dual-Vfor dual-Vthth design design

Jan 4-8, 2008Jan 4-8, 2008 VLSI Design ConferenceVLSI Design Conference 1919

Thank You All !Thank You All !

Questions?Questions?

jan 4-8, 2008 vlsi design conference 1 total power minimization in glitch-free cmos circuits...

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