jag are port
TRANSCRIPT
CHAPTER 1
PREAMBLE
In this section some of the important topics such as the main objective of the project, its
problem definition are described.
1.1 Problem Definition
Our work is to design the circuits with transmission line using RF concept and to prove
that power is not only depending on the transmitter and receiver circuits but transmission
line also contribute for that. So after designing these circuits we are proving that even
though MJ-DB having more number of transistors still because of on chip interconnects
(transmission line) we can reduce the power of overall circuit.
1.2 Objective
The main objective of the thesis is to design the circuits with transmission line using RF
concept and to prove that power is not only depending on the transmitter and receiver
circuits but transmission line also contribute for that.
1.3 Motivation:
A large proportion of design effort and attention on efficient interconnect design is
essential in current CMOS technology circuit design, particularly to address power
consumption on interconnects.
Many new interconnect circuit techniques involving low-swing signaling have been
proposed. To assess their effectiveness, an objective comparison should be made.
However, this might not be a trivial task to perform. When a new signaling technique and
circuit architecture are proposed, they are normally tested with some reasonable
methodology to obtain its speed and power consumption characteristics. A comparison is
then made to a previously published technique.
The parameters that are commonly used as key indicators of success of new techniques
are their power reduction over a known previous technique.
However, a difficult problem arises from these customary testing methods, especially
when comparing power dissipations of different signaling circuits. Many factors affect
power dissipation, therefore in order to measure power for a certain technique, those
factors must be put into consideration. Comparative study of different interconnect
circuits have been performed in , and the task of comparing performance of a proposed
circuit to another benchmark circuit has been widely used in many papers proposing new
novel circuit ideas for power improvements. With this fair comparison as our initial
objective, another crucial step arises in completing this task. Each circuit should be
optimized before being compared. This leads to a completely new problem of circuit
characterization and optimization process, which as the understanding of the author, have
not been fully explored and analyzed for various low-swing interconnect circuits.
Therefore, this thesis will study, characterize, and analyze the design and optimization
process necessary for low-swing interconnects circuits.
The goal of this analysis is to find the optimum power consumption that is
possible under a certain design topology. It is also hoped that this study will be able to
deliver more objective and accurate Results and conclusions. To begin with, this paper
reviews existing low swing on-chip interconnect circuits, which all have the goal of
achieving lower power. In this study, a comparison is made using estimation and
simulation methods under a testing condition close to real situations that consider realistic
wire dimensions and its resistive and capacitive parameters. The technology node used
throughout this study is the 180 nm technology process.
1.4 Methodology:
With the stated goal above, we develop a framework of our methods as follows. The
whole work will be done using technological parameters from Tanner EDA 180nm tool.
In order to find the energy-delay trade-off characteristics of an interconnect circuit, a
simplified test circuit will be required. Using this test circuit, delay and power will be
estimated. SPICE simulations are done using the Tanner EDA Tool.
Most low-swing voltage techniques to-date [1], [3] rely on extra power supply, or
reference voltage, multiple threshold process technology, large area penalty, and multiple
wire interconnects when differential signaling is employed [4]. They also suffer from
large short-circuit current problem, long propagation delay, and high power dissipation.
Due to reduction in the voltage swing, drivers for the low swing voltage signaling
schemes generally do not provide sufficient driving capability for the larger loads. In
order to improve the driving capability, some driver circuits rely on bootstrapping
techniques. However, these circuits require extra bootstrapping capacitors, and generally
need access to the well terminals that may not be readily available in many digital CMOS
processes. The interconnect signaling schemes employing low-swing bus drivers; require
suitable matching level converters at the receiver end. If the receiver is not designed
properly it results in excessive static power dissipation and loss of performance. The work
in [3] proposes a series of level converters in the HOA signaling schemes that consume
low power and are very fast. However, the level converters in [3] require two power
supplies; Vdd1, (conveniently can be set to Vbus), and Vddh. They also require nMOS
devices with two different threshold voltages, Vtn1 (lower threshold voltage) and Vtnh
(high threshold voltage). Unfortunately, there is no reported suitable low complexity
circuit design, in the literature, for the level restorer at the receiver side for the LHOS
signaling schemes. Two new low power LHOS (mj-sib and mj-db) signaling schemes
with high driving capability at the driver side and suitable matching low power level
restorer at the receiver side.
During the course of the project, various books, texts and papers were referred to the
various IEEE papers which we referred are as follows.
.
2.1 Dynamic Diode-Connected Driver
The concept of DDCD is made in designing of driver circuit where in which the diodes
are realized or formed by using a cmos transistor, this is carried out by connecting the
gate terminal to the drain terminal, here only the driver is designed and the simulation
results showed a reduction of the energy-delay product between 27% and 54% when
compared with the full swing CMOS buffer for a 0.5mm and 0.18 mm process. Unlike
most alternatives, no extra power supplies, nor a multi-threshold process, are required.
Figure 2.1 Dynamic diode connected driver
Working:
The working of the driver circuit can be explained in there different conditions which are
as follows, initially assuming the input is high. The transistorsM3, M4 and M6 are on and
M1 (the N driver), M2, M5and M7 are off (M1 off mode).
At the input transition from high to low, M4, M3 and the P driver (M8) are turned off,
while the gate of the N driver (M1) is charged, through M5-M6, fully activating the
output transistor (active mode).
Then, as the line is driven towards ground, M7, now active, turns M6 off and enables M2
to turn on. At this moment, the gate of the N driver (M1) “holds” the charge while the line
is discharging but not yet low enough to activate M2.When M2 is active, the voltage at
the gate of M1 is driven to match the line (“diode-connected” mode). At an input
transition from low to high, the same sequence is applied to the P driver (M8) side.
2.2 Asymmetric Source–Follower Driver with Level Converter (ASDLC):
The concept of (ASDLC) is made in designing of receiver circuit and this is a
An asymmetric version of the SSDLC (Symmetric Source–Follower Driver with Level
Converter) [] scheme is shown in below Figure 2.2
Figure 2.2 Asymmetric Source–Follower Driver with Level
Converter
2.3 Asynchronous level converter topologies.
The various topologies are presented in [] for our project the standard pass gate logic
And keeper M4 split topology as shown in figure2.3 and 2.4 are made used in
Designing the receiver, Fig. 2.3 [labeled PG] shows a level converter described in [] that
is based on a weak feedback pull-up device (M4) and an nMOS pass gate (M1). The
purpose of the pass gate device is to isolate the input of the pMOS M3 from the previous
logic stage. The feedback device M4 can then pull-up the internal node without
consequence to the prior logic that is running at VDDL. This level converter consumes
less energy than the DCVS [] level converter due to its fewer devices and reduced
contention.
Figure2.3 standard pass gate logic
Fig. 2.4 [STR1] shows the first new level converter that they as in [] As seen in the figure,
the feedback device M4 (keeper) from Fig. 2.3 is split into two devices M4 and M5.This
is a known high-performance dynamic design technique and the advantage of this change
is to reduce the capacitive load (gate capacitance of the keeper device) on node N [in Fig.
2.3]. When sized properly, M5 is larger than M4 (which tends to minimum width and
length) thus reducing the loading on transistors M2 and M3 by the keeper. This allows
M2 andM3 to be sized smaller, reducing the total energy consumption.
;
Figure2.4 keeper M4 split
2.5 Multi junction driver:
The concept of multi junction driver is well described in this paper and design of a high
performance, adaptive low/high swing CMOS driver circuit (mj–driver) is carried out
which is suitable for driving of global interconnects with large capacitive load is
presented showing a better performance performance of 16% faster, reduces the power
consumption by 3%, and energy delay product by 19% than when compared with a
counterpart driver in diode–connected configuration. On the other hand, mj–driver has
47% lower active area and only requires one set of sizing for optimum performance at 1
and 0.8V. Furthermore, unlike its counterpart this exhibits 30% variation in output swing
voltage with variation in the load, the output voltage swing for the mj -driver remains
unchanged with the output load.
Figure 2.5 multi junction driver configuration
The above figure shows the configuration of mj driver which is adaptive in nature
It is a UDLD based low swing driver, where the output stage achieves symmetrical low
swing through the use of diode connected transistors pairs (MD10–MD11) and (MU10–
MU11).
In addition to the output stage the circuit provides high current driving capability through
the use of multi–path technique where two separate paths are provided for assisting low–
to–high and high–to–low transitions at the output (upper and lower half of the circuit in
Fig. 2.4, respectively).
The combination of these two paths and the feedback path through XIF1 provides for
large output currents and fast switching of the output during the transitions, as will be
described [].
CHAPTER 2
Concepts of Power Dissipation(incomplete)
2.1 Power Dissipation Models
The total power dissipation on the chip can be divided into four classes:
interconnects logic, memory, and clock distribution and latches. Clock distribution and
latches are considered separately owing to the high duty cycle of the clock signal. For the
logic and memory, power can further be classified as being dynamic power or static
(leakage power). The modeling of leakage power would be identical for logic and
memory.
2.1.1 Interconnect power dissipation model
Only the interconnects that are part of the logic are modeled, as memory is quite different
and cannot be modeled using the stochastic wire length distributions. Local, intermediate
(semi-global) and global tiers need to be considered separately.
2.1.2 Memory power dissipation model
The dynamic power dissipation in memory occurs only during reads and writes. The
dominant part of the power dissipation is the charging and discharging of the huge
capacitance of the wires and the transistors connected to these wires.
2.1.3 Leakage power dissipation model
For the leakage power calculation, total leakage current is calculated based on the ITRS
projections for transistor leakage current per unit width.
2.1.4 Clock power dissipation model
Depending on skew objectives, there are a number of clock distribution schemes. The
least expensive in terms of power, but with most skew, is the H-tree based clock
distribution scheme. Most aggressive is a complete grid based clock distribution of the
Alpha microprocessors that achieves low skews even with non-uniform loading.
It is clear that the scaling of interconnects and transistors have very different
impacts on semiconductor technology. In particular, the inability of the latency of global
interconnects to scale with the technology has rather profound impacts on design
architectures. There are many approaches for addressing the global interconnect issues
including reverse scaling, LC transmission lines, 3D integration, optical interconnects and
carbon nano tubes. Each of these options has its merits and penalties with respect to
metrics of interest such as delay, energy per bit, bandwidth, pitch, form factor and multi-
chip dimension for different interconnect lengths. In this paper, each of the above options
is quantitatively benchmarked with respect to the metrics of interest using HSPICE circuit
simulations with identical boundary conditions and methodologies. With the diverse
number of applications, each of these options has its niche, but scaled and 3D
interconnects appear to be the most widely applicable options.
Transistors sizing:
In integrated circuits design, it is customary to trade off speed for energy, Given a
specific delay requirement, wire length, and driver supply voltage, find the driver and
load transistor widths (Wp and Wn, respectively) for the minimum power.
Given a certain driver and load transistor size and a known wire resistance, the amount of
current that flows through the circuit is found by using the numerical analysis
methods(bidirectional theorem) so that for a particular value all the transistors should
conduct in saturation region this makes us to note the correct value of current .
After the current flow is computed, using the other parameters value the Wp and Wn can
be estimated using the current equation Id which is given below.
W/L=2Id/ µn Cox (VDsat )2
The value for the µn , µp , Cox , Vtn , Vtp is taken from the tanner library ,using those value
the current is calculated
µn = 0.1522
µp =.16953
Cox =6.059×10-3
Vtn =0.18V
Vtp = -0.1248V
I d is equal to 200 µA
Calculation of interconnects capacitance and resistance:
R=Rsh ×L
W
Rs=1030
R=1030×1 µ
103 n
Interconnect Capacitance
C=Cs h× C 0A
ε0 =80854×10-12
A=area =L×W
L=1.49×10-7
W=130×10-9
A=19.4ρm
C=1ρf
Current-mode signaling:
Another potential solution to the speed limitation problem of on-chip interconnects
signaling is the use of current-mode signaling instead of voltage mode signaling. In a
current-mode signaling scheme, a low resistance terminates the interconnect at the
receiver end. But they also reported that by using current mode signaling, a data rate up to
1 Gb/s was achievable, unlike the voltage mode signaling where data rates up to 600 Mb/s
was successfully measured
Interconnect model:
A distributed RC model of a transmission line would be the accurate model of an
interconnect wire. Each point along the transmission line for this distributed model has a
different resistive and capacitive value, depending on the distance from its end. However
due to its complexity, lumped RC model are normally employed instead [17]. This type of
modeling is simple and sufficient to approximate signal delay and cross-coupling effects
to a first order. Weste [20] who cites [22] mentions the sufficiency of a three segment π
model wire for simulations because it can give a good accuracy, with a
Deviation only up to 3%. Interconnects modeled as RC π3 structures are also used in [11],
and the schematic is shown in the below Figure. These are three segments of lumped RC
model in the π structure connected together. Such segmentations are used if the wire
being modeled is significantly long.
An empirical rule to determine whether the wire length is long enough to be modeled as
segments is given by
Length
Where is the signal wavelength.
Interconnect wires modeled as 3 RC line
Resistance:
The interconnect is a combination of RC with R=50Ω and C=1Pf
This value is calculated using formula
R=t d*Z0
C1=C2 = t d/Z0)
Where Z0 is the impedance of the transmission line & t d is the rise time.
A simple buffer is used as the receiver this is reduce the circuit complexity.
The total resistance of a wire is given as:
R= ρ ×lt × w
=Rslw
Where Rs=1030
R=1030×1µ
103 n
R=10K
where w is the width, t is the thickness, and l is the length of the wire. The resistivity
parameter for Cu is 2.2 /cm, while for Al is 3.3 /cm. Due to its lower
resistivity, therefore Cu is now being used as metal layers for current and future
technologies [24]. Even though copper is a solution to address the issue of increasing wire
delay, this will not be long before the same delay severity reoccurs in future technologies.
Circuit topologies
The basic principle of low-swing interconnect is that if a signal line's swing can be
reduced, it will be easier to switch. Initially this was used to make faster interconnections.
However, more recently this has been used to decrease switching power. The trade of in
power reduction is that more complicated drivers and receivers and possibly additional
power supplies are needed. These extra circuits and supplies will require additional
power, making low-swing interconnect inefficient for some situations. Several driver and
receiver circuits are presented here.
The schematic has 3 parts namely driver, inter-connect, & receiver.
The various circuit topology which are designed in the project are as follows
DDC DB(dynamically diode connected driver circuit )
ASFLC(asymmetric source follower level converter circuit)
MJSIB (Multi-junction single band )
MJDB Multi-junction double band
DDC DB:
From the above figure we can make out that before driver circuit set of inverter
and buffers and nand gate is connected, the main reason behind using the concept
of merging and splitting of inverter is to increase fan-out and to split the current in
the circuit .Nand gate uses the same input from the previous inverter .The nand
gate is used to send particular output to the next stage.
The driver circuit is designed using a dynamic diode (diode are realized using
cmos)
Totally we are using two dynamic diodes. The next stage comes the driver circuit
which is used to drive the in to output side effectively.
The current in the diode is controlled using a set of cmos transistors which is as
shown in figure this circuitry is used to split the current so that excess current
can’t be able to harm diode.
ASFLC(asynchronous level converter circuit).
This driver is designed using a source follower (it is a circuit senses the signal at
the gate & drives potential to follow the gate voltage)
The receiver may be a simple inverter or level converter circuit.
At point x1 if the value is zero, pmos conducts and the above pmos is always on
as its connected to gnd and this particular operation makes the output to pass
through lower transistors if the value is 1 the output follows the same direction .So
the working principle behind level converter is to get the output at different time
scale also possible.
Mjsib
Driver circuit
The input signal is fed to an inverter that helps in increasing the fan-out to be able to be to
drive three other gates i.e. a NAND, NOR and NOT gates. The whole group of logic gates
before the DDC topology is to maintain the input signal within the stable limits.
When inmj=0, MU11 is ON and as a result of which, the gate and drain of MU10
are at the same potential. UD2=0, turning MD7 OFF and MD8 ON as a result of
which MD10 is OFF and MD11 is also OFF.
The output from XIM2 = 1, turning MU8 OFF.
MU10 provides a path between the outmj to the ground meaning low voltage or 0
bit is transmitted.
Transmission Line
The transmission line is designed with r-Π model analogy, consisting on cascaded
resistors and capacitors.
So we are to find a particular value of resistance and capacitance such that signals
of any frequency can be transmitted without disrupting the key features of the
signal.
Receiver Circuit
M1 and M9 act as pass transistors and always at saturation as per the circuit, so M3 and
M2 together act as an inverter.
We have two level converters that feed back the intermediate output signal in both the
cases (for both high and low voltage signal).
If Out1=0, this signal is sent forward via a buffer and hence out sib = 0
At the same instant, if the requited/expected voltage signal (or bit) is not received,
it is fed back via an inverter to transistors M4 and M11
Out1=0 means high voltage is at the inverter output node 3, this high output will
switch M4 OFF and M11 ON and M10 being always ON, so node 4 is grounded
and it turns M2 OFF.
Further, M9 and M1 being always ON will switch M3 ON and thus providing a
conduction path between node3 and Vdd.
The high voltage from Vdd then encounters an inverter and hence giving a low
voltage signal/ bit at outsib. As for Out1 = 1, the upper level converter will be
active and hence sending a high voltage signal/ bit at outsib.
Mjdb
Driver circuit
The input signal is fed to an inverter that helps in increasing the fan-out to be able to be to
drive three other gates i.e. a NAND, NOR and NOT gates. The whole group of logic gates
before the DDC topology is to maintain the input signal within the stable limits.
When inmj=0, MU11 is ON and as a result of which, the gate and drain of MU10
are at the same potential.
UD2=0, turning MD7 OFF and MD8 ON as a result of which MD10 is OFF and
MD11 is also OFF.
The output from XIM2 = 1, turning MU8 OFF.
MU10 provides a path between the outmj to the ground meaning low voltage or 0
bit is transmitted.
Transmission Line
The transmission line is designed with r-Π model analogy, consisting on cascaded
resistors and capacitors.
So we are to find a particular value of resistance and capacitance such that signals
of any frequency can be transmitted without disrupting the key features of the
signal.
Receiver circuit
There are two inverters cascaded forming a buffer to stabilize the intermediate signal that
may be affected by noise. Thus the required signal is received.
WHAT IS LAYOUT?
Integrated Circuit (IC) Layout or mask design is the representation of an integrated circuit
in terms of planar geometric shapes which correspond to the patterns of metal, oxide, or
semiconductor layers that make up the components of the integrated circuit.
In other words, Layout is the process by which a circuit specification is converted to a
physical implementation with enough information to deduce all the relevant physical
parameters of the circuit.
A layout engineer’s job is to place and connect all the components that make up a chip so
that they meet all criteria. Typical goals are performance, size, and manufacturability path
on the architecture level.
THE ROLE OF LAYOUT IN THE DESIGN PROCESS:
From a computer scientist’s point of view, the layout process seems familiar enough. We
are given a piece of source code, this time usually in terms of a Circuit diagram, and we
want to compile it to an object code, the physical layout of the circuit.
The entire process consists of three steps, partial product generation, partial product
reduction and final addition. The layout step is the last major step in the design process
before testing and fabrication; it is the step which reveals to the designer all the subtle
electrical characteristics of the clean and logical digital systems.
TOLERANCES AND DESIGN RULES:
The layout must pass a series of checks in a process known as Verification. The two most
common checks in the verification process are Design Rule Checking (DRC), and Layout
Versus Schematic (LVS). When all verification is complete, the data is translated into an
industry standard format, typically GDSII, and sent to a semiconductor foundry.
The process of sending this data to the foundry is called tape out, due to the fact the data
used to be shipped out on a magnetic tape. The foundry converts the data into another
format and uses it to generate the photo masks used in a photolithographic process of
semiconductor device fabrication.
DESIGN RULE CHECK:
Design Rule Checking of Check(s) (DRC) is the area of Electronic Design Automation
that determines whether a particular chip layout satisfies a series of recommended
parameters called Design Rules. Design Rule Checking is a major step during Physical
Verification of the design, which also involves LVS (Layout
Versus Schematic) Check, XOR Checks, ERC (Electrical Rule Check) and Antenna
Checks. Design rules are a set of parameters provided by the semiconductor manufacturer
that enable the designer to verify the correctness of the mask set.
Design rules are specific to a particular semiconductor manufacturing process. A design
rule set specifies a minimum size or spacing requirements between the layers of the same
type or of different types. This provides a safety margin for various process variations, to
ensure that the design will still have reasonable performance after the circuit is fabricated.
There is a limit to how small features the photolithographic process can generate.
Generally, this feature size is the width of a single minimum-width poly silicon wire used
as a transistor gate (since this is the most important physical dimension in determining the
speed of circuit)
Basic Design Rules are
(1) Size Rules.
(2) Separation Rules.
(3) Overlap Rules.
The most important design rules are summarized below (all distances are minimum):
Poly silicon Region Width 0.18μm Poly – Poly Spacing 0.18 μm
Poly silicon Gate Extension 0.22 μm P/N Select Extension 0.23 μm
Diffusion- Diffusion Spacing 0.9 μm Contact Extension 0.1 μm
Metal1 Width 0.24 μm Metal1- Metal1 Spacing 0.24 μm
Metal1 Width 0.28 μm Metal2 _ Metal2 Spacing 0.28 μm
Via Size 0.36 μm
LAYOUT VERSUS SCHEMATIC (LVS):
The Layout Versus Schematic (LVS) is the class of electronic design automation (EDA)
verification software that determines whether a particular integrated circuit layout
corresponds to the original schematic of circuit diagram of the design.
A successful Design rule check (DRC) ensures that the layout conforms to the rules
designed / required for faultless fabrication. However, it does not guarantee if it really
represents the circuit you desire to fabricate. This is where an LVS check is used.
LVS checking software recognizes the drawn shapes of the layout that represent the
electrical components of the circuit, as well as the connections between them. The
software then compares them with the schematic or circuit diagram. In most cases the
layout will not pass LVS the first time requiring the layout engineer to examine the LVS
software's reports and make changes to the layout.
CHAPTER 4
Schematic, Layout and Simulation tool
4. Tanner EDA Tools
T-Spice Pro includes 4 main elements:
4.1 T-Spice: Analog Simulation
T-Spice is a complete design capture and simulation solution that provides accuracy and
convergence with market-proven reliability. To transform your ideas into designs, you
must be able to simulate large circuits quickly and with a high degree of accuracy. That
means you need a simulation tool that offers fast run times, integrates with your other
design tools, and is compatible with industry standards. To transform your ideas into
designs, you must be able to simulate large circuits quickly and with a high degree of
accuracy. That means you need a simulation tool that offers fast run times, integrates with
your other design tools, and is compatible with industry standards.
T-Spice offers HSPICE® and PSpice® compatible syntax and supports the latest
industry models, including PSP, BSIM3.3, BSIM4.6, BSIM SOI 4.0, EKV 2.6,
MOS 9, PSP, RPI a-Si & Poly-Si TFT, VBIC, and MEXTRAM models to allow
easy integration of legacy designs and foundry models.
T-Spice lets you precisely characterize circuit behavior using virtual data
measurements, Monte Carlo analysis, and parameter sweeping.
For greater efficiency and productivity, T-Spice puts you in control over your
simulation process with an easy-to-use graphical interface and a faster, more
intuitive design environment.
With key features such as multi-threading support, automatic selection of
advanced convergence algorithms, and “.alter” command for easy what-if
simulations with netlist changes, T-Spice saves you time and money during the
simulation phase of your design flow.
4.2 S-Edit: Schematic Capture
Tightly integrated with Tanner EDA’s T-Spice™ simulation, L-Edit™ layout, and
HiPer™ verification tools, S-Edit gives you the power you need to handle your most
complex full custom IC design capture. Its efficient design capture process integrates
easily with third-party tools and legacy data. S-Edit enables you to explore design choices
and provides an easy-to-use view into the consequences of those choices.
S-Edit’s tight integration with SPICE simulation allows viewing operating point
results directly on the schematic and performing waveform cross-probing to view
node voltages and device terminal currents or charges.
S-Edit imports schematics via EDIF from third party tools, including Cadence,
Mentor, Laker, ORCAD and ViewDraw with automatic conversion of schematics
and properties for seamless integration of legacy data.
S-Edit’s schematic design checks enables you to check your design for common
errors such as undriven nets, unconnected pins and nets driven by multiple outputs
so you can catch errors early before running simulations.
4.3 W-Edit: Waveform Viewing & Analysis
The W-Edit waveform analysis tool is a comprehensive viewer for displaying, comparing,
and analyzing simulation results. W-Edit provides an intuitive multiple-window,
multiple-chart interface for easy viewing of waveforms and data in highly configurable
formats
W-Edit is dynamically linked to T-Spice and S-Edit with a run-time update feature
that displays simulation results as they are being generated and allows waveform
cross-probing directly in the schematic editor for faster design cycles.
Focus on and optimize your design with W-Edit’s advanced features such as
automatically calculating and displaying FFT results in a variety of formats,
including dB or linear magnitude, wrapped or unwrapped phase, and real or
imaginary parts.
W-Edit allows creation of new traces based on mathematical expressions of other
traces for advanced analysis and easy comparison with measured data.
4.4 L-Edit
L-Edit is an easy to learn draw type LAYOUT EDITOR from Tanner Research.
While it is primarily a VLSI design tool, it is also flexible enough to do
micromachining design, printed circuit board layout, and other CAD work. The
multipass display is particularly powerful (layers can be semi-transparent; where two
layers overlap, a third color is produced), as is the hierarchy of cells and layers.
Changes to a cell (or group) are propagated to all instances and arrays of that cell. The
drawing tool pallet includes standard tools and supports right angle, 45 degree, and all
angles modes (unusual for VLSI CAD programs).
CHAPTER 7
SIMULATION RESULTS
CIRCUIT STRUCTURE FOR LOW-HIGH OFFSET SYMMETRIC (LHOS) CMOS
DRIVER–RECEIVER DDC–DB:
Layout of DDC -DB:
Power results of DDC-DB:
Circuit Structure for High Offset Asymmetric (HOA) CMOS Driver–Receiver asf -lc:
Layout:
ASF_LC OUTPUT:
Power results:
Mj-sib layout:
Mj sib output:
Power results :
Mjdb schematic:
Mj-db layout:
Mj-db output:
Power results:
CHAPTER
BIBLIOGRAPHY
[1] H. Zhang, V. George, and J. M. Rabaey, “Low-swing on-chip signaling techniques:
Effectiveness and robustness,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst.,
vol. 8, no. 3, pp. 264–272, Jun. 2000.
[2]. E. Kusse and J. M. Rabaey, “Low-energy embedded FPGA structures,” in Proc. Int.
Symp. Low Power Electron. Des., Monterey, CA, Aug.
1998, pp. 155–160.
[3]. A. Rjoub and O. Koufopavlou, “Efficient drivers, receivers and repeaters for low
power CMOS bus architectures,” in Proc. IEEE Int. Conf. Electron., Circuits Syst., Pafos,
Cyprus, Sep. 1999, vol. 2, pp. 789–794.
[4]. M. Ferretti and P. A. Beerel, “Low swing signaling using a dynamic diode-connected
driver,” in Proc. Solid-State Circuits Conf., Villach, Austria, Sep. 2001, pp. 369–372.
[5]. S. H. Kulkarni and D. Sylvester, “High performance level conversion for dual
design,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 9, pp. 926–936,
Sep. 2004.