j11 mlb pib schematic 2.6 - assistenza apple | … · schematic / pcb #’s j11 mlb pib schematic 1...

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TABLE_TABLEOFCONTENTS_HEAD

DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL

TABLE_TABLEOFCONTENTS_HEAD


DRAWING


2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

PROPRIETARY PROPERTY OF APPLE INC.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

DESCRIPTION OF REVISION

CKAPPD

2 1

1245678

B

D

6 5 4 3

C

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

THE INFORMATION CONTAINED HEREIN IS THE

C

A

D

DATE

R

SHEET

Apple Inc.

THE POSESSOR AGREES TO THE FOLLOWING:

DRAWING TITLE

DSIZE

REVISION

DRAWING NUMBER

BRANCH

REV ECN

7

B

3

II NOT TO REPRODUCE OR COPY IT I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

IV ALL RIGHTS RESERVEDIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

8

02/23/122.6.0

PCB TO BE SILK-SCREENED WITH UL/CUL RECOGNITION MARK, MANUFACTURER’S UL FILEPCB, UL RECOGNIZED, MIN. 130-C TEMP. RATING AND V-0 FLAME RATING PER UL 796 & UL 94.PRODUCT SAFETY REQUIREMENTS:

NUMBER, UL PCB MATERIAL DESIGNATION, 130-C TEMP. RATING AND V-0 FLAME RATING.

Schematic / PCB #’s

J11 MLB PIB SCHEMATIC

1 OF 72

2012-02-23

1 OF 109

2.7.0

051-9276

J13_MLB4554

High Side Current Sensing09/15/2011

J13_MLB4453

Voltage & Load Side Current Sensing09/15/2011

J13_MLB4352

SMBus Connections10/05/2011

K21_MLB4251

LPC+SPI Debug Connector12/13/2010

J13_MLB4150

SMC Support10/06/2011

J30_MLB4049

SMC07/26/2011

N/A3947

LIO CONNECTORSN/A

J13_MLB3846

External A USB3 Connector10/06/2011

J13_MLB3745

SSD CONNECTOR11/18/2011

J13_MLB3640

X21 WIRELESS CONNECTOR10/06/2011

J13_MLB3538

TBT Power Support11/18/2011

J13_MLB3437

Thunderbolt Host (2 of 2)09/01/2011

J13_MLB3336

Thunderbolt Host (1 of 2)02/22/2012

K21_MLB3234

DDR3 DRAM Channel B (32-63)12/13/2010

J13_MLB3133

FSB/DDR3/FRAMEBUF Vref Margining11/18/2011

J13_MLB3032

DDR3 DRAM CHANNEL B (32-63)08/29/2011

J13_MLB2931

DDR3 DRAM CHANNEL B (0-31)08/29/2011

J13_MLB2830

DDR3 DRAM CHANNEL A (32-63)08/29/2011

J13_MLB2729

DDR3 DRAM CHANNEL A (0-31)08/29/2011

J13_MLB2628

CPU Memory S3 Support11/18/2011

J13_MLB2527

Clock (CK505) and Chipset Support08/12/2011

J13_MLB2426

USB HUB & MUX08/12/2011

J13_MLB2325

CPU & PCH XDP08/04/2011

J13_MLB2224

PCH DECOUPLING11/18/2011

J13_MLB2123

PCH GROUNDS08/12/2011

J13_MLB2022

PCH POWER09/22/2011

J13_MLB1921

PCH GPIO/MISC/NCTF02/23/2012

J13_MLB1820

PCH PCI/USB/TP/RSVD09/22/2011

J13_MLB1719

PCH DMI/FDI/PM/Graphics10/06/2011

J13_MLB1618

PCH SATA/PCIe/CLK/LPC/SPI02/20/2012

K21_MLB1517

CPU DECOUPLING-II12/13/2010

J13_MLB1416

CPU DECOUPLING-I08/16/2011

K21_MLB1314

CPU GROUNDS12/13/2010

J11_MLB1213

CPU POWER10/18/2011

K21_MLB1112

CPU DDR3 INTERFACES12/13/2010

J13_MLB1011

CPU CLOCK/MISC/JTAG09/22/2011

J13_MLB910

CPU DMI/PEG/FDI/RSVD10/13/2011

K91_MLB89

Signal Aliases05/15/2010

K91_MLB78

Power Aliases05/15/2010

(K99_MLB)67

Functional Test / No Test(02/16/2010)

J11_MLB_NON_POR55

BOM Configuration11/09/2011

K21_MLB44

K78 BOM Variants11/16/2010

J13_MLB33

Revision History11/18/2011

J13_MLB22

System Block Diagram11/18/2011

PCB Rule Definitions109

7201/11/2012

CONSTRAINTS

Project Specific Constraints108

7101/11/2012

CONSTRAINTS

SMC Constraints106

7001/11/2012

CONSTRAINTS

Thunderbolt Constraints105

6901/11/2012

CONSTRAINTS

PCH Constraints 2103

6801/11/2012

CONSTRAINTS

PCH Constraints 1102

6701/11/2012

CONSTRAINTS

Memory Constraints101

6601/11/2012

CONSTRAINTS

CPU Constraints100

6501/11/2012

CONSTRAINTS

LCD Backlight Driver97

6410/13/2011

J13_MLB

Thunderbolt Connector A94

6311/18/2011

J13_MLB

Internal DisplayPort Connector90

6212/13/2010

K21_MLB

Power Control 1/ENABLE79

6111/18/2011

J13_MLB

Power FETs78

6012/13/2010

K21_MLB

Misc Power Supplies77

5912/13/2010

K21_MLB

CPU VCCIO (1.05V) Power Supply76

5809/01/2011

J13_MLB

CPU IMVP7 & AXG VCore Output75

5712/13/2010

K21_MLB

CPU IMVP7 & AXG VCore Regulator74

5609/22/2011

J13_MLB

1.5V DDR3 Supply73

5510/07/2011

J13_MLB

5V / 3.3V Power Supply72

5411/18/2011

J13_MLB

System Agent Supply71

5309/01/2011

J13_MLB

PBus Supply & Battery Charger70

5210/10/2011

J13_MLB

DC-In & Battery Connectors69

5111/11/2010

K21_MLB

AUDI0: SPEAKER AMP62

5012/13/2010

K21_MLB

SPI ROM61

4910/13/2011

J13_MLB

IPD / KBD Backlight57

4812/13/2010

K21_MLB

Fan56

4712/13/2010

K21_MLB

(.csa)

ContentsPage SyncDate (.csa)

Page Contents SyncDate

Thermal Sensors55

4608/30/2011

J13_MLB

TITLE=MLB

ABBREV=DRAWING

LAST_MODIFIED=Thu Feb 23 12:05:40 2012

PCBF,MLB,J11820-3208 CRITICALPCB1

SCHEM,MLB,J11051-9276 CRITICALSCH1

MASTER11

Table of ContentsMASTER

SCHEM,MLB,J11

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT

U5700

PG 49

PCI-E

GPIOs

AXG=GT2, ULV, 1023P

PG 9

U2900-U2930U3000-U3030

PG 29,30

x8MEMORYU3200-U3230U3100-U3130

XDP CONNCPU

J2500

CHARGER

KBD DRIVER

XHCI/EHCI2

MUX

FDI

JTAG

PG 10

INTEL

EDP

PG 9 PG 9

DMI

PG 11

FDI

PG 17

INTEL CPU

IVY BRIDGE 2C-35W

PCIE0

32KHz

CLK

DMI

PG 17

U1000

TRACKPAD

PG 49

PG 23

PG 19

PG 16

VOLTAGE/CURRENT SENSOR

TBT/MLBBOT/INLET TEMP SENSOR

PG 47

J6950,U7000

PG 19

PANTHER POINT - MPCH

U1800

1017PLPC

MUX

U4510

PG 38

PG 46,47

CPU TEMP SENSOR

PG 50

(ON AP)

PG 37

BluetoothJ4001

U5750

PG 49

J5715

KBD CONN

PG 49

PG 45,46

J5600

FAN CONNPG 48

KBDLED

LID

SMB_2PG 43

PG 40

PG 39

PG 39

PG 24

SENSOR

SYSTEM

HEADPHONE

PCHXDP CONN

PG 23

J2550

PG 16

RGB OUT

DVI OUT

JTAG

PG 16 PG 16

UP TO 6

SATA

SATA0

25MHz

PG 16

PG 16

PG 16

PG 16

PG 17

CTRL

LINE IN

2

PG 18

Misc

HDAPCISMBUS

PG 18

PG 18

PG 17

PWR

PG 63

WIRELESS

PG 37

CONN

X21

PG 6

USB HUB

U2600

U6100

(UP TO 10 DEVICES)

USB

2

PG 41

SMC

PG 52,53

POWER CIRCUIT

PG 54-60

SMB_1SMB_5 SMB_3 FAN0ADC

USB A

USB MUX

J5700

U5410

U5510

DEBUG MUX

MOJO SMC

1

U4730

J5100

LPC+SPICONN

LIO BOARD

FILTERPG

PG 7

I2C

34

U4900

PM_SLP S3/S4 USB

U4650

PG 11

J4700

SNK0

SNK1

J4001

J6702

CONN

J4720

HDA

PG 11

U6620

PG 10

AMPSPEAKER

J6701

2

J6700

PG

CodecAudio

75

J9000

CONN

EDP

J4501

SATA

HDDPG 38

SPI

53

81

6

UP TO 8 LANES

LVDS OUT

HDMI OUT

J9400

PG 64

/ TBT

DPBDP OUT

U9420

PG 64

DISPLAY PORT AUXIO

MUXDPMLO

U2700

CLOCK

Conn

43

29

83

41

0

74

6

USB 3

1

BUFFER

SPIBoot ROM

SERIAL PORT

J4600

Filter

PG 9

HEADPHONE/LINE IN JACK

MIC

PG 7

RIGHT SPEAKERCONNPG 52

J6903

PG 51

AMPSPEAKERU6210

SPK

EFFECTTHERMAL

(LEFT PORT)

EXTERNAL

U2660

PG 24

USB3

PG 40

U4700

Re-DRIVER

J4750

HALL

PG 7

LEFT USB EXTBUSB CAMERA

I2C

CAMERA +ALS CONN

J4610

USB PORT B

LEFT L/O CONN I2C

LID

U6201

LEFT SPEAKERCONN

PG 11

TBT Host

PG 25

PG 34,35 37

PG 34

U3600

U3690

PCIe x4

PA_DPSRC_3

PA_CIO1

PA_CIO0

SPI

PA_LSTX/LSRX

EEPROM

25MHzXtal

PG 16

RTC

PCIE1

PG 9

EDPDP0, x1

DPC

x4

x4

PA_DPSRC_1

PA_AUX

B

MEMORY

PG 27,28

x8

ADUAL ChannelDDR3-1600MHZMEMORY

64-bit

TMDS OUT

PCI-E

System Block Diagram

SYNC_MASTER=J13_MLB SYNC_DATE=11/18/2011

051-9276

2.7.0

2 OF 109

2 OF 72

Apple Inc.


124578

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6 3



J11 POWER SYSTEM ARCHITECTURE

R6906

SLP_S4_L(P94)

25S5_PWRGD

ALL_SYS_PWRGD

KBDLED_ANPDEU5750

P5VS0_ENTPS51980

10-1PG61

P3V3S3_EN

DELAY

COUGAR-POINT PM_SLP_SUS_L 13-1

PP1V5_S3RS0_FET

23

RESET*

UNCOREPWRGOOD

SM_DRAMPWROK

30

CPU_PWRGD

PLT_RERST_L

PP1V5_S0_REG

PP1V05_S0_LDO.

U3810TPS22924

A15

22-1

PPVIN_G3H_P3V42G3H

1.05VISL95870

PM_DSW_PWRGD

U3816/U3820

27

(PAGE 41)

EN

14-1P5VS0_EN

DELAY

RC

RC

DELAY

P1V5S0_EN

P1V8S0_EN

RC

DELAY

DELAY

RC

PVCCSA_EN

1V05_S0_LDO_EN

19

17

22

21

PM_SLP_S3_R_L

P60

SMC_PM_G2_EN

SLP_S5#(E4)

RC

U7940

DELAY

RC6

P5VS3_EN

P3V3S0_EN

P5V_3V3_SUS_EN

PG62

PBUSVSENS_EN

14-1

T29_A_HV_EN

PG 17

PG 17

PG62

13&&

Q3880

U3890LT3957

VIN

(PAGE 36)PP15V_T29_REG

VOUTEN

VIN

PG62

PG 17

7

EN2

EN15V

R6905

9

EN

(PAGE 60)

ENISL8014A

U7720PP1V8_S0_REG

VOUT

S3

S5

P1V8S0_PGOOD

EN

(PAGE 60)

U7780TPS720105

(PAGE 60)

TPS72015

U7770

19

18

(PAGE 62)

V4MON

PM_SLP_S4_L

9

SLP_S3_L(P93)

PWRGD(P12)

PWR_BUTTON(P90)

RSMRST_IN(P13)

U1000

(PCH)

CPUVCCIOS0_EN U7600

3

(PAGE 42)

SMC POWER

SN0903048U5010

22

SMC_RESET_L 4

RSMRST#

PROCPWRGD

12

26

4

P1510

PM_MEM_PWRGD

28

PM_DSW_PWRGD

PM_SYSRST_L

PM_PWRBTN_L

PM_RSMRST_L

29

PPCPUVCCIO_S0_REG

5

U4900

SMC_RESET_L

PM_PWRBTN_L

PM_SYSRST_LSYSRST(PA2)

6-1

PP5V_S0_CPUVCCIOS0.

13U7201

7

PM_SLP_S5_L 11P5VS3_EN

R5430

(R/H)

PP3V3_S0

14-1

10-3

U7740

VIN

EN

PP3V3_S3_FET

14P3V3S0_EN

Q7830

Q7810

T29_PWR_EN

R7831

R4599

A

10-2

PP1V5S0_EN

PP3V3_T29_FET

17P1V8_S0_EN

(PAGE 36)

P5V_3V3_SUS_EN

A

PGOOD

Q5300

SMC_PBUS_VSENSE

U9701

LP8550

Q7820

15

BKL_EN

14

PM_SLP_S4_L

(PAGE 65)

PBUSVSENS_EN

F9700

3A 32V

VOUT2

(PAGE 55)

P3V3S5_PGOOD

13-2

BKLT_PLT_RST_L

Q9706

TBTBST_EN_UVLO

14-1

VOUT

A

PP3V3_SUS_FET

VIN

(PAGE 59)

SMC_CPU_FSB_ISENSE

VIN

VOUT

VIN

PGOOD

A

21

R7640

16-1

R7140

EN

SMC_CPU_ISENSE

PP1V05_TBTCIO_FET

25

CPUIMVP_VR_ONMAX15120

PVCCSA_ENEN

VIN

22

V3MON

PPVCORE_S0_CPU_REG

PPVIN_S5_P5VP3V3

VID0

VCC

DDRREG_EN

DDRVTT_EN

PP3V3_S5

14-1

21CPUVCCIOS0_EN

SLP_S4#(H4)

U1800

SLP_SUS#

PM_RSMRST_L

CPUIMVP_VR_ON

P3V3S5_EN

SMC_PBUS_VSENSE

(L/H)

3.3V

VOUT1

PP5V_S0_VCCSA

CPU_VCCSA_VID<1>

PP3V3_S5_REG

P5VS3_PGOODSMC

PWRBTN#

(PAGE 9~13)

P17(BTN_OUT)

99ms DLY

SLP_S5_L(P95)

(PAGE 16~21)

SLP_S3#(F4)

SYS_RERST#

COUGAR-POINT

RST*

DDRREG_PGOOD

R7350

16PLTRST#

R7550

P1V8S0_PGOOD

P5VS3_PGOOD

P3V3S5_PGOOD

A

CPUVCCIOS0_PGOOD

PM_S0_PGOOD

VOUT1

U2750

A

P1V5CPU_EN

DRAMPWROKALL_SYS_PWRGD

SMC_DELAYED_PWRGD

DPWROK

PM_SLP_S5_L

23-1

PPVCCSA_S0_REG

PVCCSA_PGOOD

PGOOD

CPU_VCCSA_VID<0>

10-4SMC_ONOFF_L

4

15

V2MON

PP5V_S3_REG

14Q7860

PP5V_S0_KBDLED

8

U2760

CPU

PM_SLP_S3_L

R7978

IMVP_VR_ON(P16)

6

PP3V3_S0_VMON

PAGE49

OUTMIC2292

VDD

ISL88042IRTEZU7960

PP1V05_SUS_LDOR7962

RC

DELAY

PG62DDRREG_EN

(PCH)

USB_PWR_EN

Q5300

VID1

EN

CPU VCORE

U7400

VCC

PVCCSA_PGOOD

(PAGE 54)

U7100

1.5V

24

TPS51916

(PAGE 56)

U7300

0.75V

ISL95870AH

VOUT

Q5310

6A FUSE

4

DCIN(14.5V)

IN

PPVBAT_G3H_CHGR_R

Q7055PPVBATT_G3H_CONN

A

P3V3S5_EN

V

(PAGE 60)

TPS720105

P5V_3V3_SUS_EN

P3V3S3_EN

PP5V_SUS_FET

Q7840

U4900

(6 TO 8.4V)

2S3P

J6950

SMC Q7801

PPDDR_S3_REG

CPUIMVP_PGOOD

CPUVCCIOS0_PGOOD

R7510

SMC_GFX_ISENSE

D6905

U6990

3.425V G3HOT

LT3470A

(PAGE 52)

PP3V42_G3H_REG

ENABLE2

ENABLE

V

PBUS SUPPLY/

(PAGE 53)

U7090

SMC_RESET_L

VIN

PP5V5_CHRG_VDDP

SMC_BATT_ISENSE

LCD_BKLT_EN

PGOOD

PP5V_S0_FET

PP5V_S0_VMON

PP1V5_S3RS0_VMON

PP1V05_S0_VMON

16

PPVOUT_SW_LCDBKLT

PP3V3_S0_SSD_R

SMC_SYS_KBDLED

VOUT2PPVTT_S0_DDR_LDO

VLDOIN

PGOODG

PGOOD

(PAGE 57)

VR_ON

R0954

VOUT A

TPS22920

(PAGE 36)

PPVCORE_S0_AXG_REG

25-1

CPUIMVP_AXG_PGOOD

PPBUS_G3H

F7040

VOUT

LT3470A

(PAGE 53)

1

EN/UVLO

ISL6259HRTZ

U7000

F6901

CHGR_BGATE

BATTERY CHARGER

(PAGE 41)

(PAGE 16~21)

PM_PCH_PWRGD

U1800

1V05_S0_LDO_EN

RSMRST_OUT(P15)

PM_SLP_S3_L

TBT_PWR_EN

26

J6900

R7020

SMC_DCIN_ISENSE 1

PP5V5_CHAR_VDDP

PPDCIN_G3H_OR_PBUS

SMC_GFX_VSENSE

D7005

1

PPVBAT_G3H_CHRG_RET

R7050

A

ADAPTER

AC

A

Revision HistorySYNC_DATE=11/18/2011

051-9276

2.7.0

3 OF 109

3 OF 72

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

Apple Inc.


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TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

BOM OPTIONSBOM NAMEBOM NUMBERTABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM



TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

BOM Variants Bar Code Labels / EEEE #’s

Sub-BOMs

EEEE:F27H[EEEE_F27H]1825-7670 CRITICALLABEL,TEXT,MLB,K21/K78

EEEE:F27J[EEEE_F27J]1825-7670 CRITICALLABEL,TEXT,MLB,K21/K78

EEEE:F27K[EEEE_F27K]1825-7670 CRITICALLABEL,TEXT,MLB,K21/K78

EEEE:F27G[EEEE_F27G]LABEL,TEXT,MLB,K21/K78 CRITICAL825-7670 1

EEEE:F27C[EEEE_F27C]1825-7670 CRITICALLABEL,TEXT,MLB,K21/K78

EEEE:F27D[EEEE_F27D]1825-7670 CRITICALLABEL,TEXT,MLB,K21/K78

EEEE:F27F[EEEE_F27F]LABEL,TEXT,MLB,K21/K78 CRITICAL825-7670 1

EEEE:F279[EEEE_F279]1825-7670 CRITICALLABEL,TEXT,MLB,K21/K78

J11_CMNPTS,CPU:1.7GHZ,EEEE:DYKG,DDR3:HYNIX_8GB639-3474 PCBA,MLB,1.7GHZ,HY 8GB,J11

639-3776 PCBA,MLB,2.0GHZ,HY 4GB,J11 J11_CMNPTS,CPU:2.0GHZ,EEEE:F27K,DDR3:HYNIX_4GB

J11 MLB DEVELOPMENT BOM J11_DEVEL:ENG085-3937

CMN PTS,PCBA,MLB,J11607-9089 J11_COMMON

EEEE:F0V4[EEEE_F0V4]1825-7670 CRITICALLABEL,TEXT,MLB,K21/K78

825-7670 LABEL,TEXT,MLB,K21/K78 CRITICAL1 [EEEE_DYKL] EEEE:DYKL

LABEL,TEXT,MLB,K21/K78 CRITICAL825-7670 1 [EEEE_DYKH] EEEE:DYKH

EEEE:DYKK[EEEE_DYKK]1825-7670 CRITICALLABEL,TEXT,MLB,K21/K78

EEEE:DYKG[EEEE_DYKG]LABEL,TEXT,MLB,K21/K78 CRITICAL825-7670 1

EEEE:F0V3[EEEE_F0V3]LABEL,TEXT,MLB,K21/K78 CRITICAL825-7670 1

EEEE:DYKF[EEEE_DYKF]1825-7670 CRITICALLABEL,TEXT,MLB,K21/K78

EEEE:DYKJ[EEEE_DYKJ]1825-7670 CRITICALLABEL,TEXT,MLB,K21/K78

CRITICALDEVEL1 DEVEL_BOM085-3937 J11 MLB DEVELOPMENT BOM

CMNPTS1 CRITICAL607-9089 CMN PTS,PCBA,MLB,J11 J11_CMNPTS

J11_CMNPTS,CPU:1.7GHZ,EEEE:F0V4,DDR3:ELPIDA_8GBPCBA,MLB,1.7GHZ,EL 8GB,J11639-3660

J11_CMNPTS,CPU:1.7GHZ,EEEE:F27D,DDR3:SAMSUNG_8GBPCBA,MLB,1.7GHZ,SA 8GB,J11639-3774

J11_CMNPTS,CPU:1.7GHZ,EEEE:F27J,DDR3:ELPIDA_4GBPCBA,MLB,1.7GHZ,EL 4GB,J11639-3775

J11_CMNPTS,CPU:1.7GHZ,EEEE:DYKF,DDR3:SAMSUNG_4GB639-3472 PCBA,MLB,1.7GHZ,SA 4GB,J11

PCBA,MLB,1.7GHZ,HY 4GB,J11639-3471 J11_CMNPTS,CPU:1.7GHZ,EEEE:DYKK,DDR3:HYNIX_4GB

639-3778 PCBA,MLB,2.0GHZ,SA 4GB,J11 J11_CMNPTS,CPU:2.0GHZ,EEEE:F27G,DDR3:SAMSUNG_4GB

J11_CMNPTS,CPU:2.0GHZ,EEEE:F27H,DDR3:ELPIDA_4GB639-3780 PCBA,MLB,2.0GHZ,EL 4GB,J11

J11_CMNPTS,CPU:2.0GHZ,EEEE:F27C,DDR3:HYNIX_8GB639-3777 PCBA,MLB,2.0GHZ,HY 8GB,J11

J11_CMNPTS,CPU:2.0GHZ,EEEE:F27F,DDR3:SAMSUNG_8GB639-3779 PCBA,MLB,2.0GHZ,SA 8GB,J11

J11_CMNPTS,CPU:2.0GHZ,EEEE:F279,DDR3:ELPIDA_8GB639-3781 PCBA,MLB,2.0GHZ,EL 8GB,J11

J11_CMNPTS,CPU:1.5GHZ,EEEE:F0V3,DDR3:ELPIDA_8GBPCBA,MLB,1.5GHZ,EL 8GB,J11639-3659

PCBA,MLB,1.5GHZ,SA 4GB,J11 J11_CMNPTS,CPU:1.5GHZ,EEEE:DYKH,DDR3:SAMSUNG_4GB639-3470

PCBA,MLB,1.5GHZ,HY 8GB,J11 J11_CMNPTS,CPU:1.5GHZ,EEEE:DYKJ,DDR3:HYNIX_8GB639-3473

K78 BOM Variants

SYNC_DATE=11/16/2010SYNC_MASTER=K21_MLB

J11_CMNPTS,CPU:1.5GHZ,EEEE:DYKL,DDR3:HYNIX_4GBPCBA,MLB,1.5GHZ,HY 4GB,J11639-3469

939-0479 PCBA,MLB,1.9GHZ,HY 4GB,J11 J11_CMNPTS,CPU:1.9GHZ,EEEE:DYKL,DDR3:HYNIX_4GB

051-9276

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4 OF 109

4 OF 72


TABLE_BOMGROUP_ITEM

PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:

TABLE_ALT_HEAD

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

BOM OPTIONSBOM GROUPTABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM


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Programmable Parts

J11 BOM GROUPSModule Parts

SIZE

0

1

CFG 3

0

0

1

1

A

B

CFG 0

0

1

CFG 1

0

1

CFG 2

1

0

HYNIX

VENDOR

SAMSUNG

ELPIDA

MICRON

4GB

8GB

DIE REV

DRAM CFG CHART

Alternate Parts

PD Module Parts

CPU:2.0GHZTDP1 CRITICALU1000337S4296 IVB,QC9B,QS,L1,2.0,17W,2+2,1.15,4M,ULVBG

IVB,QC9B,QS,L1,2.0,17W,2+2,1.15,4M,ULVBG337S4296 CPU:2.0GHZU1000 CRITICAL1

CPU:1.7GHZTDPU1000 CRITICAL1337S4299 IVB,QC9E,QS,L1,1.7,17W,2+2,1.05,3M,ULVBG

IVB,QC9E,QS,L1,1.7,17W,2+2,1.05,3M,ULVBG337S4299 1 CRITICALU1000 CPU:1.7GHZ

U3200,U3210,U3220,U3230 CRITICAL4333S0629 DRAM_TYPE:ELPIDA_8GBIC,SDRAM,4GBIT,DDR3L-1600,REV B,78P FBGA

U3100,U3110,U3120,U3130 CRITICAL4333S0629 DRAM_TYPE:ELPIDA_8GBIC,SDRAM,4GBIT,DDR3L-1600,REV B,78P FGBA


U3200,U3210,U3220,U3230 CRITICAL4 DRAM_TYPE:ELPIDA_4GB333S0628 IC,SDRAM,2GBIT,DDR3L-1600,REV D,78P FBGA


U3100,U3110,U3120,U3130 CRITICAL4 DRAM_TYPE:ELPIDA_4GB333S0628 IC,SDRAM,2GBIT,DDR3L-1600,REV D,78P FGBA

U3000,U3010,U3020,U30304 CRITICAL DRAM_TYPE:ELPIDA_4GB333S0628 IC,SDRAM,2GBIT,DDR3L-1600,REV D,78P FBGA

U2900,U2910,U2920,U29304 CRITICAL DRAM_TYPE:ELPIDA_4GB333S0628 IC,SDRAM,2GBIT,DDR3L-1600,REV D,78P FBGA

4 CRITICAL DRAM_TYPE:SAMSUNG_8GBIC,SDRAM,4GBIT,DDR3-1600,C-DIE,78P FBGA U3200,U3210,U3220,U3230333S0642

4 CRITICALU2900,U2910,U2920,U2930 DRAM_TYPE:SAMSUNG_8GBIC,SDRAM,4GBIT,DDR3-1600,C-DIE,78P FBGA333S0642

4 CRITICALU3000,U3010,U3020,U3030 DRAM_TYPE:SAMSUNG_8GBIC,SDRAM,4GBIT,DDR3-1600,C-DIE,78P FBGA333S0642

CRITICAL4 DRAM_TYPE:SAMSUNG_8GBIC,SDRAM,4GBIT,DDR3-1600,C-DIE,78P FGBA U3100,U3110,U3120,U3130333S0642

4 CRITICALU3200,U3210,U3220,U3230 DRAM_TYPE:SAMSUNG_4GB333S0623 IC,SDRAM,2GBIT,DDR3-1600,D35,78P FBGA

DRAM_TYPE:SAMSUNG_4GBCRITICAL4 U3100,U3110,U3120,U3130333S0623 IC,SDRAM,2GBIT,DDR3-1600,D35,78P FGBA

DRAM_TYPE:SAMSUNG_4GB4 CRITICALU3000,U3010,U3020,U3030333S0623 IC,SDRAM,2GBIT,DDR3-1600,D35,78P FBGA

4 CRITICALU2900,U2910,U2920,U2930 DRAM_TYPE:SAMSUNG_4GB333S0623 IC,SDRAM,2GBIT,DDR3-1600,D35,78P FBGA

U3100,U3110,U3120,U3130 CRITICAL DRAM_TYPE:HYNIX_8GB4333S0625 IC,SDRAM,4GBIT,512MX8,DDR3-1600,82 FGBA

U3200,U3210,U3220,U3230 DRAM_TYPE:HYNIX_8GB4 CRITICAL333S0625 IC,SDRAM,4GBIT,512MX8,DDR3-1600,82 FBGA

DRAM_TYPE:HYNIX_8GB4 U3000,U3010,U3020,U3030 CRITICAL333S0625 IC,SDRAM,4GBIT,512MX8,DDR3-1600,82 FBGA

IC,SDRAM,2GBIT,DDR3L-1600,GEMMA,78P FPGA U3200,U3210,U3220,U3230 DRAM_TYPE:HYNIX_4GBCRITICAL333S0622 4

U3100,U3110,U3120,U3130 CRITICAL DRAM_TYPE:HYNIX_4GBIC,SDRAM,2GBIT,DDR3L-1600,GEMMA,78P FPGA4333S0622

CRITICAL DRAM_TYPE:HYNIX_8GBU2900,U2910,U2920,U29304333S0625 IC,SDRAM,4GBIT,512MX8,DDR3-1600,82 FBGA

DRAM_TYPE:HYNIX_4GB4 CRITICALU3000,U3010,U3020,U3030IC,SDRAM,2GBIT,DDR3L-1600,GEMMA,78P FPGA333S0622

DRAM_TYPE:HYNIX_4GBCRITICALU2900,U2910,U2920,U2930IC,SDRAM,2GBIT,DDR3L-1600,GEMMA,78P FPGA4333S0622

CPU:1.9GHZIVB,QC9C,QS,L1,1.9,17W,2+2,1.15,4M,ULVBG337S4297 1 CRITICALU1000

IC,TBT,CR-4C,LP,ES3,288 FCBGA,12X12MM338S1108 U3600 TBT1 CRITICAL

PCH_C1TDPIC,PCH,PPT-MB,QS77,C1,QS337S4275 U1800 CRITICAL1

IC,PCH,PPT-MB,SFF,ES2,B0337S4180 1 CRITICALU1800 PCH_ES2

PCH_C0IC,PCH,PPT-MB,SFF,P-QS,C0337S4235 1 CRITICALU1800

PCH_C1IC,PCH,PPT-MB,QS77,C1,QS337S4275 1 CRITICALU1800

1337S4165 IC,PCH,PPT-MB,SFF,ES1 U1800 CRITICAL PCH_ES1

CAN,TBT,J11/J13806-3142 1 CRITICALTBTFENCE

TBTCOVERCAN,COVER,TBT,J11/J13806-3215 CRITICAL1

1 CRITICALMDPCAN806-3216 CAN,MDP,J11/J13

TBTTOPSIDE_1P1 CRITICAL806-3214 CAN,TOPSIDE,J11/J13

1 CRITICAL806-3083 USBCANSHLD,USB,MLB,J11/J13

TBTTOPSIDE_2P_FENCECAN,TOPSIDE,FENCE,ALT,J11/J13806-3705 1 CRITICAL

TBTTOPSIDE_2P_COVERCAN,TOPSIDE,COVER,ALT,J11/J13806-3706 CRITICAL1

MLB,DYMAX UV EB 0.22 GRAM,K781 CRITICALGLUE946-3116

IC,ISL6259,BATCHARGER,3%,4C4MM,QFN28353S2929 1 CRITICALU7000

ASSEMBLY,SUBASSY,PCBA,HALL EFFECT,K99607-6811 J6955 CRITICAL1

SYNC_MASTER=J11_MLB_NON_POR

BOM Configuration

SYNC_DATE=11/09/2011

IVB,QBP8,ES2,K0,1.5,17W,2+2,0.95,4M,ULVB337S4197 U1000 CPU:1.5GHZCRITICAL1

ALTERNATE,BKLT:ENG,XDP_CONN,XDP_PCH,DDRVREF_DAC,VREFDQ:M1_M3,VREFCA:LDO_DAC,S0PGOOD_ISL,S3_S0_LED,VCCIOISNS_ENG,AIRPORTISNS_ENG,HDDISNS_ENG,LCDBKLTISNS_ENGJ11_DEVEL:ENG

J11_PROGPARTS BOOTROM_PROG,SMC_PROG,TBTROM:PROG

J11_DEBUG:ENG DEVEL_BOM,MOJO:YES,XDP,XDP_CPU:BPM,LPCPLUS

BKLT:PROD,MOJO:YES,XDP,LPCPLUS,VREFDQ:LDO,VREFCA:LDO,XDP_CPU:BPM,VCCIOISNS_PROD,AIRPORTISNS_PROD,HDDISNS_PROD,LCDBKLTISNS_PRODJ11_DEBUG:PROD

RAMCFG0:L,RAMCFG1:L,RAMCFG2:H,RAMCFG3:L,DRAM_TYPE:HYNIX_8GBDDR3:HYNIX_8GB

RAMCFG0:L,RAMCFG1:H,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:SAMSUNG_4GBDDR3:SAMSUNG_4GB

RAMCFG0:L,RAMCFG1:H,RAMCFG2:H,RAMCFG3:L,DRAM_TYPE:SAMSUNG_8GBDDR3:SAMSUNG_8GB

Diodes alt to ToshibaALL376S0613376S0855

ALL Toko alt to NEC inductor152S1462 152S1295

152S1300 ALL Coilcraft MA5274 alt to Murata152S1493

152S1085 ALL152S1307 Toko alt to Cyntec

IVB,QBTP,ES2,K0,1.5,17W,2+2,0.95,4M,ULVBGA CPU:1.5GHZTDP337S4198 1 U1000 CRITICAL

DEVEL_BOM,BKLT:PROD,MOJO:YES,XDP,LPCPLUS,VREFDQ:LDO,VREFCA:LDO,XDP_CPU:BPM,VCCIOISNS_PROD,AIRPORTISNS_PROD,HDDISNS_PROD,LCDBKLTISNS_PRODJ11_DEBUG:PVT

RAMCFG0:L,RAMCFG1:L,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:HYNIX_4GBDDR3:HYNIX_4GB

HUB_3NONREM,TBT,MPM5:YES,CPUMEM_SLG:NO,PP5V5_DCIN:NO,TPAD_PCH:NO,SKIP_5V3V3:INAUDIBLE,BTPWR:S4,TBTHV:P15V,LVDDR3_HW:YES,AXG_ACOUSTICS:NOJ11_MISC

ALTERNATE,COMMON,J11_MISC,J11_DEBUG:ENG,J11_PROGPARTS,USBHUB2513B,EDP:YES,PCH_C1J11_COMMON

XDP_CONNJ11_DEVEL:PVT

376S0612376S0972 ALL Rohm alt to Toshiba

Diodes alt to Toshiba376S0977 ALL376S0859

371S0709 NXP alt to NXPALL371S0652

138S0691138S0676 Murata alt to SamsungALL

138S0671 138S0673 Taiyo alt to MurataALL

ALL Intersil alt to OPA2333353S3238 353S1428

Dale/Vishay alt to CyntecALL152S0586 152S1301

138S0703 138S0648 ALL Murata alt to Taiyo Yuden

138S0684 138S0660 Murata alt to Taiyo YudenALL

ALL372S0186 372S0185 NXP alt to Diodes

371S0558 ALL371S0713 Diodes alt to ST Micro

ALL376S0903 376S0796 Fairchild alt to Siliconix

Diodes alt to Toshiba376S0613376S0855 ALL

197S0431 200uW Epson alt to NDK197S0432 ALL

Diodes alt to Fairchild376S0604376S1053 ALL

998-4435 ALL128S0333 Sanyo alt to Kemet

Sanyo High Voltage Polymer alt128S0357 998-4435 ALL

Kemet Rectangular Design alt998-4715 998-4435 ALL

Kemet Flute Design alt998-4716 ALL998-4435

DDR3:ELPIDA_4GB RAMCFG0:H,RAMCFG1:H,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:ELPIDA_4GB

CRITICAL1335S0809 BOOTROM_BLANKU610064 MBIT SPI SERIAL DUAL I/O FLASH,8X6X0.8

64 MBIT SPI SERIAL DUAL I/O FLASH,8X6X0.8335S0803 BOOTROM_BLANK1 U6100 CRITICAL

IC,EFI ROM,PIB,J11/J13341S3527 BOOTROM_PROG1 CRITICALU6100

IC,SMC,PIB,J11341S3434 SMC_PROGCRITICALU49001

DDR3:ELPIDA_8GB RAMCFG0:H,RAMCFG1:H,RAMCFG2:H,RAMCFG3:L,DRAM_TYPE:ELPIDA_8GB

338S1098 IC,SMC12-A3,40MHZ/50DMIPS MCU,9X9,157BGA U49001 SMC_BLANKCRITICAL

341S3526 IC,EEPROM,Cactus Ridge (V1.2) PIB, J11/J131 CRITICAL TBTROM:PROGU3690

335S0865 1 CRITICALU3690 TBTROM:BLANKEEPROM,256KBIT,SPI,5MHZ,1.8V,2X3QFN

051-9276

2.7.0

5 OF 109

5 OF 72

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FUNC_TEST

(Need 4 TPs)

FUNC_TEST

(Need 2 TPs)

(Need 2 TPs)

FUNC_TEST

(Need to add 1 GND TP)

FUNC_TEST

J5600: Fan Connector

FUNC_TEST

FUNC_TEST

J5700: IPD Flex Connector

(Need 5 TPs)

(Need 4 TPs)

(Need 6 TPs)

(Need 3 TPs)

FUNC_TEST

FUNC_TEST

(Need to add 5 GND TPs)


NO_TEST

J5715: KB BKLT ConnectorFUNC_TEST


FUNC_TEST

POWER SIGNALS

NO_TEST Nets

Misc Voltages & Control SignalsFUNC_TEST


Functional Test Points

J4001: AirPort / BT Connector

J5100: LPC+SPI Connector


J4700: LIO Connector(Need to add 4 GND TPs near

J6955: HALL EFFECT Connector


J9000: Internal DP Connector

J6950 and 1 for shield)


J6900: DC-In Connector


FUNC_TEST

J6950: Battery Connector


J6903: Speaker Connector

FUNC_TEST


J4501: SATA SSD Connector

I641

I642

I643

I644

Functional Test / No Test

SYNC_MASTER=(K99_MLB) SYNC_DATE=(02/16/2010)

TRUE =I2C_MIKEY_SDA

HDA_SDOUTTRUE

SMC_OOB1_RX_LTRUE

TRUE SATA_SSD_D2R_NTRUE SATA_SSD_D2R_P

TRUE PCIE_SSD_D2R_N<1>

PCIE_SSD_D2R_P<1>TRUE

TRUE PCIE_SSD_R2D_N<1>

TRUE PCIE_SSD_R2D_P<1>

TRUE PCIE_CLK100M_SSD_N

TRUE SATA_SSD_R2D_PTRUE SATA_SSD_R2D_N

PCIE_AP_R2D_PTRUE

TRUE PCIE_CLK100M_AP_N

TRUE USB_BT_CONN_P

USB_BT_CONN_NTRUE

PCIE_AP_D2R_NTRUE

AP_CLKREQ_Q_LTRUE

PP3V3_S3RS4_BT_FTRUE

AP_RESET_CONN_LTRUE

PCIE_WAKE_LTRUE

PCIE_AP_D2R_PTRUE

TRUE PCIE_CLK100M_AP_P

TRUE PP3V3_WLAN_F

WIFI_EVENT_LTRUE

TRUE SPKRAMP_ROUT_P

TRUE PPVBAT_G3H_CONN

TRUE USB_TPAD_NTRUE USB_TPAD_PTRUE PP3V3_TPAD_CONN

PP5V_TPAD_FILTTRUE

TRUE =PP3V42_G3H_TPAD

TRUE =SMBUS_BATT_SDA

TRUE PPVOUT_SW_LCDBKLT

LED_RETURN_6TRUE

TRUE LED_RETURN_4

TRUE DP_INT_HPD_CONN

DP_INT_ML_F_P<0>TRUE

TRUE I2C_TCON_SCL_R

TRUE =PP3V42_G3H_HALL

TRUE DP_INT_AUX_CH_C_P

LED_RETURN_3TRUE

LED_RETURN_5TRUE

TRUE I2C_TCON_SDA_R

PP3V3_SW_LCDTRUE

TRUE =SMBUS_BATT_SCL

TRUE SYS_DETECT_L

TRUE PCIE_CLK100M_SSD_P

TRUE SMC_BC_ACOK

TRUE =USB_PWR_EN

TRUE =PP3V3R1V5_S0_AUDIO

TRUE =PP3V42_G3H_ONEWIRE

TRUE USB_CAMERA_P

TRUE HDA_BIT_CLK

USB_EXTB_OC_LTRUE

HDA_RST_LTRUE

TRUE HDA_SYNC

TRUE USB3_EXTB_RX_RC_N

TRUE USB3_EXTB_RX_RC_P

TRUE USB3_EXTB_TX_C_P

TRUE USB3_EXTB_TX_C_N

TRUE =PP3V3_S5_LPCPLUS

TRUE =PP5V_S0_LPCPLUS

TRUE LPC_AD<3..0>

TRUE USB_EXTB_N

TRUE SPKRAMP_INR_N

TRUE =I2C_LIO_SDA

TRUE AUD_IPHS_SWITCH_EN

TRUE AUD_I2C_INT_L

TRUE AUD_GPIO_3

TRUE SPKRAMP_INR_P

TRUE USB_CAMERA_N

HDA_SDIN0TRUE

TRUE =PP3V3_S0_AUDIO

TRUE USB_EXTB_P

TRUE AUD_IP_PERIPHERAL_DET

TRUE =I2C_MIKEY_SCL

TRUE SYS_ONEWIRE

SSD_RESET_LTRUE

TRUE PP3V3_S5

TRUE PP1V8_S0

NC_PCIE_CLK100M_PE4NTRUEMAKE_BASE=TRUE

MAKE_BASE=TRUENC_PEG_D2RN<15..2>

TRUE

TRUE PP1V5_S3

TRUE PP15V_TBT

TRUE PPVCORE_S0_AXG

PP1V05_S0_CPU_VCCPQETRUE

PP1V05_TBTCIOTRUE

PPBUS_S5_HS_OTHER_ISNSTRUE

TRUE PPVRTC_G3H

TRUE PPVCCSA_S0_CPU

TRUE PP1V05_SUS

PPVTTDDR_S3TRUE

TRUE PP1V05_S0

TRUE PP0V75_S0_DDRVTT

PP3V3_TBTLCTRUE

TP_PCIE_CLK100M_PE5N

TP_PCIE_CLK100M_PE4P


TP_SATA_B_R2D_CN

PP5V_S0TRUE

PP3V3_S4TRUE

PPDCIN_G3H_ISOLTRUE

PP5V_S3TRUE

PP1V8_S0_CPU_VCCPLL_RTRUE

PP1V5_S3_CPU_VCCDQTRUE

TRUE PPVCORE_S0_CPU

PP1V05_S0_PCH_VCCADPLLTRUE

TRUE PP1V05_TBTLC

TRUE PP1V5_S0TRUE PP1V5_S3RS0

TRUE PP3V3_S0

TRUE PP3V3_S3TRUE PP3V3_SUS

TRUE PP5V_S5

TRUE PP5V_SUS

TRUE PPDCIN_G3H

TRUE PP3V42_G3H

TRUE PPVIN_SW_TBTBST

TRUE PPBUS_S5_HS_COMPUTING_ISNS

TRUE PPBUS_G3H

VCCSAS0_SET1TRUE

VCCSAS0_SREFTRUE

VCCSAS0_SET1_RTRUE

VCCSAS0_SET0TRUE

NC_PEG_R2D_CN<15..2>MAKE_BASE=TRUE

TRUE

SMC_BS_ALRT_L TRUE NC_SMC_BS_ALRT_LMAKE_BASE=TRUE

TP_LVDS_IG_B_CLKP NC_LVDS_IG_B_CLKP

MAKE_BASE=TRUE

TRUE

TP_LVDS_IG_BKL_PWM NC_LVDS_IG_BKL_PWMMAKE_BASE=TRUE

TRUE

TP_LVDS_IG_B_CLKN TRUE NC_LVDS_IG_B_CLKNMAKE_BASE=TRUE

SMC_LID_RTRUE

TRUE KBDLED_ANODETRUE KBDLED_FB

TP_PCI_CLK33M_OUT3 TRUEMAKE_BASE=TRUE

NC_PCI_CLK33M_OUT3

TP_PCI_PME_L TRUE

MAKE_BASE=TRUE

NC_PCI_PME_L

TP_HDA_SDIN2 TRUEMAKE_BASE=TRUE

NC_HDA_SDIN2

TP_HDA_SDIN3MAKE_BASE=TRUETRUE NC_HDA_SDIN3

TP_HDA_SDIN1 TRUE

MAKE_BASE=TRUE

NC_HDA_SDIN1

TP_PCIE_CLK100M_PEBP TRUEMAKE_BASE=TRUE

NC_PCIE_CLK100M_PEBP

TP_PCIE_CLK100M_PEBN TRUEMAKE_BASE=TRUE

NC_PCIE_CLK100M_PEBN

TP_CLINK_RESET_L NC_CLINK_RESET_LTRUEMAKE_BASE=TRUE

TP_CLINK_CLKMAKE_BASE=TRUETRUE NC_CLINK_CLK

TP_CLINK_DATAMAKE_BASE=TRUE

TRUE NC_CLINK_DATA

TP_PCH_LVDS_VBG NC_PCH_LVDS_VBGMAKE_BASE=TRUETRUE

TP_LVDS_IG_CTRL_CLK NC_LVDS_IG_CTRL_CLKMAKE_BASE=TRUETRUE

TP_LVDS_IG_CTRL_DATA NC_LVDS_IG_CTRL_DATAMAKE_BASE=TRUETRUE

TP_CRT_IG_VSYNCMAKE_BASE=TRUE

NC_CRT_IG_VSYNCTRUE

TP_CRT_IG_HSYNC NC_CRT_IG_HSYNCTRUEMAKE_BASE=TRUE

TP_CRT_IG_DDC_DATA NC_CRT_IG_DDC_DATAMAKE_BASE=TRUE

TRUE

TP_CRT_IG_RED TRUE

MAKE_BASE=TRUE

NC_CRT_IG_RED

TP_CRT_IG_DDC_CLK TRUEMAKE_BASE=TRUE

NC_CRT_IG_DDC_CLK

TP_CRT_IG_BLUE NC_CRT_IG_BLUEMAKE_BASE=TRUETRUE

TP_CRT_IG_GREEN NC_CRT_IG_GREENTRUEMAKE_BASE=TRUE

TRUE LPCPLUS_GPIOTRUE SMC_RX_L

SMC_ROMBOOTTRUE

TRUE SMC_RESET_LTRUE SMC_TCKTRUE SMC_TDITRUE LPC_PWRDWN_LTRUE LPC_SERIRQTRUE SPI_ALT_CS_LTRUE SPI_ALT_CLKTRUE SPIROM_USE_MLBTRUE LPC_CLK33M_LPCPLUSTRUE SMC_TX_L

TP_SMC_MD1TRUE

TP_SMC_TRST_LTRUE

TRUE SMC_TDOTRUE LPCPLUS_RESET_LTRUE SMC_TMSTRUE PM_CLKRUN_LTRUE LPC_FRAME_LTRUE SPI_ALT_MISOTRUE SPI_ALT_MOSI

TRUE PCIE_AP_R2D_N

TRUE =I2C_LIO_SCL

TRUE SSD_P3V3S0_EN

SATA_PCIE_SELTRUE

SSD_CLKREQ_LTRUE

TRUE SMC_OOB1_TX_L

TP_PCH_TP1

TP_PCH_TP4

TP_PCH_TP9

TRUE NC_PCH_TP16MAKE_BASE=TRUE

NC_PCH_TP17TRUEMAKE_BASE=TRUE


TP_SATA_F_D2RN

=PP18V5_DCIN_CONNTRUE

TRUE =PP5V_S3_LIO_CONN

TP_SATA_B_R2D_CP

TP_SATA_E_D2RN

TRUE

MAKE_BASE=TRUE

NC_SATA_E_D2RP

MAKE_BASE=TRUETRUE NC_SATA_E_R2D_CN

MAKE_BASE=TRUETRUE NC_SATA_E_R2D_CP

TRUEMAKE_BASE=TRUE

NC_SATA_F_D2RN

NC_SATA_F_D2RPMAKE_BASE=TRUE

TRUE

NC_SATA_F_R2D_CNMAKE_BASE=TRUETRUE

NC_SATA_F_R2D_CPMAKE_BASE=TRUE

TRUE


TRUE SMC_LID

=I2C_TPAD_SDATRUE

TRUE LED_RETURN_1

DP_INT_ML_F_N<0>TRUE

TRUE DP_INT_AUX_CH_C_N

TRUE SMC_TPAD_RST_L

TRUE =I2C_TPAD_SCL

TRUE SPKRAMP_ROUT_N

=PP5V_S0_FANTRUE

SMC_PME_S4_WAKE_LTRUE

FAN_RT_PWMTRUE

TRUE PP3V3_S0_SSD_FLT

NC_SDVO_INTNMAKE_BASE=TRUE

TRUE

NC_SDVO_TVCLKINNMAKE_BASE=TRUE

TRUE

NC_SDVO_TVCLKINPTRUEMAKE_BASE=TRUE

NC_SDVO_INTPTRUEMAKE_BASE=TRUE

NC_SDVO_STALLNMAKE_BASE=TRUETRUE

NC_SDVO_STALLPTRUE

MAKE_BASE=TRUE

NC_TP_XDP_PCH_OBSFN_D<0..1>MAKE_BASE=TRUETRUE

NC_TP_XDPPCH_HOOK3MAKE_BASE=TRUETRUE

NC_TP_XDP_PCH_OBSFN_B<0..1>TRUE

MAKE_BASE=TRUENC_TP_XDPPCH_HOOK2TRUE

MAKE_BASE=TRUE

NC_TP_XDP_PCH_OBSFN_A<0..1>TRUEMAKE_BASE=TRUE

TRUEMAKE_BASE=TRUE

NC_TP_XDP_PCH_HOOK4

TRUE

MAKE_BASE=TRUE

NC_TP_XDP_PCH_HOOK5

NC_PCH_GPIO64_CLKOUTFLEX0TRUE

MAKE_BASE=TRUENC_PCH_GPIO65_CLKOUTFLEX1TRUE

MAKE_BASE=TRUENC_PCH_GPIO66_CLKOUTFLEX2

MAKE_BASE=TRUETRUE

NC_PCH_GPIO67_CLKOUTFLEX3MAKE_BASE=TRUE

TRUE

TRUEMAKE_BASE=TRUE

NC_PCH_TP1

NC_PCH_TP2MAKE_BASE=TRUETRUE

TRUEMAKE_BASE=TRUE

NC_PCH_TP3




NC_PCH_TP7MAKE_BASE=TRUETRUE


MAKE_BASE=TRUETRUE NC_PCH_TP9



MAKE_BASE=TRUETRUE NC_PCH_TP13



TRUEMAKE_BASE=TRUE

NC_SATA_E_D2RN

NC_SATA_D_D2RPTRUE

MAKE_BASE=TRUE

NC_SATA_D_D2RNTRUEMAKE_BASE=TRUE

MAKE_BASE=TRUETRUE NC_SATA_D_R2D_CN

NC_SATA_D_R2D_CPMAKE_BASE=TRUE

TRUE

NC_SATA_B_R2D_CPMAKE_BASE=TRUE

TRUE

NC_SATA_B_D2RPTRUE

MAKE_BASE=TRUE

NC_SATA_B_D2RNTRUEMAKE_BASE=TRUE

TRUE NC_PSOC_P1_3MAKE_BASE=TRUE

MAKE_BASE=TRUETRUE NC_PCIE_CLK100M_PE7P

NC_SATA_B_R2D_CNMAKE_BASE=TRUETRUE

TRUEMAKE_BASE=TRUE

NC_PCIE_CLK100M_PE4P

TRUEMAKE_BASE=TRUE

NC_PCIE_CLK100M_PE5N

MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE7NTRUE

NC_PCIE_CLK100M_PE5PTRUE

MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE6PMAKE_BASE=TRUETRUE

TRUEMAKE_BASE=TRUE

NC_PCIE_CLK100M_PE6N

TRUEMAKE_BASE=TRUENC_CPU_RSVD<30..45>

NC_CPU_THERMDCMAKE_BASE=TRUE

TRUE

NC_EDP_TXN<0..3>MAKE_BASE=TRUE

TRUE

NC_EDP_AUXPMAKE_BASE=TRUE

TRUE

NC_EDP_TXP<0..3>MAKE_BASE=TRUE

TRUE

FAN_RT_TACHTRUE

SMC_ONOFF_LTRUE

TRUE LED_RETURN_2

TP_EDP_AUX_N

TP_CPU_THERMDC

TP_CPU_RSVD<30..45>

TP_CPU_RSVD<8..27>

=PEG_R2D_C_P<15..2>

=PEG_D2R_P<15..2>

=PEG_R2D_C_N<15..2>

=PEG_D2R_N<15..2>





TP_PSOC_P1_3

TP_SATA_B_D2RN

TP_SATA_B_D2RP

TP_SATA_D_R2D_CP

TP_SATA_D_R2D_CN

TP_SATA_D_D2RN

TP_SATA_D_D2RP

TP_SATA_F_R2D_CP

TP_SATA_F_R2D_CN

TP_SATA_E_R2D_CP

TP_SATA_F_D2RP

TP_SATA_E_R2D_CN

TP_SATA_E_D2RP

TP_PCH_TP17

TP_PCH_TP18

TP_PCH_TP16

TP_PCH_TP15

TP_PCH_TP14

TP_PCH_TP13

TP_PCH_TP12

TP_PCH_TP10

TP_PCH_TP8

TP_PCH_TP7

TP_PCH_TP6

TP_PCH_TP5

TP_PCH_TP3

TP_PCH_TP2

TP_PCH_GPIO65_CLKOUTFLEX1




TP_XDP_PCH_HOOK5

TP_XDP_PCH_HOOK4

TP_XDP_PCH_OBSFN_A<0..1>

TP_XDPPCH_HOOK2

TP_XDP_PCH_OBSFN_B<0..1>

TP_XDPPCH_HOOK3

TP_XDP_PCH_OBSFN_D<0..1>

TP_SDVO_STALLP

TP_SDVO_INTN

TP_SDVO_INTP

TP_SDVO_STALLN

TP_SDVO_TVCLKINN

TP_SDVO_TVCLKINP

NC_PEG_R2D_CP<15..2>MAKE_BASE=TRUE

TRUE

NC_PEG_D2RP<15..2>MAKE_BASE=TRUE

TRUE

TRUENC_CPU_THERMDAMAKE_BASE=TRUE

TP_EDP_TX_N<0..3>

TP_EDP_TX_P<0..3>

TP_EDP_AUX_P

TP_CPU_THERMDA

NC_CPU_RSVD<8..27>MAKE_BASE=TRUE

TRUE

NC_EDP_AUXNMAKE_BASE=TRUE

TRUE

051-9276

2.7.0

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9

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



"G3Hot" (Always-Present) Rails

1V05 S0 LDO

Chipset "VCore" Rails

TBT Rails (off when no cable)

? mA

5V Rails

1.8V/1.5V/1.2V/1.05V Rails

2A max supply

3.3V Rails

SYNC_MASTER=K91_MLB

Power Aliases


MAKE_BASE=TRUEVOLTAGE=3.3VMIN_LINE_WIDTH=0.5 MM

PP3V3_S0

MIN_NECK_WIDTH=0.20MM

=PP3V3_S0_PCH_STRAPS

=PP3V3_S0_SAISNS

=PP3V3_S0_SYSCLKGEN

=PP3V3_S0_BKLTISNS

=PP3V3_S0_IMVPISNS

=PP3V3_S0_XDP

=PP3V3_S0_P1V05S0LDO

=PP3V3_S0_3V3S0ISNS

=PP3V3_S0_TBTPWRCTL

=PP3V3_S0_P1V5S0

=PP3V3_S0_VMON

=PP3V3_S0_HDDISNS

=PP3V3_S0_SSD

=PP3V3_S0_SMC

=PP3V3_S0_SMBUS_SMC_B_S0

=PP3V3_S0_SMBUS_SMC_0_S0

=PP3V3_S0_SMBUS_PCH

=PP3V3_S0_SB_PM

=PP3V3_S0_RSTBUF

=PP3V3_S0_PWRCTL

=PP3V3_S0_PCH_VCCADAC

=PP3V3_S0_HS_OTHER_ISNS

=PP3V3_S0_PCH_VCC3_3

=PP3V3_S0_SATAMUX

=PP3V3_S0_PCH_GPIO

=PP3V3_S0_PCH

=PP3V3_S0_P1V8S0

=PP3V3_S0_FAN

=PP3V3_S0_P3V3TBTFET

=PP3V3_S0_FET

=PP3V3_S0_DP_DDC

=PP3V3_S0_CPU_VCCIO_SEL

=PP3V3_S0_CPUTHMSNS

=PP3V3_S0_HS_COMPUTING_ISNS

=PP3V3_S0_BKL_VDDIO

=PP3V3_S0_AUDIO

=PP3V3_S0_CPUVCCIOISNS

=PP3V3_S0_PCH_VCC3_3_CLK

=PPVCCIO_S0_XDP

=PPVCCIO_S0_SMC

=PP3V3_S3_1V5S3ISNS

=PP3V3_S3_BT

=PP3V3_SUS_PCH_VCCSUS_USB

MIN_LINE_WIDTH=0.50MMMAKE_BASE=TRUEVOLTAGE=3.3V

PP3V3_SUS


=PPVCORE_S0_CPU_REG

=PPVCORE_S0_AXG_REG

PP1V8_S0_CPU_VCCPLL_R

MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUEVOLTAGE=1.8V

MIN_LINE_WIDTH=0.6 MM

=PP3V3_SUS_PWRCTL

=PP3V3_S5_PCHPWRGD

=PP3V3_S3_SMBUS_SMC_MGMT

=PP3V3_S3_WLANISNS

=PP3V3_S3_PCH_GPIO

=PP3V3_S3_DBGLEDS

VOLTAGE=18.5VMAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25 MMMIN_LINE_WIDTH=0.6 MMPPDCIN_G3H

=PP3V3_S3_WLAN

=PP3V3_S3_MEMRESET

=PPBUS_G3H

=PP3V3_S3_SMBUS_SMC_A_S3

=PP3V3_SUS_ROM

=PP3V3_S4_SMC

=PP3V3_S3_USBMUX

=PP3V3_S3_USB_HUB

=PP3V3_S3_FET

=PP3V3_S4_TBTAPWR

=PP3V3_SUS_PCH_VCC_SPI

=PP3V3_SUS_P1V05SUSLDO

=PP3V3_SUS_PCH_GPIO

=PP3V3_SUS_PCH

=PP3V3_SUS_PCH_VCCSUS

=PP3V3_SUS_FET

=PP1V5_S3RS0_FET


PP1V5_S3RS0



=PP1V5_S3_CPU_VCCDDR

=PP1V5_S3RS0_VMON

=PP3V3R1V5_S0_PCH_VCCSUSHDA

MAKE_BASE=TRUE

MIN_LINE_WIDTH=2 mmMIN_NECK_WIDTH=0.17 mm

PP1V5_S0

VOLTAGE=1.5V

=PP3V3R1V5_S0_AUDIO

=PP0V75_S0_MEM_VTT_B

=PP0V75_S0_MEM_VTT_A

=PP1V05_S0_PCH_VCCSSC

=PP1V05_S0_PCH_V_PROC_IO

=PPDDR_S3_REG

=PP3V3_S0_P3V3S0FET

=PPVIN_S0_CPUVCCIOS0

=PP5V_S5_LDO

=PP5V_S5_P1V5DDRFET

=PP5V_S5_P5VSUSFET

=PP5V_S5_TPAD

=PPVTT_S3_DDR_BUF

MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mmPP5V_S5

VOLTAGE=5VMAKE_BASE=TRUE

MIN_LINE_WIDTH=0.2 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=0.75V

PPVTTDDR_S3

MAKE_BASE=TRUE

=PP3V42_G3H_ONEWIRE

=PP1V05_SUS_LDO



MIN_LINE_WIDTH=0.4 MMPP1V05_S0_PCH_VCCADPLL

=PP1V05_S0_PCH_VCCADPLL

=PP3V42_G3H_PWRCTL

=PP1V8_S0_REG=PP15V_TBT_REG

=PP3V3_TBTLC_FET

=PP1V05_TBTLC_FET

=PP1V05_TBTCIO_FET=PPVIN_S0_DDRREG_LDO

=PP3V3_S3_P3V3S3FET

=PPVIN_S5_HS_OTHER_ISNS

=PP5V_SUS_FET

=PP5V_SUS_PCH

=PPVRTC_G3_PCH

VOLTAGE=5V

PP5V_SUSMIN_LINE_WIDTH=0.50MMMIN_NECK_WIDTH=0.20MM

MAKE_BASE=TRUE

=PP5V_S3_LIO_CONN

=PP5V_S3_RTUSB

=PP5V_S3_P5VS0FET

=PP5V_S3_MEMRESET

=PP5V_S3_AUDIO_AMP=PP5V_S3_DDRREG

=PP5V_S3_REG

VOLTAGE=5VMAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.5 mmPP5V_S3

=PP5V_S0_KBDLED

=PP5V_S0_VMON

=PP5V_S0_PCH

=PP5V_S0_VCCSA=PP5V_S0_LPCPLUS

=PP5V_S0_FAN

=PP5V_S0_CPUVCCIOS0

=PP5V_S0_CPUIMVP

=PP5V_S0_BKL

=PP5V_S0_FET PP5V_S0


MAKE_BASE=TRUE


VOLTAGE=5V

=PP3V3_TBT_PCH_GPIO


=PPVDDIO_S0_SBCLK

=PP1V8R1V5_S0_PCH_VCCVRM

=PP1V8_S0_PCH_VCC_DFTERM

=PPCPUVCCIO_S0_REG

=PP1V05_SUS_PCH_JTAG

=PP1V05_S0_PCH

=PP1V05_S0_PCH_VCCIO

=PP1V05_S0_PCH_VCCIO_PCIE

=PP1V05_S0_VMON

=PP1V05_S0_PCH_VCC_DMI

=PPVCCIO_S0_CPUIMVP

=PP1V5_S3_MEMRESET

=PP1V5_S3_MEM_A

=PP1V5_S3_MEM_B

=PP1V05_S0_PCH_VCCASW

=PP1V05_S0_PCH_VCCIO_SATA

=PPVTT_S0_DDR_LDO

=PP1V5_S0_REG

=PP1V05_S0_CPU_VCCIO

=PP1V05_S0_PCH_VCCDIFFCLK

=PP1V05_S0_PCH_VCC_CORE

=PP1V8_S0_P1V5S0

PP1V8_S0MIN_LINE_WIDTH=0.5 MM

MAKE_BASE=TRUEVOLTAGE=1.8VMIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MMPP1V05_SUS



MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.4 MMPP15V_TBT

VOLTAGE=17.8V

=PPDDR_S3_MEMVREF

PP1V5_S3

MIN_NECK_WIDTH=0.1 MMMIN_LINE_WIDTH=0.8 MM


=PP3V3_S5_LPCPLUS


MAKE_BASE=TRUEVOLTAGE=3V

PPVRTC_G3H

=PP3V42_G3H_REG

=PPVIN_S5_P5VP3V3

=PP1V5_S3_P1V5S3RS0_FET

=PP3V3_TBTLC_RTR

=PPVDDIO_TBT_CLK


MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MMVOLTAGE=3.3V

PP3V3_TBTLC

=PP1V8_S0_CPU_VCCPLL =PPHV_SW_TBTAPWRSW

MAKE_BASE=TRUE

PPVCORE_S0_AXG


VOLTAGE=1.05V

=PPVCORE_S0_CPU_VCCAXG

=PPGFXVCORE_S0_VSENSE


MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.6 MMPP1V5_S3_CPU_VCCDQ=PP1V5_S3_CPU_VCCDQ

MAKE_BASE=TRUE


MIN_LINE_WIDTH=0.6 MMPP1V05_S0_CPU_VCCPQE=PP1V05_S0_CPU_VCCPQE

=PP1V8_S0_CPU_VCCPLL_R

=PP1V05_TBTLC_RTR

=PP1V05_TBTCIO_RTR

MIN_LINE_WIDTH=0.4 MMMIN_NECK_WIDTH=0.2 MMVOLTAGE=1.05VMAKE_BASE=TRUE

PP1V05_TBTCIO

PP1V05_TBTLCMIN_LINE_WIDTH=0.4 MMMIN_NECK_WIDTH=0.2 MMVOLTAGE=1.05VMAKE_BASE=TRUE

=PPVTT_S0_VTTCLAMP

=PPVCCSA_S0_REG

=PPVCCSA_S0_VSENSE

=PPVCCSA_S0_CPU

VOLTAGE=0.75VMIN_NECK_WIDTH=0.17 mm

PP0V75_S0_DDRVTT

MAKE_BASE=TRUE

MIN_LINE_WIDTH=2 mm

MIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.2 MM


PPVCCSA_S0_CPU

=PPDCIN_S5_CHGR

=PP3V3_S5_SMC

=PP3V42_G3H_HALL

=PP3V42_G3H_CHGR

=PP3V42_G3H_SMBUS_SMC_BSA

=PP3V42_G3H_SMCUSBMUX

=PP3V42_G3H_TPAD

=PPVIN_S5_SMCVREF

=PPVBAT_G3H_SYSCLK

=PP18V5_DCIN_CONN

=PP3V3_S5_SMCBATLOW

=PP3V3_S5_LCD

=PP1V05_S0_LDO



PPVCORE_S0_CPU

=PPVCORE_S0_CPU

=PPCPUVCORE_S0_VSENSE


MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mmPPBUS_S5_HS_OTHER_ISNS

MAKE_BASE=TRUE

PPBUS_S5_HS_COMPUTING_ISNS

MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.6 mm

VOLTAGE=8.4V

=PPBUS_S0_VSENSE

MIN_NECK_WIDTH=0.25 mm


MIN_LINE_WIDTH=0.6 mmPPBUS_G3H

PPVIN_SW_TBTBSTVOLTAGE=12.8V

PP1V05_S0MIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.2 MM


=PPVIN_S5_HS_COMPUTING_ISNS


VOLTAGE=3.42VMIN_NECK_WIDTH=0.2 MM

PP3V42_G3H

MAKE_BASE=TRUE


=PPDCIN_S5_CHGR_ISOL

=PPDCIN_S5_VSENSE

MAKE_BASE=TRUE

PPDCIN_G3H_ISOLMIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.25 MMVOLTAGE=18.5V

=PP18V5_DCIN_ISOL

=PPVRTC_G3_OUT

=PPVIN_S0_CPUAXG

=PPVIN_S0_VCCSAS0

=PPVIN_S5_HS_COMPUTING_ISNS_R

=PP3V3_S5_CPU_VCCDDR=PPVIN_SW_TBTBST

=PPVIN_S5_HS_OTHER_ISNS_R

=PPVIN_S3_DDRREG

=PPVIN_S0_CPUIMVP

=PP3V3_S5_PCH

=PP3V3_S5_XDP

=PP3V3_S4_TBT

=PP3V3_S3_VREFMRGN

=PP3V3_S3_USB_RESET


MIN_LINE_WIDTH=0.50MMPP3V3_S3


MIN_LINE_WIDTH=0.38 MMMAKE_BASE=TRUEVOLTAGE=3.3V

PP3V3_SW_TBTAPWR


=PP3V3_SUS_SMC

=PP3V3_S4_TBTAPWRSW

=PP3V3_S4_P3V3S4FET

=PP3V3_S5_P3V3SUSFET

=PP3V3_S5_VMON

=PP3V3_S5_PCH_VCCDSW

=PP3V3_S5_SYSCLK

=PP3V3_S5_PWRCTL

=PP3V3_S5_PCH_GPIO

=PPBUS_S0_LCDBKLT

=PP3V3_S4_TPAD

=PP3V3_S4_BT

MIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE

VOLTAGE=3.3VPP3V3_S5

MIN_NECK_WIDTH=0.20MMVOLTAGE=3.3VMAKE_BASE=TRUE

PP3V3_S4MIN_LINE_WIDTH=0.60MM

=PP3V3_S4_FET

=PP3V3_S5_REG

051-9276

2.7.0

8 OF 109

7 OF 72

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53

44

12 15

6

6

52

40 41

6 51

52

43

38

6 48

41

25

6 51

41

62

59

6

9 12 14

44

6

6

44

6 51

6 35

6

8

6

35

52

44

6 51

25

57

53

8

26 35

45

55

56 57

17

23

33 34 35

31

24

6

63

41

63

60

60

61

20 22

25

61

19

64

48

36

6 71

6 60

54

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT IN

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

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PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



2x TBT pin diodes

2x USB connector

860-1327

870-1940

EMI I/O Pogo Pins

Digital Ground

998-3975

CPU Heat Sink Mounting Bosses

USB/SD Card Pogo

Fan Boss

Unused PGOOD signal

LVDS Aliases

860-1327

TBT DP Ports

SMC AliasesUnused SMC Signals

SATA AliasesUnused SATA ODD Signals

4x 860-1327

860-1327

UNUSED SDCARD USB Aliases

CPU signals

998-3975

998-2691 998-2691

998-3975

998-2691

2x MDP connector

2x TBT chip

2x CPU Vcore

870-1938

DisplayPort Pogo

998-2691

Can Slots

X21 Boss

998-2691

998-2691

998-3975

SSD Boss

60

55

16

16

16

16

0.5%

1W MF

0.01

CRITICAL

0612-1

45 71

45 71

STDOFF-4.5OD1.8H-SM

STDOFF-4.5OD1.8H-SM

STDOFF-4.5OD1.8H-SM

STDOFF-4.5OD1.8H-SM

STDOFF-4.5OD1.9H-SMSTDOFF-4.5OD1.9H-SMSTDOFF-4.5OD1.8H-SM

CRITICAL

POGO-2.0OD-3.6H-K86-K87SM

5%1/20W

MF201

2.2K

1/20WMF

2.2K

201

5%

NOSTUFF

2.2K

MF1/20W

5%

201

NOSTUFF

2.2K5%

MF1/20W

201

201

470K

1/20W5%

MF

470K

1/20WMF

201

5%

24 67

24 67

CRITICAL

POGO-2.0OD-2.95H-K86-K87SM

10K5%

MF1/20W

201

5%

MF

10K

201

1/20W

201

100K5%

1/20WMF

TH-NSP

SL-1.1X0.4-1.4x0.7

TH-NSP

SL-1.1X0.4-1.4x0.7

SL-1.1X0.45-1.4x0.75

TH-NSP

SL-1.1X0.45-1.4x0.75

TH-NSP

40

40

1W0612

MF1%

0.002

CRITICAL

45 71

45 71

7 7

RAMCFG3:L

5%1/20W

10K

201MF

10K5%

MF1/20W

201

RAMCFG2:L RAMCFG1:L

10K5%

MF201

1/20W 1/20WMF

5%10K

201

RAMCFG0:L

201

5%10K

MF1/20W

10K5%

1/20WMF

201 201

5%

MF1/20W

10K

201

5%

MF

10K

1/20W

10K

1/20WMF

5%

201

SL-1.1X0.4-1.4x0.7

TH-NSP

TH-NSP

SL-1.1X0.45-1.4x0.75

SL-1.1X0.4-1.4x0.7

TH-NSP

TH-NSP

SL-1.1X0.45-1.4x0.75

TH-NSP

SL-1.1X0.4-1.4x0.7

TH-NSP

SL-1.1X0.4-1.4x0.7

Signal Aliases


MIN_NECK_WIDTH=0.075MMMIN_LINE_WIDTH=0.6MM

VOLTAGE=0VGND

MAKE_BASE=TRUETRUE NC_PCIE_CLK100M_EXCARDN

TRUEMAKE_BASE=TRUE

NC_PCIE_CLK100M_EXCARDP

NC_PEG_CLK100MPMAKE_BASE=TRUE

ISNS_LCDBKLT_P

TBT_B_CONFIG1_BUF

MAKE_BASE=TRUENC_PCIE_CLK100M_ENETNTRUE

NC_PCIE_CLK100M_ENETPMAKE_BASE=TRUE

TRUE

DP_TBTSNK0_AUXCH_C_PMAKE_BASE=TRUE

MAKE_BASE=TRUETRUE NC_USB3_EXTD_RXN

USB3_EXTC_TX_N

USB_EXTC_N

MAKE_BASE=TRUENC_TBT_B_D2RN<1>TRUETBT_B_D2R_N<1>

TRUEMAKE_BASE=TRUE

NC_USB_EXTD_EHCIN

NC_USB3_EXTD_TXPMAKE_BASE=TRUETRUE

SATARDRVR_EN

MLB_RAMCFG1

TRUEMAKE_BASE=TRUE

NC_TBT_B_R2D_CN<1>

TBT_B_CIO_SEL

MAKE_BASE=TRUEDPLL_REF_CLK_N

NC_PEG_CLK100MNMAKE_BASE=TRUE

PCIE_CLK100M_EXCARD_P

MLB_RAMCFG0

ENET_LOW_PWR_PCH

MAKE_BASE=TRUETRUE NC_USB3_EXTC_RXN

MAKE_BASE=TRUEMEMVTT_EN =DDRVTT_EN

DPA_IG_AUX_CH_N

MAKE_BASE=TRUEPPBUS_SW_LCDBKLT_PWR

ISNS_LCDBKLT_N=PPBUS_SW_BKL

NC_PCIE_8_D2RN

=PPVIN_S5_HS_COMPUTING_ISNS_R

TRUEMAKE_BASE=TRUE

NC_USB_EXTCP

NC_TBT_B_D2RP<1>TRUEMAKE_BASE=TRUE

TBT_B_D2R_N<0>

TBT_B_D2R_P<1>

TBT_B_D2R_P<0> NC_TBT_B_D2RP<0>TRUEMAKE_BASE=TRUE

NC_TBT_B_D2RN<0>MAKE_BASE=TRUETRUE

NC_TBT_B_R2D_CN<0>MAKE_BASE=TRUETRUE

TRUEMAKE_BASE=TRUE

NC_TBT_B_R2D_CP<0>

MAKE_BASE=TRUENC_TBT_B_R2D_CP<1>TRUETBT_B_R2D_C_P<1>

TBT_B_R2D_C_N<0>

DP_TBTPB_ML_C_N<1>

NC_DP_TBTPB_ML_CP<1>MAKE_BASE=TRUE

PCIE_FW_R2D_C_PMAKE_BASE=TRUETRUE NC_PCIE_FW_R2D_CP

PCIE_FW_R2D_C_NMAKE_BASE=TRUETRUE NC_PCIE_FW_R2D_CN

PCIE_FW_D2R_NMAKE_BASE=TRUETRUE NC_PCIE_FW_D2RN

PCIE_FW_D2R_PMAKE_BASE=TRUE

NC_PCIE_FW_D2RPTRUE

PCIE_ENET_R2D_C_P

PCIE_ENET_R2D_C_NMAKE_BASE=TRUETRUE NC_PCIE_ENET_R2D_CN

PCIE_ENET_D2R_N

=PEG_R2D_C_N<1..0> PCIE_SSD_R2D_C_N<1..0>MAKE_BASE=TRUE

=PEG_D2R_N<1..0>

=PEG_R2D_C_P<1..0>MAKE_BASE=TRUE

PCIE_SSD_R2D_C_P<1..0>

=PEG_D2R_P<1..0>

TBT_B_CONFIG2_RC

NC_USB3_EXTC_TXNMAKE_BASE=TRUETRUE

TRUEMAKE_BASE=TRUE

NC_USB3_EXTD_RXP

DP_TBTPB_HPD

TBT_B_LSRX

MLB_RAMCFG3

USB_SDCARD_N

USB_SDCARD_P

=PP3V3_S3_USB_HUB

=PPVIN_S5_HS_COMPUTING_ISNS

ISNS_HS_COMPUTING_P

ISNS_HS_COMPUTING_N

PPBUS_SW_BKLMIN_LINE_WIDTH=0.5 MMMIN_NECK_WIDTH=0.375 MMVOLTAGE=12.6VMAKE_BASE=TRUE

MAKE_BASE=TRUEDP_TBTSNK0_AUXCH_C_N

PEG_CLK100M_N

MEM_B_CLK_N<1>

USB3_EXTD_RX_P

PCIE_CLK100M_ENET_N

NC_PCIE_EXCARD_D2RNTRUEMAKE_BASE=TRUE DP_TBTSNK0_ML_C_N<3..0>

MAKE_BASE=TRUE

DP_TBTSNK0_ML_C_P<3..0>MAKE_BASE=TRUE

TP_DP_IG_B_MLP<3..0>

NC_DP_TBTPB_AUXCH_CNMAKE_BASE=TRUE

NC_DP_TBTPB_AUXCH_CPMAKE_BASE=TRUE

DP_TBTPB_AUXCH_C_N

MAKE_BASE=TRUEDP_TBTSNK1_AUXCH_C_N

MAKE_BASE=TRUEPCIE_TBT_R2D_C_N<2>

USB_EXTD_EHCI_P

MAKE_BASE=TRUETP_MEM_A_CLKP<1>

USB3_EXTD_RX_N

USB3_EXTC_TX_P

PCIE_TBT_R2D_C_P<0>MAKE_BASE=TRUE





MAKE_BASE=TRUEPCIE_TBT_D2R_N<1>

LVDS_IG_B_DATA_N<0..3>

LVDS_IG_A_DATA_P<3>

LVDS_IG_B_DATA_P<0..3>

LVDS_IG_B_CLK_N

DPLL_REF_CLK_PMAKE_BASE=TRUE

DPA_IG_AUX_CH_P

USB3_EXTC_RX_P

USB3_EXTC_RX_N

MAKE_BASE=TRUETP_DDRREG_PGOODMAKE_BASE=TRUETP_P1V5S3RS0_RAMP_DONE

IR_RX_OUT_RC

DPLL_REF_CLKN

DPLL_REF_CLKP

TP_PCH_CLKOUT_DPN

USB3_EXTD_TX_P

NC_IR_RX_OUT_RCNO_TEST=TRUEMAKE_BASE=TRUE

DDRREG_PGOOD

P1V5S3RS0_RAMP_DONE

MAKE_BASE=TRUE NO_TEST=TRUENC_SMC_SYS_LEDSMC_SYS_LED

LVDS_IG_B_CLK_PTP_LVDS_IG_B_CLKPMAKE_BASE=TRUE

LVDS_IG_PANEL_PWRMAKE_BASE=TRUELCD_IG_PWR_EN

LVDS_IG_BKL_PWMLCD_BKLT_PWMMAKE_BASE=TRUE

LVDS_IG_A_DATA_N<3>MAKE_BASE=TRUE NO_TEST=TRUE

NC_LVDS_IG_A_DATAN<3>

NC_LVDS_IG_A_DATAP<3>MAKE_BASE=TRUE NO_TEST=TRUE

NC_LVDS_IG_B_DATAP<0..3>NO_TEST=TRUEMAKE_BASE=TRUE

TP_LVDS_IG_B_CLKNMAKE_BASE=TRUE

NC_LVDS_IG_B_DATAN<0..3>NO_TEST=TRUEMAKE_BASE=TRUE

NC_SATA_ODD_R2DCPNO_TEST=TRUEMAKE_BASE=TRUE

MAKE_BASE=TRUENC_SATA_ODD_R2DCN

NO_TEST=TRUE

MAKE_BASE=TRUENC_SATA_ODD_D2RP

NO_TEST=TRUE

LVDS_IG_BKL_ONLCD_BKLT_ENMAKE_BASE=TRUE

NC_SATA_ODD_D2RNMAKE_BASE=TRUE NO_TEST=TRUE



NC_PCIE_5_R2D_CN

NC_PCIE_7_R2D_CN

NC_PCIE_6_D2RN

PCIE_TBT_D2R_N<2>MAKE_BASE=TRUE

NC_PCIE_7_D2RN


NC_PCIE_8_R2D_CP

NC_PCIE_6_R2D_CP

NC_PCIE_5_R2D_CP

NC_PCIE_6_R2D_CN

MAKE_BASE=TRUETP_MEM_A_CLKN<1>

MAKE_BASE=TRUEDP_TBTSNK1_ML_C_N<3..0>

MAKE_BASE=TRUEDP_TBTSNK1_ML_C_P<3..0>

DP_TBTSNK1_HPDMAKE_BASE=TRUE

DP_TBTSNK1_AUXCH_C_PMAKE_BASE=TRUE

DPB_IG_HPD

TP_DP_IG_C_MLP<3..0>

NC_PCIE_EXCARD_R2D_CNTRUEMAKE_BASE=TRUE

MAKE_BASE=TRUEDP_TBTSNK0_DDC_DATA

MAKE_BASE=TRUEDP_TBTSNK0_DDC_CLK

DP_TBTSNK0_HPDMAKE_BASE=TRUE

SATA_ODD_R2D_C_N

SATA_ODD_D2R_P

SATA_ODD_D2R_N

SATA_ODD_R2D_C_P

TP_PCH_CLKOUT_DPP

TRUEMAKE_BASE=TRUE

NC_USB3_EXTC_RXP

TBT_B_R2D_C_P<0>

USB_EXTD_EHCI_N

TBT_B_R2D_C_N<1>

MAKE_BASE=TRUETRUE NC_TBT_B_LSTX

MEM_B_CLK_P<1>

MAKE_BASE=TRUENC_PCIE_ENET_D2RPTRUEPCIE_ENET_D2R_P

TRUEMAKE_BASE=TRUE

NC_PCIE_ENET_D2RN

DP_TBTPB_AUXCH_C_P

TP_DP_IG_C_MLN<3..0>

DPB_IG_AUX_CH_P

DPB_IG_AUX_CH_N

PCIE_EXCARD_D2R_P

PCIE_CLK100M_ENET_P

MEM_A_CLK_N<1>

MEM_A_CLK_P<1>

PEG_CLK100M_P

MAKE_BASE=TRUETRUE NC_PCIE_EXCARD_R2D_CP

PCIE_CLK100M_EXCARD_N

PCIE_EXCARD_R2D_C_P

PCIE_EXCARD_R2D_C_N

USB3_EXTD_TX_N

USB_EXTC_P

PCIE_CLK100M_FW_P

DP_TBTPB_ML_C_N<3>

MAKE_BASE=TRUETRUE NC_PCIE_ENET_R2D_CP

MAKE_BASE=TRUEPCIE_SSD_D2R_N<1..0>

MAKE_BASE=TRUENC_DP_TBTPB_ML_CN<3>

NC_DP_TBTPB_ML_CP<3>MAKE_BASE=TRUE

DP_TBTPB_ML_C_P<3>

PCIE_CLK100M_FW_N

MAKE_BASE=TRUEPCIE_SSD_D2R_P<1..0>

MAKE_BASE=TRUENC_PCIE_CLK100M_FWP

MAKE_BASE=TRUENC_PCIE_CLK100M_FWN

TBT_B_LSTX

DP_TBTPB_ML_C_P<1>

NC_DP_TBTPB_ML_CN<1>MAKE_BASE=TRUE

PCIE_EXCARD_D2R_N

MAKE_BASE=TRUEDP_IG_D_HPD

TP_DP_IG_B_MLN<3..0>

NC_PCIE_7_R2D_CP

NC_PCIE_5_D2RN

DPA_IG_HPD


NC_PCIE_8_R2D_CN

TP_DP_IG_D_CTRL_CLK

TP_DP_IG_D_CTRL_DATA

NC_PCIE_EXCARD_D2RPMAKE_BASE=TRUETRUE

=PP3V3_S0_DP_DDC

TP_DP_IG_D_HPD

DPA_IG_DDC_DATA

DPA_IG_DDC_CLK

=PP3V3_S0_DP_DDC

DP_IG_D_CTRL_DATAMAKE_BASE=TRUE

DP_IG_D_CTRL_CLKMAKE_BASE=TRUE

DPB_IG_DDC_DATA

DPB_IG_DDC_CLK

MLB_RAMCFG2

MAKE_BASE=TRUEXDP_DC3_PCH_GPIO19_SATARDRVR_EN

MAKE_BASE=TRUEXDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH

TP_MEM_B_CLKP<1>MAKE_BASE=TRUE

MAKE_BASE=TRUETP_MEM_B_CLKN<1>

MAKE_BASE=TRUETRUE NC_USB_EXTCN

NC_USB3_EXTC_TXPMAKE_BASE=TRUETRUE

MAKE_BASE=TRUETRUE NC_USB3_EXTD_TXN

MAKE_BASE=TRUETRUE NC_USB_EXTD_EHCIP

MAKE_BASE=TRUEPCIE_TBT_D2R_P<3>




NC_PCIE_8_D2RP

NC_PCIE_7_D2RP

NC_PCIE_6_D2RP

NC_PCIE_5_D2RPR0910

1 2

3 4

Z0910

1

Z0912

1

Z0913

1

Z0911

1

Z0915

1

Z0914

1

Z0905

1

ZS0905

1

R09201

2

R09211

2

R09221

2

R09231

2

R09241

2

R09251

2

ZS0907

1

R09021

2

R09011

2

R09091

2

SL09011

SL09021

SL09041

SL09031

R0954

12

34

R09501

2

R09511

2

R09521

2

R09531

2

R09161

2

R09171

2

R09181

2

R09191

2

R09141

2

SL09061

SL09081

SL09051

SL09071

SL09101

SL09091

051-9276

2.7.0

9 OF 109

8 OF 72

33

33 68

18

18

33 69

16

19

33

16

19

19

26 26 55

17

64

64

16

33 69

33 69

33 69

33 69

33 69

33 69

16

16

16

16

16

16

16

9 37 65

9

9 37 65

9

33

33

33

19

7 24

33 68

16 68

11 66

18

16

33 68

33 68 17

33 69

33 68

33 68

18

18

18

33 68

33 68

33 68

33 68

33 68

33 68

17

18

18

10 65

10 65

16

18

6

17 62

17 64

6

17 64

33 68

33 68

16

16

16

33 68 16

33 68

16

16

16

16

33 68

33 68

33

33 68

17

17

63

63

33

16

18

33 69

11 66

16

33 69

17

17

17

16

16

11 66

16 68

16

16

16

18

18

16

33 69

6 37 65

33 69

16

6 37 65

33

33 69

16 17

16

16

17

33 68

16

17

17

7 8

17

17

17

7 8

17

17

19

16 23

19 23

33 68

33 68

33 68

33 68

16

16

16

16

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

NC

NCNCNCNC

NCNCNCNCNCNCNCNCNCNC

NC

NCNC

NC

NC

NC

NC

NC

NCNCNCNC

NCNCNC

EDP_TX_3

EDP_TX_0

EDP_TX_1

EDP_TX_2

EDP_TX_2*

EDP_TX_3*

EDP_TX_0*

EDP_TX_1*

EDP_AUX

EDP_AUX*

EDP_COMPIO

EDP_HPD

EDP_ICOMPO

FDI1_LSYNC

DMI_TX_3*

FDI0_LSYNC

FDI0_TX_3

FDI1_TX_1

FDI1_TX_0

FDI1_TX_2

FDI1_TX_3

FDI0_FSYNC

FDI1_FSYNC

FDI_INT

FDI1_TX_3*

FDI1_TX_2*

FDI0_TX_1

FDI0_TX_0

FDI0_TX_2

FDI1_TX_1*

FDI0_TX_3*

FDI1_TX_0*

FDI0_TX_2*

FDI0_TX_1*

DMI_TX_1*

DMI_TX_2*

DMI_TX_0

DMI_TX_2

DMI_TX_1

DMI_TX_3

FDI0_TX_0*

DMI_RX_2*

DMI_RX_0

DMI_RX_1

DMI_RX_2

DMI_RX_3

DMI_TX_0*

DMI_RX_3*

DMI_RX_1*

DMI_RX_0* PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX_2*

PEG_RX_0*

PEG_RX_1*

PEG_RX_3*

PEG_RX_4*

PEG_RX_5*

PEG_RX_7*

PEG_RX_6*

PEG_RX_8*

PEG_RX_9*

PEG_RX_10*

PEG_RX_12*

PEG_RX_11*

PEG_RX_14*

PEG_RX_13*

PEG_RX_15*

PEG_RX_0

PEG_RX_1

PEG_RX_3

PEG_RX_2

PEG_RX_4

PEG_RX_6

PEG_RX_5

PEG_RX_7

PEG_RX_8

PEG_RX_10

PEG_RX_9

PEG_RX_11

PEG_RX_12

PEG_RX_13

PEG_RX_14

PEG_RX_15

PEG_TX_1*

PEG_TX_2*

PEG_TX_0*

PEG_TX_3*

PEG_TX_4*

PEG_TX_5*

PEG_TX_7*

PEG_TX_6*

PEG_TX_10*

PEG_TX_8*

PEG_TX_9*

PEG_TX_11*

PEG_TX_12*

PEG_TX_13*

PEG_TX_14*

PEG_TX_15*

PEG_TX_1

PEG_TX_0

PEG_TX_2

PEG_TX_3

PEG_TX_4

PEG_TX_6

PEG_TX_5

PEG_TX_7

PEG_TX_8

PEG_TX_9

PEG_TX_10

PEG_TX_11

PEG_TX_12

PEG_TX_14

PEG_TX_13

PEG_TX_15

(1 OF 9)

PCI EXPRESS BASED INTERFACE SIGNALS

DMI

INTEL FLEXIBLE DISPLAY INTERFACE SIGNALS

EMBEDDED DISPLAY PORT

NCNC

RSVD_26

RSVD_27

RSVD_25

RSVD_23

RSVD_24

RSVD_22

RSVD_21

RSVD_19

RSVD_18

RSVD_16

RSVD_17

RSVD_15

RSVD_14

RSVD_13

RSVD_12

DC_TEST_BG1

DC_TEST_BD1

DC_TEST_BE1

DC_TEST_BG3

DC_TEST_BE3

DC_TEST_BG4

DC_TEST_BG58

DC_TEST_BG59

DC_TEST_BE59

DC_TEST_BG61

DC_TEST_BD61

DC_TEST_BE61

DC_TEST_D61

DC_TEST_A61

DC_TEST_C61

DC_TEST_A59

DC_TEST_C59

DC_TEST_A58

DC_TEST_D3

DC_TEST_D1

DC_TEST_C4

DC_TEST_A4

RSVD_45

RSVD_44

RSVD_41

RSVD_43

RSVD_42

RSVD_39

RSVD_40

RSVD_38

RSVD_36

RSVD_33

RSVD_31

RSVD_32

RSVD_30CFG_3

CFG_2

CFG_1

CFG_0

CFG_9

CFG_8

CFG_7

CFG_6

CFG_14

CFG_12

CFG_10

CFG_16

CFG_17

VCC_VAL_SENSE

RSVD_8

RSVD_7

RSVD_6

CFG_15

CFG_13

CFG_11

CFG_5

CFG_4

VSS_VAL_SENSE

VAXG_VAL_SENSE

VCC_DIE_SENSE

VSSAXG_VAL_SENSE

RSVD_11

RSVD_9

RSVD_10

RSVD_20

RSVD_37

RSVD_35

RSVD_34

SB_DIMM_VREFDQ

SA_DIMM_VREFDQ

RESERVED(5 OF 9)

NCNCNC

NC

OUT

OUT

OUT

OUT

S

D

G

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



doc 439028 rev1.0 HR_PPDG sections 6.2.1 and 6.3.1.

NOTE: Intel validation sense lines per

Note. VOLTAGE=0V

Note. VOLTAGE=1.05V

even if internal Graphics is disabled since they are

NOTE: The EDP_HPD processor input is a low voltage active low signal.Therefore, an inverting level shifter is required on the motherboardto convert the active high signal from Embedded DisplayPort sink device

shared with other interfaces.

NOTE: eDP_COMPIO and eDP_ICOMPO can not be left floating

to low voltage signals for the processor

Intel Doc 467283 ChiefRiver Platform design guild rev0.71 section 2.2.12 recommendation.

Note. VOLTAGE=1.25V

Note. VOLTAGE=0V

NOTE: Intel does not recommend to usethis alnalog sense due to accuracy concern.

NOTE: Intel provides an internal pull-up OF 5-15k to VCCIO on all CFG signals.

connect it to CPU VCCIo via a 10-kOhm pull-up resistor on the motherboard.

CR SFF Intel doc #460452 Rise/Fall time <6ns

(refer to latest Processor EDS for DC specifications).

If HPD is disabled while eDP interface is still enabled,

This signal can be left as no-connect if entire eDP interface is disabled.

These can be Placed close to J2500 and Only for debug access

CFG [4] :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED

CFG [3] :PCIE x4 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED

CFG [2] :PCIE x16 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED

CFG [6:5] :PCIE BIFURCATION 11 = 1 X16 (DEFAULT) 10 = 2 X8 01 = RSVD 00 = X8, X4, X4

CFG [7] :PEG DEFER TRAINING 1 = (DEFAULT) IMMEDIATELY AFTER xxRESETB 0 = WAIT FOR BIOS

FOR IVYBRIDGE PROCESSOR

17 65

17 65

17 65

17 65

17 65

17 65

17 65

17 65

17 65

17 65

17 65

17 65

17 65

17 65

17 65

17 65

8

6

6

6

6

6

6

6

6

6

6

6

6

6

6

8

8

6

6

6

8

6

6

6

6

6

6

6

6

6

6

6

8

6

6

6

8

6

6

6

6

6

6

8

6

6

8

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

9 23 65

9 23 65

9 23 65

9 23 65

9 23 65

9 23 65

9 23 65

9 23 65

23 65

23 65

23 65

23 65

23 65

23 65

23 65

23 65

9 23

23

17 65

17 65

17 65

17 65

17 65

17 65

17 65

17 65

17 65

17 65

17 65

17 65

17 65

17 65

17 65

17 65

17 65

17 65

17 65

17 65

17 65

CRITICALOMIT_TABLE

BGA

IVY-BRIDGE2C-35W

IVY-BRIDGE

BGA

CRITICALOMIT_TABLE

2C-35W

46 71

46 71

31

31

MF201

1/20W

1K5%

PLACE_NEAR=U1000.AG11:12.7MM

201

PLACE_NEAR=U1000.G3:12.7MM

MF1/20W1%

24.9

PLACE_NEAR=U1000.AF3:12.7MM

24.9

1%1/20W

201MF

EDP:YESSOT-523-3

2N7002TXG

402

1/16W

MF-LF

5%

NOSTUFF

1K

402

1/16W

MF-LF

NOSTUFF

1K5%

1/16W

402

MF-LF

5%

1K

NOSTUFF

402

EDP:YES

1/16W

MF-LF

1K5%

402

1K

1/16W

MF-LF

NOSTUFF

5% 5%

1K

NOSTUFF

MF-LF

1/16W

402

NOSTUFF

1/16W

MF-LF

5%

1K

402

NOSTUFF

5%

1K

MF-LF

1/16W

402

NOSTUFF

MF-LF

1/16W

1K5%

402

NOSTUFF

PLACE_SIDE=BOTTOM

MF-LF

1%

402

1/16W

49.9

PLACE_NEAR=U1000.H45:50.8MM

PLACE_SIDE=BOTTOMPLACE_NEAR=U1000.H43:50.8MM

49.9

1/16W

402

1%

NOSTUFF

MF-LF

49.9

1/16W

402MF-LF

PLACE_SIDE=BOTTOM

NOSTUFF

PLACE_NEAR=U1000.K45:50.8MM

1%

PLACE_SIDE=BOTTOM

49.9

402MF-LF

NOSTUFF

1%

PLACE_NEAR=U1000.K43:50.8MM

1/16W

SYNC_MASTER=J13_MLB

CPU DMI/PEG/FDI/RSVD


CPU_CFG<0>CPU_CFG<1>

CPU_CFG<2>CPU_CFG<4>CPU_CFG<5>CPU_CFG<6>CPU_CFG<7>

DP_INT_HPD

EDP_HPD_L

=PEG_R2D_C_P<9>

=PEG_D2R_N<14>

=PEG_D2R_P<8>

FDI_DATA_N<7>

FDI_DATA_P<5>FDI_DATA_P<6>



PPCPU_MEM_VREFDQ_A


=PEG_R2D_C_P<14>

CPU_DC_TEST_C61_A61

=PEG_R2D_C_P<15>


=PEG_D2R_P<15>=PEG_D2R_P<14>

CPU_PEG_COMP

TP_EDP_TX_P<2>

=PEG_R2D_C_P<0>


=PEG_D2R_P<7>

=PEG_D2R_P<5>

CPU_CFG<6>

CPU_CFG<4>

CPU_CFG<0>

=PEG_R2D_C_P<1>

=PEG_R2D_C_N<12>

=PEG_D2R_N<6>=PEG_D2R_N<5>

CPU_THERMD_NCPU_THERMD_P

=PEG_D2R_P<10>=PEG_D2R_P<11>=PEG_D2R_P<12>

CPU_DC_TEST_C59_A59

=PEG_D2R_P<13>

FDI_INT

FDI_FSYNC<0>

DMI_S2N_N<0>

=PEG_R2D_C_P<2>

CPU_CFG<17>

CPU_DC_TEST_C4_BE1_BG1

TP_CPU_DC_TEST_BD1

CPU_DC_TEST_C4_BE3_BG3TP_CPU_DC_TEST_BG4TP_CPU_DC_TEST_BG58

CPU_DC_TEST_BG59_BG61

CPU_DC_TEST_BE59_BE61TP_CPU_DC_TEST_BD61TP_CPU_DC_TEST_D61

TP_CPU_DC_TEST_D1

TP_CPU_DC_TEST_A4

CPU_CFG<3>CPU_CFG<2>CPU_CFG<1>

CPU_CFG<9>CPU_CFG<8>CPU_CFG<7>

CPU_CFG<14>

CPU_CFG<12>

CPU_CFG<10>


CPU_CFG<13>

CPU_CFG<11>

CPU_CFG<5>

TP_CPU_VCC_DIE_SENSE

FDI_LSYNC<1>

=PEG_R2D_C_P<13>

=PEG_R2D_C_P<8>=PEG_R2D_C_P<7>=PEG_R2D_C_P<6>

=PEG_R2D_C_N<15>=PEG_R2D_C_N<14>=PEG_R2D_C_N<13>

=PEG_R2D_C_N<11>

=PEG_R2D_C_N<9>=PEG_R2D_C_N<8>

=PEG_R2D_C_N<10>


=PEG_R2D_C_N<5>=PEG_R2D_C_N<4>=PEG_R2D_C_N<3>

=PEG_R2D_C_N<0>


=PEG_D2R_P<9>

=PEG_D2R_P<6>

=PEG_D2R_P<4>

=PEG_D2R_P<2>=PEG_D2R_P<3>

=PEG_D2R_P<1>

=PEG_D2R_N<15>

=PEG_D2R_N<9>=PEG_D2R_N<8>=PEG_D2R_N<7>



=PEG_D2R_N<2>

DMI_S2N_N<1>

DMI_S2N_N<3>

DMI_N2S_N<0>

DMI_S2N_P<3>DMI_S2N_P<2>DMI_S2N_P<1>DMI_S2N_P<0>

DMI_S2N_N<2>

FDI_DATA_N<0>

DMI_N2S_P<3>

DMI_N2S_P<1>DMI_N2S_P<0>

DMI_N2S_N<2>DMI_N2S_N<1>

FDI_DATA_N<1>FDI_DATA_N<2>FDI_DATA_N<3>

FDI_DATA_P<2>

FDI_DATA_P<0>FDI_DATA_P<1>

FDI_DATA_N<6>

FDI_FSYNC<1>

FDI_DATA_P<4>

FDI_DATA_P<3>

FDI_LSYNC<0>

FDI_DATA_N<4>

=PEG_D2R_N<11>

MIN_LINE_WIDTH=0.3 MMMIN_NECK_WIDTH=0.2 MMVOLTAGE=0.75V

PPCPU_MEM_VREFDQ_B

=PEG_R2D_C_P<10>

EDP_HPD_L

EDP_COMP

TP_EDP_TX_P<3>

TP_EDP_TX_P<1>DP_INT_ML_P<0>

TP_EDP_TX_N<3>TP_EDP_TX_N<2>

DP_INT_AUX_CH_NDP_INT_AUX_CH_P

DP_INT_ML_N<0>TP_EDP_TX_N<1>

=PEG_R2D_C_P<11>

DMI_N2S_N<3>

TP_CPU_DC_TEST_A58

CPU_DC_TEST_C4_D3

=PEG_R2D_C_P<12>

=PEG_R2D_C_P<5>

FDI_DATA_P<7>

FDI_DATA_N<5>

CPU_AXG_VALSENSE_P


CPU_VCC_VALSENSE_P

=PPVCORE_S0_CPU

CPU_AXG_VALSENSE_N

CPU_VCC_VALSENSE_N

=PEG_D2R_N<10>

DMI_N2S_P<2>

=PEG_D2R_P<0>


=PEG_R2D_C_P<3>=PEG_R2D_C_P<4>

CPU_CFG<3>

CPU_CFG<16>

U1000

N3

M2

P7

P6

P3

P1

P11

P10

K3

K1

M7

M8

P4

N4

T3

R2

AF4

AG4

AF3

AG11

AD2

AC1

AC3

AA4

AC4

AE10

AE11

AE6

AE7

AA11

AA10

U6

U7

W10

W11

W3

W1

AA7

AA6

AC12

AG8

W7

W6

T4

V4

AA3

Y2

AC8

AC9

U11

G3

G1

G4

K22

H22

K19

J21

F8

G8

C8

A8

C5

B6

H6

H8

F6

E5

K6

K7

C21

B22

D19

D21

C19

A19

D16

D17

C13

B14

D12

D13

C11

A11

C9

B10

F22

G22

A23

C23

K13

J14

G13

H13

K10

M10

G10

F10

D8

D9

K4

J4

D24

D23

E21

F21

G19

H19

B18

C17

K17

K15

G17

F17

E14

F14

C15

A15

U1000

B50

C51

K49

K53

F53

G53

L51

F51

D52

L53

B54

D53

A51

C53

C55

H49

A55

H51

A4

A58

A59

A61

BD1

BD61

BE1

BE3

BE59

BE61

BG1

BG3

BG4

BG58

BG59

BG61

C4

C59

C61

D1

D3

D61

AG13

AH2

AM14

AM15

AT21

AT49

AU19

AU21

AV19

AY21

AY22

BA19

BA22

BB19

BB21

BD21

BD22

BD25

BD26

BE22

BE24

BE26

BF23

BG22

BG26

H48

K24

K48

L42

L45

L47

M13

M14

N42

N50

P13

U14

W14

BE7

BG7

H45

F48

H43

K43

K45

R10311

2

R10101 2

R10301 2

Q1031

3

1

2

R10471

2

R10461

2

R10451

2

R10441

2

R10421

2

R10491

2

R10431

2

R10411

2

R10401

2

R10701

2

R10641

2

R10711

2

R10651

2

051-9276

2.7.0

10 OF 109

9 OF 72

9 23 65

9 23 65

9 23 65

9 23 65

9 23 65

9 23 65

9 23 65

62

9

7 9 10 12 14

7 9 10 12 14

65

6

7 9 10 12 14

9

65

6

6

62 65

6

6

62 65

62 65

62 65

6

7 12 15

7 12 14

9 23 65

9 23

IN

IN

IN

IN

OUT

OUT

BI

BI

BI

BI

BI

IN

BI

BI

BI

NC

SM_RCOMP_2

SM_RCOMP_1

SM_RCOMP_0

SM_DRAMRST*

BCLK_ITP

BCLK_ITP*

DPLL_REF_CLK*

DPLL_REF_CLK

BCLK*

BCLK

RESET*

SM_DRAMPWROK

UNCOREPWRGOOD

PM_SYNC

PROC_SELECT*

PROC_DETECT*

PREQ*

TMS

TRST*

TDI

TDO

DBR*

BPM_0*

BPM_1*

BPM_2*

BPM_3*

BPM_4*

BPM_5*

BPM_6*

BPM_7*

TCK

PRDY*

THERMTRIP*

CATERR*

PROCHOT*

PECI

(2 OF 9)

CLOCKS

THERMAL

PWR MGMT

JTAG & BPM

DDR3 MISC

IN

OUT

OUT

BI

OUT

IN

IN

OUT

IN

BI

IN

IN

IN

IN

OUT

IN

IN

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

Intel Doc 460452 ChiefRiver SFF DG rev1.0 section 2.7.11 recommendation R1115.

16 65

23 65

23 65

23 65

23 65

23 25 65

23 65

23 65

23 65

23 65

23 65

16 65

23 65

23 65

23 65

CRITICALOMIT_TABLE

IVY-BRIDGE2C-35W

BGA

NOSTUFF

1K5%1/20WMF201201

MF1/20W5%51

NOSTUFF

1K5%

1/20WMF201

NOSTUFF

10K

201MF1/20W

5%

PLACE_NEAR=U1000.B46:12.7MM

8 65

1/20W

MF

4.99K1%

201

NOSTUFF

1%

MF1/20W

200

201

PLACE_NEAR=U1000.BG43:12.7MM

1%1/20W

201MF

25.5

PLACE_NEAR=U1000.BE43:12.7MM

19

40 65

19 41 65

19 41 65

19 23 65

17 65

26

16 65

1%1/20WMF201

130

PLACE_NEAR=U1000.BE45:12.7MM

625%

1/20WMF201

201MF

1/20W5%

56

2001%

1/20WMF

201

PLACE_NEAR=R1121.2:1MM

40 41 56 65

1401%1/20WMF201

PLACE_NEAR=U1000.BF44:12.7MM43.2

1%

MF1/20W

201

751%

1/20WMF

201

17 26 65

8 65

23 25

16 65

23 65

23 65

23 65

SYNC_DATE=09/22/2011SYNC_MASTER=J13_MLB

CPU CLOCK/MISC/JTAG

CPU_PROCHOT_L


PM_MEM_PWRGD

CPU_RESET_L


PLT_RESET_LS1V1_L


CPU_SM_RCOMP<0>

PM_MEM_PWRGD_R

PM_SYNC

CPU_PROC_SEL_L

CPU_PROCHOT_R_L

CPU_SM_RCOMP<2>CPU_SM_RCOMP<1>

=MEM_RESET_L

CPU_PWRGD

PM_THRMTRIP_L

CPU_CATERR_L

CPU_PECI

ITPCPU_CLK100M_PITPCPU_CLK100M_N

DPLL_REF_CLKNDPLL_REF_CLKP

DMI_CLK100M_CPU_NDMI_CLK100M_CPU_P

XDP_CPU_PREQ_L

XDP_CPU_TMSXDP_CPU_TRST_L

XDP_CPU_TDIXDP_CPU_TDO

XDP_DBRESET_L

XDP_BPM_L<0>XDP_BPM_L<1>XDP_BPM_L<2>XDP_BPM_L<3>XDP_BPM_L<4>XDP_BPM_L<5>XDP_BPM_L<6>XDP_BPM_L<7>

XDP_CPU_TCK

XDP_CPU_PRDY_L

U1000

J3

H2

N59

N58

G58

E55

E59

G55

G59

H60

J59

J61

C49

K58

AG3

AG1

A48

C48

N53

N55

C57

F49

C45

D44

BE45

AT30

BF44

BE43

BG43

L56

M60

L59

D45

L55

J58

B46

R11021

2

R11041

2

R11001

2

R11111

2

R11151

2

R11141

2

R11131

2

R11211 2

R11011

2

R11031 2

R11201

2

R11121

2

R11251 2

R11261

2

051-9276

2.7.0

11 OF 109

10 OF 72

7 12 15 26

7 9 10 12 14

7 9 10 12 14

65

65

65

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

SA_MA_14

SA_MA_15

SA_MA_12

SA_MA_13

SA_MA_11

SA_MA_9

SA_MA_10

SA_MA_8

SA_MA_7

SA_MA_6

SA_MA_5

SA_MA_4

SA_MA_3

SA_MA_2

SA_MA_1

SA_MA_0

SA_DQS_7

SA_DQS_5

SA_DQS_6

SA_DQS_3

SA_DQS_4

SA_DQS_2

SA_DQS_0

SA_DQS_1

SA_DQS_7*

SA_DQS_6*

SA_DQS_5*

SA_DQS_4*

SA_DQS_3*

SA_DQS_2*

SA_DQS_0*

SA_DQS_1*

SA_ODT_1

SA_ODT_0

SA_CS_1*

SA_CS_0*

SA_CKE_1

SA_CK_1*

SA_CK_1

SA_CKE_0

SA_CK_0*

SA_CK_0

SA_WE*

SA_RAS*

SA_CAS*

SA_BS_0

SA_BS_1

SA_BS_2

SA_DQ_62

SA_DQ_63

SA_DQ_61

SA_DQ_60

SA_DQ_59

SA_DQ_58

SA_DQ_57

SA_DQ_56

SA_DQ_55

SA_DQ_54

SA_DQ_53

SA_DQ_52

SA_DQ_50

SA_DQ_51

SA_DQ_49

SA_DQ_48

SA_DQ_47

SA_DQ_46

SA_DQ_45

SA_DQ_44

SA_DQ_42

SA_DQ_43

SA_DQ_41

SA_DQ_39

SA_DQ_40

SA_DQ_38

SA_DQ_37

SA_DQ_36

SA_DQ_34

SA_DQ_35

SA_DQ_31

SA_DQ_33

SA_DQ_32

SA_DQ_29

SA_DQ_30

SA_DQ_26

SA_DQ_28

SA_DQ_27

SA_DQ_24

SA_DQ_25

SA_DQ_23

SA_DQ_22

SA_DQ_21

SA_DQ_19

SA_DQ_20

SA_DQ_18

SA_DQ_17

SA_DQ_16

SA_DQ_13

SA_DQ_14

SA_DQ_15

SA_DQ_11

SA_DQ_12

SA_DQ_9

SA_DQ_10

SA_DQ_8

SA_DQ_7

SA_DQ_6

SA_DQ_5

SA_DQ_4

SA_DQ_3

SA_DQ_2

SA_DQ_1

SA_DQ_0

(3 OF 9)

MEMORY CHANNEL A

SB_MA_15

SB_MA_14

SB_MA_12

SB_MA_13

SB_MA_11

SB_MA_10

SB_MA_9

SB_MA_7

SB_MA_8

SB_MA_6

SB_MA_5

SB_MA_4

SB_MA_3

SB_MA_2

SB_MA_1

SB_MA_0

SB_DQS_7

SB_DQS_6

SB_DQS_5

SB_DQS_4

SB_DQS_3

SB_DQS_2

SB_DQS_1

SB_DQS_0

SB_DQS_7*

SB_DQS_6*

SB_DQS_5*

SB_DQS_4*

SB_DQS_3*

SB_DQS_2*

SB_DQS_1*

SB_DQS_0*

SB_ODT_0

SB_ODT_1

SB_CS_1*

SB_CS_0*

SB_CKE_1

SB_CK_1

SB_CK_1*

SB_CK_0*

SB_CKE_0

SB_CK_0

SB_DQ_37

SB_DQ_36

SB_DQ_34

SB_DQ_35

SB_DQ_33

SB_DQ_31

SB_DQ_32

SB_DQ_30

SB_DQ_29

SB_DQ_26

SB_DQ_27

SB_DQ_28

SB_DQ_24

SB_DQ_25

SB_DQ_21

SB_DQ_22

SB_DQ_23

SB_DQ_20

SB_DQ_19

SB_DQ_18

SB_DQ_17

SB_DQ_16

SB_DQ_15

SB_DQ_14

SB_DQ_13

SB_DQ_12

SB_DQ_11

SB_DQ_10

SB_DQ_8

SB_DQ_9

SB_DQ_7

SB_DQ_6

SB_DQ_4

SB_DQ_5

SB_DQ_3

SB_DQ_2

SB_DQ_1

SB_DQ_0

SB_DQ_39

SB_DQ_38

SB_DQ_40

SB_DQ_41

SB_DQ_42

SB_DQ_44

SB_DQ_43

SB_DQ_46

SB_DQ_45

SB_DQ_47

SB_DQ_49

SB_DQ_48

SB_DQ_51

SB_DQ_50

SB_DQ_52

SB_DQ_54

SB_DQ_53

SB_DQ_56

SB_DQ_55

SB_DQ_57

SB_DQ_59

SB_DQ_58

SB_DQ_61

SB_DQ_60

SB_DQ_62

SB_BS_0

SB_DQ_63

SB_BS_2

SB_BS_1

SB_RAS*

SB_CAS*

SB_WE*

(4 OF 9)

MEMORY CHANNEL B

Apple Inc.


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6 3



27 66

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27 66

27 66

27 66

27 66

27 66

27 66

27 66

27 66

27 66

27 66

27 66

27 66

27 66

27 66

27 66

27 66

27 66

27 66

27 66

27 66

27 66

27 66

27 66

27 66

27 66

27 66

28 66

28 66

28 66

28 66

28 66

28 66

28 66

28 66

28 66

28 66

28 66

28 66

28 66

28 66

28 66

28 66

28 66

28 66

28 66

28 66

28 66

28 66

28 66

28 66

28 66

28 66

28 66

28 66

28 66

28 66

28 66

28 66

27 28 32 66

27 28 32 66

27 28 32 66

27 28 32 66

27 28 32 66

27 28 32 66

29 66

29 66

29 66

29 66

29 66

29 66

29 66

29 66

29 66

29 66

29 66

29 66

29 66

29 66

29 66

29 66

29 66

29 66

29 66

29 66

29 66

29 66

29 66

29 66

29 66

29 66

29 66

29 66

29 66

29 66

29 66

29 66

30 66

30 66

30 66

30 66

30 66

30 66

30 66

30 66

30 66

30 66

30 66

30 66

30 66

30 66

30 66

30 66

30 66

30 66

30 66

30 66

30 66

30 66

30 66

30 66

30 66

30 66

30 66

30 66

30 66

30 66

30 66

30 66

29 30 32 66

29 30 32 66

29 30 32 66

29 30 32 66

29 30 32 66

29 30 32 66

27 28 32 66

27 28 32 66

27 28 32 66

27 28 32 66

27 28 32 66

27 66

27 66

27 66

27 66

28 66

28 66

28 66

28 66

27 66

27 66

27 66

27 66

28 66

28 66

28 66

28 66

27 28 32 66

27 28 32 66

27 28 32 66

27 28 32 66

27 28 32 66

27 28 32 66

27 28 32 66

27 28 32 66

27 28 32 66

27 28 32 66

27 28 32 66

27 28 32 66

27 28 32 66

27 28 32 66

27 28 32 66

27 28 32 66

29 30 32 66

29 30 32 66

29 30 32 66

29 30 32 66

29 30 32 66

29 66

29 66

29 66

29 66

30 66

30 66

30 66

30 66

29 66

29 66

29 66

29 66

30 66

30 66

30 66

30 66

29 30 32 66

29 30 32 66

29 30 32 66

29 30 32 66

29 30 32 66

29 30 32 66

29 30 32 66

29 30 32 66

29 30 32 66

29 30 32 66

29 30 32 66

29 30 32 66

29 30 32 66

29 30 32 66

29 30 32 66

29 30 32 66

8 66

8 66

27 28 32 66

27 28 32 66

27 28 32 66

8 66

8 66

29 30 32 66

29 30 32 66

29 30 32 66

BGA

IVY-BRIDGE

2C-35W

OMIT_TABLE

CRITICAL

CRITICAL

OMIT_TABLE

BGA

2C-35W

IVY-BRIDGE


CPU DDR3 INTERFACES

MEM_B_A<15>MEM_B_A<14>


MEM_B_A<11>MEM_B_A<10>MEM_B_A<9>


MEM_B_A<6>MEM_B_A<5>MEM_B_A<4>MEM_B_A<3>MEM_B_A<2>MEM_B_A<1>MEM_B_A<0>

MEM_B_DQS_P<7>MEM_B_DQS_P<6>MEM_B_DQS_P<5>MEM_B_DQS_P<4>MEM_B_DQS_P<3>MEM_B_DQS_P<2>MEM_B_DQS_P<1>MEM_B_DQS_P<0>

MEM_B_DQS_N<7>MEM_B_DQS_N<6>MEM_B_DQS_N<5>MEM_B_DQS_N<4>MEM_B_DQS_N<3>MEM_B_DQS_N<2>MEM_B_DQS_N<1>MEM_B_DQS_N<0>

MEM_B_ODT<0>MEM_B_ODT<1>

MEM_B_CS_L<1>MEM_B_CS_L<0>

MEM_B_CKE<1>

MEM_B_CLK_P<1>MEM_B_CLK_N<1>

MEM_B_CLK_N<0>

MEM_B_CKE<0>

MEM_B_CLK_P<0>

MEM_B_DQ<37>MEM_B_DQ<36>


MEM_B_DQ<33>



MEM_B_DQ<26>MEM_B_DQ<27>MEM_B_DQ<28>



MEM_B_DQ<20>MEM_B_DQ<19>MEM_B_DQ<18>MEM_B_DQ<17>MEM_B_DQ<16>MEM_B_DQ<15>MEM_B_DQ<14>MEM_B_DQ<13>MEM_B_DQ<12>MEM_B_DQ<11>MEM_B_DQ<10>




MEM_B_DQ<3>MEM_B_DQ<2>MEM_B_DQ<1>MEM_B_DQ<0>





MEM_B_DQ<47>



MEM_B_DQ<52>



MEM_B_DQ<57>



MEM_B_DQ<62>

MEM_B_BA<0>

MEM_B_DQ<63>

MEM_B_BA<2>MEM_B_BA<1>

MEM_B_RAS_LMEM_B_CAS_L

MEM_B_WE_L

MEM_A_A<14>MEM_A_A<15>


MEM_A_A<11>


MEM_A_A<8>MEM_A_A<7>MEM_A_A<6>MEM_A_A<5>MEM_A_A<4>MEM_A_A<3>MEM_A_A<2>MEM_A_A<1>MEM_A_A<0>

MEM_A_DQS_P<7>

MEM_A_DQS_P<5>MEM_A_DQS_P<6>


MEM_A_DQS_P<2>


MEM_A_DQS_N<7>MEM_A_DQS_N<6>MEM_A_DQS_N<5>MEM_A_DQS_N<4>MEM_A_DQS_N<3>MEM_A_DQS_N<2>

MEM_A_DQS_N<0>MEM_A_DQS_N<1>

MEM_A_ODT<1>MEM_A_ODT<0>

MEM_A_CS_L<1>MEM_A_CS_L<0>

MEM_A_CKE<1>

MEM_A_CLK_N<1>MEM_A_CLK_P<1>

MEM_A_CKE<0>

MEM_A_CLK_N<0>MEM_A_CLK_P<0>

MEM_A_WE_LMEM_A_RAS_LMEM_A_CAS_L

MEM_A_BA<0>MEM_A_BA<1>MEM_A_BA<2>

MEM_A_DQ<62>MEM_A_DQ<63>

MEM_A_DQ<61>MEM_A_DQ<60>MEM_A_DQ<59>MEM_A_DQ<58>MEM_A_DQ<57>MEM_A_DQ<56>MEM_A_DQ<55>MEM_A_DQ<54>MEM_A_DQ<53>MEM_A_DQ<52>


MEM_A_DQ<49>MEM_A_DQ<48>MEM_A_DQ<47>MEM_A_DQ<46>MEM_A_DQ<45>MEM_A_DQ<44>


MEM_A_DQ<41>


MEM_A_DQ<38>MEM_A_DQ<37>MEM_A_DQ<36>


MEM_A_DQ<31>



MEM_A_DQ<26>









MEM_A_DQ<8>MEM_A_DQ<7>MEM_A_DQ<6>MEM_A_DQ<5>MEM_A_DQ<4>MEM_A_DQ<3>MEM_A_DQ<2>MEM_A_DQ<1>MEM_A_DQ<0> U1000

BD37

BF36

BA28

BE39

AU36

AV36

AT40

AU40

AY26

BB26

BB40

BC41

AG6

AJ6

AU6

AV9

AR6

AP8

AT13

AU13

BC7

BB7

BA13

BB11

AP11

BA7

BA9

BB9

AY13

AV14

AR14

AY17

AR19

BA14

AU14

AL6

BB14

BB17

BA45

AR43

AW48

BC48

BC45

AR45

AT48

AY48

AJ10

BA49

AV49

BB51

AY53

BB49

AU49

BA53

BB55

BA55

AV56

AJ8

AP50

AP53

AV54

AT54

AP56

AP52

AN57

AN53

AG56

AG53

AL8

AN55

AN52

AG55

AK56

AL7

AR11

AP6

AJ11

AL11

AR10

AR8

AY11

AV11

AU17

AT17

AW45

AV45

AV51

AY51

AT56

AT55

AK54

AK55

BG35

BB34

BE37

BA30

BC30

AW41

AY28

AU26

BE35

BD35

AT34

AU34

BB32

AT32

AY32

AV32

AY40

BA41

BD39

AT41

U1000

BG39

BD42

AT22

AV43

BA34

AY34

BA36

BB36

AR22

BF27

BE41

BE47

AL4

AL1

AV4

BA4

AU3

AR3

AY2

BA3

BE9

BD9

BD13

BF12

AN3

BF8

BD10

BD14

BE13

BF16

BE17

BE18

BE21

BE14

BG14

AR4

BG18

BF19

BD50

BF48

BD53

BF52

BD49

BE49

BD54

BE53

AK4

BF56

BE57

BC59

AY60

BE54

BG54

BA58

AW59

AW58

AU58

AK3

AN61

AN59

AU59

AU61

AN58

AR58

AK58

AL58

AG58

AG59

AN4

AM60

AL59

AF61

AH60

AR1

AU4

AT2

AM2

AL3

AV1

AV3

BE11

BG11

BD18

BD17

BE51

BG51

BA61

BA59

AR59

AT60

AK61

AK59

BF32

BE33

BD43

AT28

AV28

BD46

AT26

AU22

BD33

AU30

BD30

AV30

BG30

BD29

BE30

BE28

AT43

BG47

BF40

BD45

051-9276

2.7.0

12 OF 109

11 OF 72

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

BI

OUT

VCCIO_29

VCCIO_28

VCCIO_27

VCCIO_26

VCCIO_25

VCCIO_24

VCCIO_23

VCCIO_22

VCCIO_21

VCCIO_20

VCCIO_19

VCCIO_18

VCCIO_17

VCCIO_16

VCCIO_15

VCCIO_14

VCCIO_13

VCCIO_12

VCCIO_11

VCCIO_10

VCCIO_9

VCCIO_8

VCCIO_7

VCCIO_6

VCCIO_49

VCCIO_48

VCCIO_5

VCCIO_4

VCCIO_3

VCCIO_47

VCCIO_46

VCCIO_45

VCCIO_44

VCCIO_43

VCCIO_1

VCCIO_42

VCCIO_41

VCCIO_40

VCCIO_39

VCCIO_38

VCCIO_37

VCCIO_36

VCCIO_35

VCCIO_34

VCCIO_33

VCCIO_32

VCCIO_31

VCCIO_30

VCCIO_51

VCCIO_50

VCC_76

VCC_75

VCC_74

VCC_73

VCC_72

VCC_71

VCC_70

VCC_69

VCC_68

VCC_67

VCC_66

VCC_64

VCC_63

VCC_62

VCC_61

VCC_60

VCC_59

VCC_58

VCC_57

VCC_56

VCC_55

VCC_54

VCC_53

VCC_52

VCC_51

VCC_50

VCC_49

VCC_48

VCC_47

VCC_46

VCC_45

VCC_44

VCC_43

VCC_42

VCC_41

VCC_40

VCC_39

VCC_38

VCC_37

VCC_36

VCC_35

VCC_34

VCC_33

VCC_32

VCC_31

VCC_30

VCC_29

VCC_28

VCC_27

VCC_26

VCC_25

VCC_24

VCC_23

VCC_22

VCC_21

VCC_20

VCC_19

VCC_18

VCC_17

VCC_16

VCC_15

VCC_14

VCC_13

VCC_12

VCC_11

VCC_10

VCC_9

VCC_8

VCC_7

VCC_6

VCC_5

VCC_4

VCC_3

VCC_2

VCC_1

VCCIO_SEL

VCCPQE_1

VCCPQE_2

VIDALERT*

VIDSCLK

VIDSOUT

VCC_SENSE

VSS_SENSE

VCCIO_SENSE

VSS_SENSE_VCCIO

LINES

SENSE

SVID

QUIET

RAIL

PEG AND DDR

CORE SUPLLY

(6 OF 9)

(7 OF 9)

SENSE

LINE

1.8V

RAIL

SA RAIL

QUIET

RAIL

SENSE

LINE

DDR3-1.5V RAILS

GRPHICS

VDDQ_1

VDDQ_2

VDDQ_3

VDDQ_4

VDDQ_5

VDDQ_6

VDDQ_7

VDDQ_8

VDDQ_10

VDDQ_9

VDDQ_11

VDDQ_12

VDDQ_13

VDDQ_14

VDDQ_15

VDDQ_16

VDDQ_17

VDDQ_18

VDDQ_20

VDDQ_19

VDDQ_21

VDDQ_22

VDDQ_23

VDDQ_24

VDDQ_25

VDDQ_26

VCCDQ_1

VCCDQ_2

VDDQ_SENSE

VSS_SENSE_VDDQ

VCCSA_SENSE

VCCSA_VID_0

VCCSA_VID_1

SM_VREF

VAXG_1

VAXG_2

VAXG_4

VAXG_3

VAXG_5

VAXG_6

VAXG_7

VAXG_8

VAXG_9

VAXG_10

VAXG_11

VAXG_12

VAXG_13

VAXG_14

VAXG_15

VAXG_16

VAXG_17

VAXG_18

VAXG_19

VAXG_20

VAXG_21

VAXG_22

VAXG_23

VAXG_24

VAXG_25

VAXG_28

VAXG_26

VAXG_27

VAXG_30

VAXG_29

VAXG_33

VAXG_31

VAXG_32

VAXG_35

VAXG_34

VAXG_36

VAXG_37

VAXG_38

VAXG_39

VAXG_40

VAXG_41

VAXG_42

VAXG_43

VAXG_45

VAXG_44

VAXG_46

VAXG_47

VAXG_48

VAXG_49

VAXG_50

VAXG_51

VAXG_52

VAXG_53

VAXG_54

VAXG_55

VAXG_56

VAXG_SENSE

VSSAXG_SENSE

VCCPLL_1

VCCPLL_2

VCCPLL_3

VCCSA_2

VCCSA_1

VCCSA_3

VCCSA_4

VCCSA_5

VCCSA_6

VCCSA_7

VCCSA_8

VCCSA_9

VCCSA_10

VCCSA_11

VCCSA_12

VCCSA_13

VCCSA_15

VCCSA_14

VCCSA_16

Apple Inc.


124578

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6 3



For Future Compatibility

PLACEMENT NOTE: Please place all sense line resistors on BOTTOM side.


Note. VOLTAGE=0V

Note. VOLTAGE=1.05V

(IPU)

(NOT controlled by VCCIO_SEL)

(IPU)

Note. VOLTAGE=0V

Note. VOLTAGE=0V

Note. VOLTAGE=1.05V

Note. VOLTAGE=1.25V

Fixed at 1.05V

Note. VOLTAGE=0V

Note. VOLTAGE=1.05V


56 65

56 65

56 65

56 65

58 65

58 65

53

56 65

56 65

56 65

53

0 5%1/20W201 MF

MF0 5%1/20W201

1/20W 5% MF43

201

PLACE_NEAR=U1000.A44:38mm

201MF1/20W1%130

PLACE_NEAR=U1000.C44:2.54mm

10K

1/20W5%

MF201

NOSTUFF

201

1%75

MF1/20W

PLACE_NEAR=U7400.17:2.54mm

1%100

PLACE_SIDE=BOTTOMPLACE_NEAR=U1000.F45:50.8mm

MF-LF1/16W

402

1%PLACE_SIDE=BOTTOM

MF-LF1/16W

PLACE_NEAR=U1000.G45:50.8mm100

402

MF1/20W

1%100

201

PLACE_NEAR=U1000.U10:50.8mm

PLACE_SIDE=BOTTOMPLACE_NEAR=U1000.BC43:50.8mm 100

1%1/20W

MF201

PLACE_SIDE=BOTTOMPLACE_NEAR=U1000.BA43:50.8mm

201

1/20W1%

100

MF

201

5%10K

MF1/20W

201MF

5%1/20W

10K

1/20W5%1K

MF

201

PLACE_NEAR=U1000.AY43:2.54mm

MF1/20W

1K5%

201

PLACE_NEAR=U1000.AY43:2.54mm 10%16V

0201

0.1UF

X5R-CERM

PLACE_NEAR=U1000.AY43:2.54mm

PLACE_NEAR=U1000.AN16:50.8mmPLACE_SIDE=BOTTOM

1001%1/16WMF-LF402

100

PLACE_SIDE=BOTTOM1%

MF-LF1/16W

402

PLACE_NEAR=U1000.F43:50.8mm

PLACE_SIDE=BOTTOM 1%

MF-LF1/16W

402

100PLACE_NEAR=U1000.G43:50.8mmPLACE_SIDE=BOTTOM1%

MF-LF1/16W

100

402

PLACE_NEAR=U1000.AN17:50.8mm

IVY-BRIDGE

CRITICAL

OMIT_TABLE

BGA

2C-35W

CRITICAL

BGA

IVY-BRIDGE

2C-35W

OMIT_TABLE


CPU POWER

SYNC_MASTER=J11_MLB




=PP1V8_S0_CPU_VCCPLL_R


=PPVCORE_S0_CPU


CPU_VCCSA_VID<1>CPU_VCCSA_VID<0>

VOLTAGE=0.75VCPU_DDR_VREF

=PP1V5_S3_CPU_VCCDQ

CPU_VDDQ_SENSE_PCPU_VDDQ_SENSE_N

CPU_VCCSASENSE

CPU_AXG_SENSE_PCPU_AXG_SENSE_N

=PP1V05_S0_CPU_VCCPQE


CPU_DDR_VREF


=PPVCCSA_S0_CPU

CPU_VCCIOSENSE_P

CPU_VIDSOUT

=PPVCORE_S0_CPU=PPVCCSA_S0_CPU

=PP3V3_S0_CPU_VCCIO_SEL

CPU_VCCIOSENSE_N


CPU_VCCSENSE_N

CPU_VCCIO_SEL

CPU_VIDALERT_L_RCPU_VIDSCLK

CPU_VIDALERT_L

CPU_VCCSENSE_P

CPU_VIDSOUT_RCPU_VIDSCLK_R

R13111 2

R13121 2

R1310

1 2

R13021

2

R13201

2 R13001

2

R13701

2

R13711

2

R13821

2R13801

2

R13811

2R13141

2

R13131

2

R13301

2

R13311

2

C13301

2

R13621

2

R13601

2

R13611

2

R13631

2

U1000A26

A29

A31

A34

A35

A38

A39

A42

C26

C27

C32

C34

C37

C39

C42

D27

D32

D34

D37

D39

D42

E26

E28

E32

E34

E37

E38

F25

F26

F28

F32

F34

F37

F38

F42

G42

H25

H26

H28

H29

H32

H34

H35

H37

H38

H40

J25

J26

J28

J29

J32

J34

J35

J37

J38

J40

J42

K26

K27

K29

K32

K34

K35

K37

K39

K42

L25

L28

L33

L36

L40

N26

N30

N34

N38

F43

AA14

AA15

AB17

AB20

AC13

AD16

AD18

AD21

AE14

AE15

AF16

AF18

AF20

AF46

AG15

AG16

AG17

AG20

AG21

AG48

AG50

AG51

AJ14

AJ15

AJ17

AJ21

AJ25

AJ43

AJ47

AK50

AK51

AL14

AL15

AL16

AL20

AL22

AL26

AL45

AL48

AM16

AM17

AM21

AM43

AM47

AN20

AN42

AN45

AN48

BC22

AN16

W16

W17

AM25

AN22

A44

B43

C44

G43

AN17

U1000

AY43

AA46

AB47

AB50

AB51

AB52

AB53

AB55

AB56

AB58

AB59

AC61

AD47

AD48

AD50

AD51

AD52

AD53

AD55

AD56

AD58

AD59

AE46

N45

P47

P48

P50

P51

P52

P53

P55

P56

P61

F45

T48

T58

T59

T61

U46

V47

V48

V50

V51

V52

V53

V55

V56

V58

V59

W50

W51

W52

W53

W55

W56

W61

Y48

Y61

AM28

AN26

BB3

BC1

BC4

L17

L21

N16

N20

N22

P17

P20

R16

R18

R21

U10

U15

V16

V17

V18

V21

D48

D49

W20

AJ28

AJ33

AJ36

AJ40

AL30

AL34

AL38

AL42

AM33

AM36

AM40

AN30

AN34

AN38

AR26

AR28

AR30

AR32

AR34

AR36

AR40

AV41

AW26

BA40

BB28

BG33

BC43

BA43

G45

051-9276

2.7.0

13 OF 109

12 OF 72

7 9 10 12 14

7 9 12 15

7 14

7 9 10 12 14

7 9 12 14

7 10 12 15 26

53

12

7 15

7 14

7 9 12 15

12

7 10 12 15 26

7 12 15

7 9 12 14 7 12 15

7

(8 OF 9)VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS_NCTF

VSS_NCTF

VSS_NCTF

VSS_NCTF

VSS_NCTF

VSS_NCTF

VSS_NCTF

VSS_NCTF

VSS_NCTF

VSS_NCTF

VSS_NCTF

VSS_NCTF

VSS_NCTF

VSS_NCTF

(9 OF 9)VSS

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BGA

2C-35W

IVY-BRIDGE

OMIT_TABLE

CRITICAL

BGA

2C-35W

IVY-BRIDGE

OMIT_TABLE

CRITICAL

CPU GROUNDS

U1000A13

A17

A21

A25

A28

A33

A37

A40

A45

A49

A53

A9

AA1

AA13

AA50

AA51

AA52

AA53

AA55

AA56

AA8

AB16

AB18

AB21

AB48

AB61

AC10

AC14

AC46

AC6

AD17

AD20

AD4

AD61

AE13

AE8

AF1

AF17

AF21

AF47

AF48

AF50

AF51

AF52

AF53

AF55

AF56

AF58

AF59

AG10

AG14

AG18

AG47

AG52

AG61

AG7

AH4

AH58

AJ13

AJ16

AJ20

AJ22

AJ26

AJ30

AJ34

AJ38

AJ42

AJ45

AJ48

AJ7

AK1

AK52

AL10

AL13

AL17

AL21

AL25

AL28

AL33

AL36

AL40

AL43

AL47

AL61

AM13

AM20

AM22

AM26

AM30

AM34

AM38

AM4

AM42

AM45

AM48

AM58

AN1

AN21

AN25

AN28

AN33

AN36

AN40

AN43

AN47

AN50

AN54

AP10

AP51

AP55

AP7

AR13

AR17

AR21

AR41

AR48

AR61

AR7

AT14

AT19

AT36

AT4

AT45

AT52

AT58

AU1

AU11

AU28

AU32

AU51

AU7

AV17

AV21

AV22

AV34

AV40

AV48

AV55

AW13

AW43

AW61

AW7

AY14

AY19

AY30

AY36

AY4

AY41

AY45

AY49

AY55

AY58

AY9

BA1

BA11

BA17

BA21

BA26

BA32

BA48

BA51

BB53

BC13

BC5

BC57

BD12

BD16

BD19

BD23

BD27

BD32

BD36

BD40

BD44

BD48

BD52

BD56

BD8

BE5

BG9

U1000BG13

BG17

BG21

BG24

BG28

BG37

BG41

BG45

BG49

BG53

C29

C35

C40

D10

D14

D18

D22

D26

D29

D35

D4

D40

D43

D46

D50

D54

D58

D6

E25

E29

E3

E35

E40

F13

F15

F19

F29

F35

F40

F55

G48

G51

G6

G61

H10

H14

H17

H21

H4

H53

H58

J1

J49

J55

K11

K21

K51

K8

L16

L20

L22

L26

L30

L34

L38

L43

L48

L61

M11

M15

M4

M58

M6

N1

N17

N21

N25

N28

N33

N36

N40

N43

N47

N48

N51

N52

N56

N61

A5

A57

BC61

BD3

BD59

BE4

BE58

BG5

BG57

C3

C58

D59

E1

E61

P14

P16

P18

P21

P58

P59

P9

R17

R20

R4

R46

T1

T47

T50

T51

T52

T53

T55

T56

U13

U8

V20

V61

W13

W15

W18

W21

W46

W8

Y4

Y47

Y58

Y59

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CPU VCORE DECOUPLINGProcessor Load Line : -2.9 mOhms

PLACEMENT_NOTE (C1640-C1645):

CPU VCCPLL DECOUPLING

CPU VCCIO/VCCPQ DECOUPLING

CPU VCCPLL Low pass filter

PLACEMENT_NOTE (C1684-C167F):


Intel recommendation (Section 6.5): 26x 1uF, 10x 10uF, 2x 330uF

Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402

Note:The smallest 10mOhm available in the library are 0805s


Intel recommendation (section 6.4): 2x 1uF, 1x 330uF

Intel recommendation (Table 7-1): 16x 2.2uF, 12x 22uF, 3x 330uF

All INTEL recommendations from Intel doc #4439028 Huron River Platform Power Design Guide



0.010

MF0603

1%1/4W

PLACE_NEAR=U1000.BC1:2.54 mm:NO_VIA

1UF

X5R402

10%10V

X5R402

10%10V

1UF 1UF

X5R402

10%10V

CERM-X5R

10UF6.3V20%

0402-1

Place near U1000 on bottom sidePlace near U1000 on bottom side

10UF

CERM-X5R0402-1

20%6.3V

Place near U1000 on bottom side

10UF

CERM-X5R0402-1

20%6.3V


10UF

CERM-X5R0402-1

20%6.3V


10UF

CERM-X5R0402-1

20%6.3V

1UF

X5R402

10%10V


10UF

CERM-X5R0402-1

20%6.3V


10UF

CERM-X5R0402-1

20%6.3V


10UF

CERM-X5R0402-1

20%6.3V


10UF

CERM-X5R0402-1

20%6.3V

20%2V

CASE-B2-SMTANT

270UF

2VTANT

20%270UF

CASE-B2-SM

1UF

X5R402

10%10V

CERM-X5R6.3V

10UF20%

0402-1

CRITICAL

10UF6.3V20%

CERM-X5R0402-1

CRITICAL

20%270UF2VTANTCASE-B2-SM CASE-B2-SM

TANT

20%2V

270UF

CASE-B2-SM

2V20%

TANT

270UF

270UF

TANTCASE-B2-SM

2V20%

CASE-B2-SM

270UF

TANT

20%2V 2V

TANTCASE-B2-SM

270UF20%

2V20%

TANT

PLACE_NEAR=U1000.BC2:5mm

CASE-B2-SM

270UF

CASE-B2-SMTANT

270UF2V20%

10UF

0402-1

20%6.3V

CRITICAL

CERM-X5R

1UF

X5R402

10%10V

0402-1

20%

CRITICAL

6.3V

10UF

CERM-X5R

CRITICAL

6.3V

0402-1CERM-X5R

20%10UF

0402-1

CRITICAL

20%

CERM-X5R6.3V

10UF

CERM-X5R

CRITICAL

20%

0402-1

6.3V

10UF6.3V20%

CERM-X5R

CRITICAL

0402-1

10UF20%10UF6.3V

0402-1CERM-X5R

CRITICAL CRITICAL

CERM-X5R

20%

0402-1

6.3V

10UF6.3VCERM-X5R

CRITICAL

0402-1

20%10UF 10UF

CRITICAL

6.3V

0402-1CERM-X5R

20%

CRITICAL

6.3V

0402-1CERM-X5R

20%10UF

10VX5R

10%

402

1UF

Place on bottom side of U1000

10UF20%

CERM-X5R6.3V

0402-1

CRITICAL

0201

6.3VX5R

20%

CRITICAL

1UF

0201

20%6.3V

1UF

X5R

CRITICAL

0201

6.3V

1UF

X5R

20%

CRITICAL

0201

6.3V

1UF

X5R

20%

CRITICAL

0201

20%6.3VX5R

1UF

CRITICAL

0201

6.3VX5R

1UF20%

CRITICAL

0201

6.3V

1UF

X5R

20%

CRITICAL

0201

1UF

X5R

CRITICAL

20%6.3V

0201

6.3V

1UF20%

CRITICAL

X5R

CRITICAL

20%1UF

X5R0201

6.3V

CRITICAL

0201

20%6.3V

1UF

X5R

1UF

0201

20%6.3VX5R

CRITICAL

0201

6.3V

1UF

X5R

20%

CRITICAL

0201X5R

20%1UF

CRITICAL

6.3V20%6.3V

1UF

0201X5R

CRITICAL

0201

1UF6.3VX5R

20%

CRITICAL

6.3V

1UF20%

CRITICAL

0201X5R

X5R

Place on bottom side of U100.

1UF10%10V

402

CRITICAL

0201X5R6.3V

1UF20%

CRITICAL

0201

6.3VX5R

1UF20%

0201

CRITICAL

1UF6.3VX5R

20%1UF6.3V

0201X5R

20%

CRITICAL CRITICAL

1UF

X5R

20%

0201

6.3V

0201X5R6.3V

1UF20%

CRITICAL

0201

6.3V

1UF

X5R

20%

CRITICAL

0201

CRITICAL

6.3V

1UF

X5R

20%

0201

1UF20%

CRITICAL

6.3VX5R

0201X5R6.3V

1UF20%

CRITICAL


X5R402

10%10V

1UF

X5R6.3V20%

0201

1UF

CRITICAL

0201X5R6.3V

1UF20%

CRITICAL

20%

0201

6.3V

1UF

X5R

CRITICAL

0201

1UF20%6.3VX5R

CRITICAL

0201

6.3V

1UF

X5R

20%

CRITICAL

0201

6.3V

1UF

X5R

20%

CRITICAL

0201

CRITICAL

20%

X5R

1UF6.3V

X5R6.3V20%1UF

CRITICAL

0201

20%

X5R0201

6.3V

CRITICAL

1UF6.3VX5R

1UF20%

CRITICAL

0201

Place close to U1000 on top side.

CRITICAL

10UF20%6.3V

0402-1CERM-X5R CERM-X5R

20%

0402-1

CRITICAL

10UF6.3V


1UF

X5R402

10%10V

1UF

X5R402

10%10V

1UF

X5R402

10%10V

X5R402

10%10V

1UF

CRITICAL

1UF

X5R6.3V20%

0201 0201X5R

1UF20%6.3V

CRITICAL

0201

1UF

X5R6.3V20%

CRITICAL

6.3VX5R

1UF

CRITICAL

20%

0201

20%6.3VX5R

1UF

CRITICAL

0201

6.3V

0201

20%1UF

X5R

CRITICAL

1UF

X5R402

10%10V

1UF

X5R402

10V10%

1UF

X5R402

10%10V

1UF

X5R402

10%10V

1UF

X5R402

10%10V

1UF

X5R402

10%10V

1UF

X5R402

10%10V

1UF

X5R402

10%10V

1UF

X5R402

10%10V

X5R10V

1UF

402

10%1UF

X5R402

10%10V

1UF

X5R402

10%10V

1UF

X5R402

10%10V

1UF

X5R402

10%10V

1UF

X5R402

10%10V


10UF

CERM-X5R

20%6.3V

0402-1

0

402

5%

MF-LF1/16W

PLACE_NEAR=U1000.BB3:2.54 mm:NO_VIA

1UF

X5R402

10%10V

Place near U1000 on top side

CPU DECOUPLING-I


=PP1V8_S0_CPU_VCCPLL_R=PP1V8_S0_CPU_VCCPLL

=PP1V05_S0_CPU_VCCPQE


=PPVCORE_S0_CPU

R16011 2

C167F1

2

C16971

2

C161F1

2

C16981

2

C16991

2

C169A1

2

C169B1

2

C169C1

2

C16841

2

C16851

2

C16861

2

C16551

2

C16561

2

C16871

2

C16881

2

C16891

2

C16001

2

C16011

2

C16021

2

C16031

2

C16041

2

C16051

2

C169D1

2

C169E1

2

C169F1

2

C161A1

2

C161B1

2

C161C1

2

C161D1

2

C16901

2

C16911

2

C16921

2

C16931

2

C16941

2

C16951

2

C16961

2

R16001 2

C160X1

2

C160Y1

2

C161E1

2

C162A1

2

C162B1

2

C162C1

2

C162D1

2

C162E1

2

C167A1

2

C167B1

2

C167C1

2

C167D1

2

C16801

2

C16571

2

C16581

2

C16811

2

C16821

2

C16831

2

C167E1

2

C167G1

2

C167H1

2

C160Z1

2

C16791

2

C16591

2

C16601

2

C16611

2

C16621

2

C16631

2

C16641

2

C16651

2

C16661

2

C16671

2

C16681

2

C16691

2

C16701

2

C16061

2

C16071

2

C16081

2

C16091

2

C16101

2

C16111

2

C16121

2

C16131

2

C16141

2

C16151

2

C16161

2

C16171

2

C16181

2

C16191

2

C16201

2

C16211

2

C16221

2

C16231

2

C16241

2

C16251

2

C16261

2

C16271

2

C16281

2

C16291

2

C16301

2

C16311

2

C16321

2

C16331

2

C16341

2

C16351

2

C16361

2

C16371

2

C16381

2

C16391

2

C16401

2

C16411

2

C16421

2

051-9276

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CPU VCCSA DECOUPLING


Graphics Load Line : -3.9 mOhms


VAXG DECOUPLING

Intel recommendation (section 6.3): 18x 1uF(9 no-stuff), 10x 104F(2 no-stuff), 8x 22uF(2 no stuff), 4x 470uF(2 no-stuff)

Intel recommendation (Section 6.13): 10x 1uF, 8x 10uF, 1x 330uF


CPU VDDQ/VCCDQ DECOUPLING

Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402

Intel recommendation (Section 6.6): 3x 1uf, 3x 10uf, 1x 330uf




0603

0.010

1%

1/4W

MF


402X5R10V10%

1UF

CASE-B2-SM

270UF

TANT

20%2V

270UF

TANT2V20%

CASE-B2-SM

CERM-X5R

0402-1

20%

6.3V

10UF

CRITICAL CRITICAL

CERM-X5R

0402-1

6.3V

20%

10UF

0402-1

CERM-X5R

20%

10UF

6.3V

CRITICAL

6.3V

0402-1

CERM-X5R

CRITICAL

20%

10UF

0402-1

20%

6.3V

CERM-X5R

10UF

CRITICAL

10UF

CERM-X5R

6.3V

20%

0402-1

CRITICAL

Place close to U1000 on bottom side

10UF20%

CERM-X5R

6.3V

0402-1

22UF

CRITICAL

402

4VX5R

20%

AXG_ACOUSTICS:YES

6.3V


10UF

CERM-X5R

20%

0402-1 0402-1

20%

6.3V

CERM-X5R

10UF

Place close to U1000 on bottom sidePlace close to U1000 on bottom side

10UF

CERM-X5R

6.3V

20%

0402-1 0402-1

20%

6.3V

CERM-X5R

10UF

Place close to U1000 on bottom sidePlace close to U1000 on bottom side

10UF

CERM-X5R

6.3V

20%

0402-1

0402-1

20%

6.3V

CERM-X5R

10UF20%

6.3V

CERM-X5R

10UF

0402-1 0402-1

20%

6.3V

CERM-X5R

10UF

0402-1

20%

6.3V

CERM-X5R

10UF 10UF

CERM-X5R

6.3V

20%

0402-1

CASE-B2-SMTANT2V20%270UF

CASE-B2-SMTANT

20%2V

270UF

CASE-B2-SMTANT2V20%270UF


10UF

CERM-X5R

6.3V

20%

0402-1

6.3V

20%


10UF

CERM-X5R

0402-1

CRITICAL

AXG_ACOUSTICS:YES

20%

402

4VX5R

22UF20%4V

402

CRITICAL

X5R

22UF

AXG_ACOUSTICS:YES AXG_ACOUSTICS:YES

X5R4V

CRITICAL

20%22UF

402

20%4V

CRITICAL

22UF

402X5R

AXG_ACOUSTICS:YES AXG_ACOUSTICS:YES

CRITICAL

X5R402

22UF20%4V

AXG_ACOUSTICS:NO

CRITICAL

X5R-CERM10603

6.3V20%22UF 22UF

X5R-CERM10603

6.3V

AXG_ACOUSTICS:NO

20%

CRITICAL

0603

22UF

X5R-CERM1

AXG_ACOUSTICS:NO

CRITICAL

6.3V20%

0603

6.3VX5R-CERM1

AXG_ACOUSTICS:NO

22UF20%

CRITICAL

0603X5R-CERM1

AXG_ACOUSTICS:NO

6.3V

22UF20%

CRITICAL

0603X5R-CERM1

AXG_ACOUSTICS:NO

CRITICAL

20%22UF

6.3V

10V10%

1UF

402X5R


1UF

X5R402

10%10V 10V

402

1UF10%

X5R X5R

1UF10%10V

402

1UF

402

10VX5R

10% 10%10VX5R

1UF

402

10%

X5R402

10V

1UF

1UF10%

X5R10V

CRITICAL

402


X5R


10V

402

CRITICAL

10%1UF


1UF10%10V

402X5R

CRITICAL

10VX5R

10%

402

1UF

CRITICAL

X5R402

10V10%

CRITICAL

1UF

402X5R

1UF10%10V

CRITICAL

X5R

10%

10V

402

1UF

X5R10V10%1UF

CRITICAL

402

10%10VX5R402

1UF

CRITICAL

402X5R10V10%1UF

CRITICAL

X5R


1UF10%10V

402

10%

X5R

402

10V


1UF

X5R

1UF10%10V

402


X5R

10%

402

10V


1UF

10VX5R

10%1UF

402

10V10%

X5R402

1UF

CRITICALPlace on bottom side of U1000

X5R

1UF

402

10%10V

CRITICAL

1UF

10V


10%

X5R402

1UF

402X5R


10V10%


CPU DECOUPLING-II

SYNC_MASTER=K21_MLB


=PP1V5_S3_CPU_VCCDQ

=PPVCCSA_S0_CPU


R1702

1 2

C17571

2

C17381

2

C17391

2

C17401

2

C17271

2

C17411

2

C17421

2

C17431

2

C17441

2

C17451

2

C17461

2

C17471

2

C17001

2

C17011

2

C17021

2

C17041

2

C17051

2

C17061

2

C17071

2

C17081

2

C17091

2

C17581

2

C17591

2

C17601

2

C17611

2

C17621

2

C17101

2

C17031

2

C17561

2

C17681

2

C17111

2

C17121

2

C17131

2

C17141

2

C17151

2

C17161

2

C17481

2

C17491

2

C17511

2

C17521

2

C17531

2

C17551

2

C17631

2

C17641

2

C17651

2

C17661

2

C17671

2

C17231

2

C17241

2

C17251

2

C17541

2

C17501

2

C17281

2

C17291

2

C17301

2

C17311

2

C17321

2

C17171

2

C17181

2

C17191

2

C17201

2

C17211

2

C17221

2

051-9276

2.7.0

17 OF 109

15 OF 72

7 9 12

7 12

7 12

7 10 12 26

IN

OUT

OUT

BI

IN

IN

OUT

OUT

IN

IN

OUT

OUT

OUT

BI

OUT

BI

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

IN

IN

OUT

OUT

BI

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

IN

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

OUT

BI

BI

NC

NC

IHDA

(1 OF 10)

JTAG

SATA

LPC

RTC

SPI

HDA_SDIN2

HDA_SDIN0

HDA_SYNC

SPI_CS1*

JTAG_TMS

FWH0/LAD0

FWH1/LAD1

FWH2/LAD2

FWH3/LAD3

FWH4/LFRAME*

HDA_DOCK_EN*/GPIO33

HDA_DOCK_RST*/GPIO13

HDA_SDIN1

HDA_SDIN3

HDA_SDO

JTAG_TCK

JTAG_TDI

JTAG_TDO

LDRQ0*

LDRQ1*/GPIO23

RTCX2

SATA0GP/GPIO21

SATA0RXN

SATA0RXP

SATA0TXN

SATA0TXP

SATA1GP/GPIO19

SATA1RXN

SATA1RXP

SATA1TXN

SATA1TXP

SATA2RXN

SATA2RXP

SATA2TXN

SATA2TXP

SATA3COMPI

SATA3RBIAS

SATA3RCOMPO

SATA3RXN

SATA3RXP

SATA3TXN

SATA3TXP

SATA4RXN

SATA4RXP

SATA4TXN

SATA4TXP

SATA5RXN

SATA5RXP

SATA5TXN

SATA5TXP

SATAICOMPI

SATAICOMPO

SATALED*

SERIRQ

SPI_CLK

SPI_CS0*

SPI_MISO

SPI_MOSI

HDA_RST*

SPKR

RTCX1

HDA_BCLK

INTVRMEN

INTRUDER*

SRTCRST*

RTCRST*

IN

OUT

OUT

OUT

IN

C-LINK

SMBUS

PCI-E*

CLOCKS

FLEX

CLOCKS

(2 OF 10)

XTAL25_OUT

XTAL25_IN

XCLK_RCOMP

SML1DATA/GPIO75

SML1CLK/GPIO58

SML1ALERT*/PCHHOT*/GPIO74

SML0DATA

SML0CLK

SML0ALERT*/GPIO60

SMBDATA

SMBCLK

SMBALERT*/GPIO11

REFCLK14IN

PETP8

PETP7

PETP6

PETP5

PETP4

PETP3

PETP1

PETN8

PETN7

PETN6

PETN5

PETN4

PETN3

PETN2

PETN1

PERP8

PERP7

PERP6

PERP5

PERP4

PERP3

PERP1

PERN8

PERN6

PERN5

PERN4

PERN3

PERN2

PERN1

PEG_B_CLKRQ*/GPIO56

PEG_A_CLKRQ*/GPIO47

PCIECLKRQ7*/GPIO46

PCIECLKRQ6*/GPIO45

PCIECLKRQ5*/GPIO44

PCIECLKRQ4*/GPIO26

PCIECLKRQ3*/GPIO25

PCIECLKRQ2*/GPIO20

PCIECLKRQ1*/GPIO18

PCIECLKRQ0*/GPIO73

CL_RST1*

CL_DATA1

CL_CLK1

CLKOUT_PEG_B_P

CLKOUT_PEG_B_N

CLKOUT_PEG_A_P

CLKOUT_PEG_A_N

CLKOUT_PCIE7P

CLKOUT_PCIE7N

CLKOUT_PCIE6P

CLKOUT_PCIE6N

CLKOUT_PCIE5P

CLKOUT_PCIE5N

CLKOUT_PCIE4P

CLKOUT_PCIE4N

CLKOUT_PCIE3P

CLKOUT_PCIE3N

CLKOUT_PCIE2P

CLKOUT_PCIE2N

CLKOUT_PCIE1P

CLKOUT_PCIE1N

CLKOUT_PCIE0P

CLKOUT_PCIE0N

CLKOUT_ITPXDP_P

CLKOUT_ITPXDP_N

CLKOUT_DP_P

CLKOUT_DP_N

CLKOUT_DMI_P

CLKOUT_DMI_N

CLKOUTFLEX3/GPIO67

CLKOUTFLEX2/GPIO66

CLKOUTFLEX1/GPIO65

CLKOUTFLEX0/GPIO64

CLKIN_SATA_P

CLKIN_SATA_N

CLKIN_PCILOOPBACK

CLKIN_GND1_P

CLKIN_GND1_N

CLKIN_DOT_96P

CLKIN_DOT_96N

CLKIN_DMI_P

CLKIN_DMI_N

PERN7

PETP2

PERP2

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

IN

IN

OUT

OUT

IN

IN

OUT

OUT

IN

OUT

OUT

IN

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



(IPU-RSMRST#)

1.8V -> 1.1V

(IPD-PLTRST#)

(IPD-PWROK)

(IPD-PWROK)

(IPU)

(IPU)

(IPD-PWROK)

(IPU)

(IPD)

VSel strap not functional (VCCVRM = 1.8V)

(IPD)

(IPD-BOOT)

(IPD-BOOT)

(IPD)

(IPD)

(IPU)

(IPU)

(IPD)

(IPD-BOOT)

(IPU)

(IPU)

(IPU/IPD)

(IPU/IPD)

(IPD-PWROK)

(IPU-RSMRST#)

Unused clock terminations for FCIM Mode

Controlled by PCIECLKRQ5#

DOES THIS NEED LENGTH MATCH???

If HDA = S0, must also ensure that signal cannot be high in S3.Connect to ENET_MEDIA_SENSE via 12K R if HDA = 1.5V.Connect to ENET_MEDIA_SENSE via alias if HDA = 3.3V.

25 68

42 68

42 68

6 40 42

37 67

37 67

37 67

37 67

6 36 68

6 36 68

36 68

36 68

43 68

43 68

201

1/20W5%

MF

330K

1/20W5%

201MF

1M

1/20W5%

201MF

20K

1/20W5%

201MF

20K

PLACE_NEAR=U1800.AB10:2.54mm

1/20W1%

201MF

37.4

1/20W5%

201MF

10K

1/20W1%

201MF

90.9

PLACE_NEAR=U1800.AC49:2.54mm

43 68

43 68

16

23 68

23 68

23 68

1/20W5%

201MF

0

NO STUFF

NO STUFF

0

MF201

5%1/20W

1%1K

MF201

1/20W

25 68

25

1/20W

750

PLACE_NEAR=U1800.AH4:2.54mm

1%

201MF

PLACE_NEAR=U1800.AF12:2.54mm

MF

49.9

1/20W1%

201

23

8 23

6 36 68

6 36 68

16 36

16

16

43 68

43 68

10 65

10 65

8

8

16 67

16 67

16 67

16 67

16 67

16 67

16 67

25 68

16

8

8

8

8

16

33 68

33 68

16 35

4.7K2015% MF1/20W

1/20W5% MF

10K201

201

10KMF5% 1/20W

MF5% 1/20W 201

10K

10KMF 2015% 1/20W10KMF 2011/20W5%

201

10KMF1/20W5%

1/20W5%

10KMF 20110KMF 2015% 1/20W

MF 2015% 1/20W

10K

1/20W5% MF

10K201

10KMF 2015% 1/20W

10K5% 1/20W MF 201

2011/20W

10KMF5%

5%

10K201MF1/20W

201MF1/20W

10K5%

16 24

16

10KMF 2015% 1/20W

MF 2015% 1/20W

10K

PLACE_NEAR=U1800.F35:1.27mm33

MF 2015% 1/20W

PLACE_NEAR=U1800.K37:1.27mm 2015%

33MF1/20W

PLACE_NEAR=U1800.H35:1.27mm 201

33MF5% 1/20W

PLACE_NEAR=U1800.H37:1.27mm33

MF 2015% 1/20W

6 39 68

6 39 68

6 39 68

6 39 68

6 40 42 68

6 40 42 68

6 40 42 68

6 40 42 68

5%

33MF 2011/20W

201

33MF5% 1/20W33MF 2015% 1/20W33MF 2015% 1/20W

6 40 42 68 201

33MF5% 1/20W

10KMF 2015% 1/20W

5%

10KMF 2011/20W

201

10K5% 1/20W MF

1/20W

10KMF 2015%

10KMF 2015% 1/20W

MF 201

10K5% 1/20W

10KMF 2015% 1/20W

10KMF 2015% 1/20W10KMF 2015% 1/20W

QP8D-MM915462BGA

PCH-PPT-MB-SFF-ES1

OMIT_TABLE

42 68

42 68

23 68

19

6 39 68

QP8D-MM915462

PCH-PPT-MB-SFF-ES1

OMIT_TABLE

BGA

6.3V

0201-MURX5R

20%1.0UF

0201-MURX5R6.3V20%1.0UF

201

PLACE_NEAR=U1800.W49:5.1mm

1/20WMF

1%604

8

8

8

8

8 68

8 68

8

8

8

8

8

8

8

8

8

8

8

8

6 37 65

6 37 65

6 16 37

SYNC_MASTER=J13_MLB

PCH SATA/PCIe/CLK/LPC/SPI


PEGCLKRQB_L_GPIO56

=PP3V3_SUS_PCH_GPIO

=PP3V3_S0_PCH_GPIO

USB_EXTB_SEL_XHCI

SMBUS_PCH_ALERT_L

USB_EXTD_SEL_XHCI

EXCARD_CLKREQ_L

PEG_CLKREQ_L

TBT_CLKREQ_L

PEGCLKRQA_L_GPIO47

ENET_CLKREQ_L

JTAG_DPMUXUC_TRST_L

AP_CLKREQ_L

ITPCPU_CLK100M_P

ENET_MEDIA_SENSE_RDIV

SMBUS_PCH_ALERT_L

SMBUS_PCH_CLK

SMBUS_PCH_DATA

TP_CLINK_CLK

PCH_XCLK_RCOMP

SYSCLK_CLK25M_SB_R

PCH_CLK33M_PCIIN

SSD_CLKREQ_L

PCIE_CLK100M_TBT_P


PCH_CLK14P3M_REFCLK

PCIE_CLK100M_PCH_P

NC_PCIE_7_R2D_CN

SYSCLK_CLK32K_RTC

SATARDRVR_EN

DP_AUXCH_ISOL

PCH_SATALED_L

FW_CLKREQ_L

LPC_FRAME_R_L

XDP_DC3_PCH_GPIO19_SATARDRVR_EN

NC_PCIE_5_R2D_CN

PCH_SATAICOMP

TBT_CLKREQ_L



EXCARD_CLKREQ_L

JTAG_DPMUXUC_TRST_L

LPC_AD<1>

PCIE_ENET_D2R_P

PCIE_ENET_R2D_C_N

PCIE_AP_D2R_N

PCIE_AP_D2R_P

TP_SATA_F_D2RP

TP_SATA_F_R2D_CN

PCIE_ENET_R2D_C_P

PCIE_ENET_D2R_N

PCIE_EXCARD_D2R_P

PCIE_EXCARD_D2R_N

PCIE_FW_D2R_P

PCIE_FW_D2R_N

PCIE_FW_R2D_C_N

PCIE_FW_R2D_C_P

PCIE_EXCARD_R2D_C_N

LPC_FRAME_L

ITPCPU_CLK100M_N

HDA_RST_L

TP_HDA_SDIN2

HDA_SDIN0

HDA_SYNC_R

LPC_AD_R<0>

LPC_AD_R<1>

LPC_AD_R<2>

LPC_AD_R<3>

LPC_FRAME_R_L

ENET_MEDIA_SENSE_RDIV

TP_HDA_SDIN1

XDP_PCH_TCK

TP_LPC_DREQ0_L

TBT_PWR_EN_PCH

XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL

SATA_HDD_D2R_N

SATA_HDD_D2R_P

SATA_HDD_R2D_C_N

SATA_HDD_R2D_C_P

SATA_ODD_D2R_N

SATA_ODD_D2R_P

SATA_ODD_R2D_C_N

SATA_ODD_R2D_C_P

TP_SATA_C_D2RN

TP_SATA_C_D2RP

TP_SATA_C_R2D_CP

PCH_SATA3COMP

PCH_SATA3RBIAS

TP_SATA_D_D2RN

TP_SATA_D_D2RP

TP_SATA_D_R2D_CN

TP_SATA_D_R2D_CP

TP_SATA_E_D2RN

TP_SATA_E_R2D_CN

TP_SATA_F_D2RN

TP_SATA_F_R2D_CP

PCH_SATALED_L

LPC_SERIRQ

SPI_CLK_R

SPI_MOSI_R

HDA_RST_R_L

HDA_BIT_CLK_R

PCH_INTVRMEN_L

PCH_INTRUDER_L

PCH_SRTCRST_L

RTC_RESET_L

=PPVRTC_G3_PCH

HDA_BIT_CLK_R





PCH_CLK100M_SATA_N

PCH_CLK100M_SATA_P

PCH_CLKIN_GNDP1

PCH_CLKIN_GNDN1

PCIE_CLK100M_PCH_N

TP_PCH_CLKOUT_DPP

DMI_CLK100M_CPU_N

TP_PCIE_CLK100M_PEGAP

TP_PCIE_CLK100M_PEGAN

PEGCLKRQA_L_GPIO47

TP_CLINK_RESET_L

TP_CLINK_DATA

USB_EXTD_SEL_XHCI

SML_PCH_0_CLK

USB_EXTB_SEL_XHCI

PCIE_AP_R2D_C_P

PCIE_AP_R2D_C_N

NC_PCIE_7_R2D_CP

NC_PCIE_7_D2RN

NC_PCIE_8_D2RP

NC_PCIE_8_D2RN

LPC_AD<2>

LPC_AD<3>

PCH_CLK14P3M_REFCLK

PCH_CLK96M_DOT_N

PCH_CLK100M_SATA_P

PCIE_CLK100M_PCH_N

=PP3V3_S0_PCH

PCH_CLK96M_DOT_P

PCH_CLK100M_SATA_N

PCIE_CLK100M_PCH_P

PCH_CLKIN_GNDP1

PCH_SRTCRST_L

HDA_SDOUT

HDA_SYNC

HDA_BIT_CLK

TP_PCH_CLKOUT_DPN

DMI_CLK100M_CPU_P

PCH_CLK96M_DOT_N

PCH_CLK96M_DOT_P

NC_PCIE_6_R2D_CP

SYSCLK_CLK25M_SB SYSCLK_CLK25M_SB_R

PCH_SPKR

LPC_AD_R<3>RTC_RESET_L

PCH_SPKR

NC_PCIE_6_R2D_CN

NC_PCIE_6_D2RP

NC_PCIE_6_D2RN

PCIE_EXCARD_R2D_C_P

NC_PCIE_5_D2RP

NC_PCIE_5_D2RN

NC_PCIE_5_R2D_CP

LPC_AD_R<2>

SML_PCH_0_DATA

PCH_CLKIN_GNDN1

NC_PCIE_7_D2RP

LPC_AD_R<1>

LPC_AD_R<0>

=PP1V05_S0_PCH

PCIE_CLK100M_AP_N

PCIE_CLK100M_AP_P

AP_CLKREQ_L

PEG_CLKREQ_L

ITPXDP_CLK100M_N

PCIE_CLK100M_SSD_N

ITPXDP_CLK100M_P

PCIE_CLK100M_TBT_N

PEG_CLK100M_P

PEG_CLK100M_N

TP_PCIE_CLK100M_PEBP

PCIE_CLK100M_SSD_P

ENET_CLKREQ_L

TP_PCIE_CLK100M_PEBN

SSD_CLKREQ_L

PCIE_CLK100M_EXCARD_N

PCIE_CLK100M_EXCARD_P

FW_CLKREQ_L

NC_PCIE_8_R2D_CP

NC_PCIE_8_R2D_CN

PCIE_CLK100M_ENET_N

PCIE_CLK100M_ENET_P

PCIE_CLK100M_FW_N

PCIE_CLK100M_FW_P

PCH_INTVRMEN_L

PEGCLKRQB_L_GPIO56

SML_PCH_1_CLK

SML_PCH_1_DATA

LPC_AD<0>

HDA_SDOUT_R

HDA_RST_R_L

HDA_SYNC_R

TP_SATA_E_R2D_CP

TP_SATA_E_D2RP

TP_SATA_C_R2D_CN


XDP_PCH_TDO

XDP_PCH_TMS

TP_HDA_SDIN3

TP_SPI_CS1_L

XDP_PCH_TDI

SPI_MISO

PCH_INTRUDER_L

SPI_CS0_R_L

HDA_SDOUT_R

JTAG_ISP_TMS

R18001

2

R18011

2

R18021

2

R18031

2

R18301

2

R18201

2

R18901

2

R18401 2

R18411 2

R18861

2

R18321

2

R18311

2

R1877 1 2

R1878 1 2

R1834 1 2

R1842 1 2

R1869 1 2

R1844 1 2

R1845 1 2

R1847 1 2

R1814 2 1

R1815 1 2

R1843 1 2

R1833 1 2

R1879 1 2

R1846 1 2

R1853 1 2

R1848 1 2

R1854 1 2

R1855 1 2

R1812 1 2

R1813 1 2

R1810 1 2

R1811 1 2

R1861 1 2

R1862 1 2

R1863 1 2

R1864 1 2

R1860 1 2

R1891 1 2

R1892 1 2

R1893 1 2

R1894 1 2

R1895 1 2

R1896 1 2

R1897 1 2

R1870 1 2

R1871 1 2

U1800

A37

A39

C39

C37

K40

H35

K35

M35

F35

D36

B36

C35

A35

K37

H37

K22

C21

M17

U12

M12

M15

H40

F37

F19

A19

C19

M2

AN3

AN1

AU3

AU1

R1

AN6

AN8

AR3

AR1

AD4

AD2

AL3

AL1

AF12

AH4

AF10

AD8

AD6

AG3

AG1

AE3

AE1

AH8

AH6

AC3

AC1

AJ3

AJ1

AB12

AB10

W10

Y4

AD12

AB8

AB6

Y2

W8

N1

A23

U1800

L3

J1

M8

BD17

BF17

M24

K24

BB26

AY26

E51

AK8

AK6

BB24

AY24

AN10

AN12

AR12

AR10

AD48

AD50

AE49

AE51

AD40

AD42

AA49

AA51

Y48

Y50

AB40

AB42

AB44

AB46

W44

W46

AF44

AF46

AF40

AF42

H50

D48

G49

J51

M4

U8

T4

B8

M19

K8

J3

H4

R8

C4

BJ33

BJ35

BH36

BJ37

BJ39

BH40

BJ41

BJ43

BL33

BL35

BK36

BL37

BL39

BK40

BL41

BL43

BB30

BB33

BF33

BD35

AY35

BD37

AY37

AY40

AY30

AY33

BD33

BF35

BB35

BF37

BB37

BB40

J49

H12

F17

F10

H22

K12

A9

C9

D12

C11

AC49

W49

W51

C1802 1

2

C18031

2

R18851 2

051-9276

2.7.0

18 OF 109

16 OF 72

16

7 17 18 19

7 17 18 19 25 35

16 24

16

16

16

16

16 35

16

16

16

16 36

10 65

16

16

6

16 68

6 16 37

6

8

8

23 25

16

16

16

8

67

6

6

6

6

10 65

6

16 68

16

16

16

16

16

6

6

6

6

6

6

6

6

6

16

16 68

16 68

16

16

16

16

7 17 20

16 68

6

6

6

7 20 22

16

16

16

6

6

8

8

8

8

16 67

16 67

16 67

16 67

7 22

16 67

16 67

16 67

16

16

8

16 68

16

16 16

16

8

8

8

8

8

8

16

16

8

16

16

7 22

23 65

23 65

6

6

16

8

8

8

8

16

16

16 25 68

16 68

16 68

6

6 7 22

6

16

16 25 68

IN

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

IN

IN

OUT

OUT

IN

IN

OUT

OUT

IN

IN

OUT

OUT

OUT

IN

IN

OUT

IN

IN

IN

IN

IN

IN

IN

BI

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

FDI

(3 OF 10)

DMI

SYSTEM POWER

MANAGEMENT

DMI_ZCOMP

DMI3TXN

DMI2TXN

DMI1TXN

DMI0TXN

FDI_LSYNC1

DSWVRMEN

FDI_FSYNC1

FDI_FSYNC0

FDI_RXP5

FDI_RXP4

FDI_RXP3

FDI_RXP2

FDI_RXP1

FDI_RXP0

APWROK

CLKRUN*/GPIO32

DMI0RXN

DMI1RXN

DMI2RXN

DMI2RXP

DMI3RXN

DMI3RXP

DMI3TXP

DPWROK

DRAMPWROK

FDI_INT

FDI_LSYNC0

FDI_RXN0

FDI_RXN1

FDI_RXN2

FDI_RXN3

FDI_RXN4

FDI_RXN5

FDI_RXN6

FDI_RXN7

FDI_RXP6

FDI_RXP7

PMSYNCH

PWROK

SLP_A*

SLP_LAN*/GPIO29

SLP_S3*

SLP_S4*

SLP_S5*/GPIO63

SLP_SUS*

SUSACK*

SUSCLK/GPIO62

SUS_STAT*/GPIO61

SYS_PWROK

SYS_RESET*

WAKE*

RI*

BATLOW*/GPIO72

ACPRESENT/GPIO31

PWRBTN*

SUSWARN*/SUSPWRDNACK/GPIO30

RSMRST*

DMI1RXP

DMI0RXP

DMI_IRCOMP

DMI2RBIAS

DMI0TXP

DMI1TXP

DMI2TXP

(4 OF 10)

LVDS

DIGITAL DISPLAY INTERFACE

CRT

LVDSA_DATA0*

LVDSA_DATA1*

LVDSB_DATA3*

LVDSB_DATA2*

CRT_BLUE

CRT_DDC_CLK

CRT_DDC_DATA

CRT_GREEN

CRT_HSYNC

CRT_IRTN

CRT_RED

CRT_VSYNC

DAC_IREF

DDPB_0N

DDPB_0P

DDPB_1N

DDPB_1P

DDPB_2N

DDPB_2P

DDPB_3N

DDPB_3P

DDPB_AUXN

DDPB_AUXP

DDPB_HPD

DDPC_0N

DDPC_0P

DDPC_1N

DDPC_1P

DDPC_2N

DDPC_2P

DDPC_3N

DDPC_3P

DDPC_AUXN

DDPC_AUXP

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_HPD

DDPD_0N

DDPD_0P

DDPD_1N

DDPD_1P

DDPD_2N

DDPD_2P

DDPD_3N

DDPD_3P

DDPD_AUXN

DDPD_AUXP

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_HPD

LVDSA_CLK

LVDSA_CLK*

LVDSA_DATA2*

LVDSA_DATA3*

LVDSA_DATA0

LVDSA_DATA1

LVDSA_DATA3

LVDSB_CLK

LVDSB_CLK*

LVDSB_DATA0*

LVDSB_DATA1*

LVDSB_DATA0

LVDSB_DATA1

LVDSB_DATA2

LVDSB_DATA3

LVD_VREFH

LVD_VREFL

L_DDC_CLK

L_DDC_DATA

SDVO_CTRLCLK

SDVO_CTRLDATA

SDVO_INTN

SDVO_INTP

SDVO_STALLN

SDVO_STALLP

SDVO_TVCLKINN

SDVO_TVCLKINP

L_BKLTEN

L_VDD_EN

L_BKLTCTL

LVD_IBG

LVD_VBG

LVDSA_DATA2

L_CTRL_CLK

L_CTRL_DATA

NCNCNCNC

NCNC

NCNC

NCNC

NCNC

NCNC

NCNC

NCNC

NC

NCNC

NC

NC

NC

NCNC

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



(IPD-DeepS4/S5)

(IPU)

(IPU)

(IPU)

(IPD-PLTRST#)

(IPD-PLTRST#)

(IPD-PLTRST#)

(IPD-PLTRST#)

(IPD)

(IPD)

(IPD)

(IPD)

(IPD)

(IPD)

9 65

9 65

9 65

9 65

9 65

9 65

49.9

1/20W1%

201MF

PLACE_NEAR=U1800.BF19:12.7mm

9 65

9 65

9 65

9 65

9 65

9 65

9 65

9 65

9 65

9 65

9 65

9 65

9 65

9 65

9 65

1/20W5%

201

1K

MF

PLACE_NEAR=U1800.R51:2.54mm

750

MF

1%1/20W

201

PLACE_NEAR=U1800.BK20:2.54mm

390K

MF201

5%1/20W

1/20W5%

201MF

10K

0

MF201

5%1/20W

17 61

1/20W5%

201MF

100K

25 40

23 25 40

10 26 65

25

25

61

17 23 40

40 41 61

41

6 17 36

6 17 40 42

6 25 40 42

41 68

17 40 61

17 26 36 40 48 61

17 26 40 61

10 65

40

8

8

8

9 65

9 65

9 65

9 65

9 65

9 65

9 65

9 65

9 65

9 65

9 65

9 65

9 65

9 65

9 65

9 65

5% 2011/20W MF

100K

1/20W5% MF

1K201

1/20W5% 201

8.2KMF

1/20W5% 201MF

1K

5% 201MF

100K1/20W

5% 1/20W 201MF

100K

100K1/20W5% 201MF

10K

1/20W5%

201MF

5% MF

10K2011/20W

17 55

OMIT_TABLE

QP8D-MM915462BGA

PCH-PPT-MB-SFF-ES1 PCH-PPT-MB-SFF-ES1

OMIT_TABLE

QP8D-MM915462BGA

MF

5%100K1/20W

201

PCH DMI/FDI/PM/Graphics


SMC_ADAPTER_EN

TP_CRT_IG_GREEN

TP_CRT_IG_VSYNC

PCH_DAC_IREF

TP_DP_IG_B_MLN<0>

TP_DP_IG_B_MLN<1>

TP_DP_IG_B_MLN<2>

TP_DP_IG_B_MLP<2>

TP_DP_IG_B_MLN<3>

TP_DP_IG_B_MLP<3>

DPA_IG_AUX_CH_N

DPA_IG_AUX_CH_P

DPA_IG_HPD

TP_DP_IG_C_MLN<0>

TP_DP_IG_C_MLN<1>

TP_DP_IG_C_MLN<2>

TP_DP_IG_C_MLN<3>

TP_DP_IG_C_MLP<3>

DPB_IG_AUX_CH_N

DPB_IG_AUX_CH_P

DPB_IG_DDC_CLK

DPB_IG_DDC_DATA

DPB_IG_HPD

TP_DP_IG_D_MLN<0>

TP_DP_IG_D_MLP<0>

TP_DP_IG_D_MLP<1>

TP_DP_IG_D_MLN<2>

TP_DP_IG_D_MLN<3>

TP_DP_IG_D_MLP<3>

TP_DP_IG_D_AUXN

TP_DP_IG_D_AUXP

TP_DP_IG_D_CTRL_CLK

TP_DP_IG_D_CTRL_DATA

TP_DP_IG_D_HPD

DPA_IG_DDC_CLK

TP_SDVO_STALLN

TP_SDVO_STALLP

TP_SDVO_TVCLKINN

MEM_VDD_SEL_1V5_L

PM_CLK32K_SUSCLK_R

FDI_DATA_P<6>

FDI_DATA_P<7>

FDI_DATA_P<5>

FDI_FSYNC<1>

FDI_LSYNC<1>

FDI_LSYNC<0>

=PPVRTC_G3_PCH

DMI_S2N_N<3>

DMI_S2N_N<1>

DMI_S2N_N<0>

PCH_DSWVRMEN

PM_PCH_APWROK

PM_CLKRUN_L

DMI_N2S_N<0>

DMI_N2S_N<1>

DMI_N2S_N<2>

DMI_N2S_P<2>

DMI_N2S_N<3>

DMI_N2S_P<3>

PM_MEM_PWRGD

FDI_DATA_N<1>

FDI_DATA_N<3>

FDI_DATA_N<4>

FDI_DATA_N<6>

PM_SYNC

PM_PCH_PWROK

TP_PM_SLP_A_L

PM_SLP_S3_L

PM_SLP_S4_L

PM_SLP_S5_L

PM_SLP_SUS_L

PCH_SUSACK_L

LPC_PWRDWN_L

PM_PCH_SYS_PWROK

PM_SYSRST_L

PCIE_WAKE_L

PM_BATLOW_L

PM_RSMRST_L

DMI_N2S_P<0>

DMI_S2N_P<1>

PM_DSW_PWRGD

FDI_DATA_P<0>

DMI_S2N_N<2>

DMI_S2N_P<2>

PCH_DMI2RBIAS

PCH_RI_L

FDI_FSYNC<0>

FDI_DATA_P<4>

FDI_DATA_N<7>

FDI_DATA_P<3>

FDI_DATA_P<2>

FDI_DATA_P<1>

FDI_DATA_N<5>

TP_CRT_IG_BLUE

TP_CRT_IG_RED

TP_CRT_IG_DDC_CLK

TP_CRT_IG_HSYNC

=PP3V3_S0_PCH_GPIO

=PP3V3_S5_PCH

=PP3V3_SUS_PCH_GPIO

PCH_SUSACK_L

TP_CRT_IG_DDC_DATA

TP_DP_IG_D_MLN<1>

TP_DP_IG_D_MLP<2>

TP_SDVO_TVCLKINP

DPA_IG_DDC_DATA

TP_SDVO_INTP

LVDS_IG_BKL_PWM

LVDS_IG_BKL_ON

LVDS_IG_PANEL_PWR

TP_DP_IG_B_MLP<1>

TP_DP_IG_B_MLP<0>

TP_DP_IG_C_MLP<2>

TP_DP_IG_C_MLP<1>

TP_DP_IG_C_MLP<0>

TP_SDVO_INTN

FDI_DATA_N<2>

FDI_DATA_N<0>

=PP3V3_SUS_PCH_GPIO

=PP1V05_S0_PCH_VCCIO_PCIE

DMI_S2N_P<3>

DMI_S2N_P<0>

PCH_DMI_COMP

PCH_SUSWARN_L

PM_PWRBTN_L

=PP3V3_SUS_PCH_GPIO

PCH_SUSWARN_L

PM_CLKRUN_L

PM_SLP_S4_L

MEM_VDD_SEL_1V5_L

FDI_INT

PM_SLP_S3_L

PM_SLP_S5_L

PM_SLP_SUS_L

PCIE_WAKE_L

PM_PWRBTN_L

DMI_N2S_P<1>

R19001

2

R19511

2

R19201

2

R19151

2

R19051

2

R198612

R19091

2

R1923 2 1

R1925 1 2

R1991 1 2

R1985 1 2

R1922 2 1

R1921 2 1

R1924 2 1

R19831

2

R1982 1 2

U1800

H19

G3

H10

T2

BL21

BJ21

BD22

BF22

BL23

BJ23

BB22

AY22

BK20

BJ19

BL19

BB19

AY19

BL17

BJ17

BB17

AY17

BD19

BF19

A21

B12

F22

BH12

BK8

BB10

BK12

BH8

BL13

BJ15

BD12

BJ11

AY15

AY12

BJ9

BF10

BJ13

BL15

BF12

BL11

BB15

BB12

BL9

BD10

BB8

K19

M22

F12

B20

C7

A7

D4

K10

F6

A15

G6

F15

D3

C13

M10

L1

D8

U1800

M46

R49

N49

R46

M50

T48

U46

N51

R51

AY48

AY50

AY44

AY46

BB44

BB46

BA49

BA51

AW51

AW49

AY42

BC49

BC51

BD48

BD50

BF46

BF45

BE49

BE51

AU51

AU49

T50

U44

BE46

BG51

BG49

BF42

BD42

BJ47

BL47

BL45

BJ45

AU46

AU44

M48

U42

BK44

L49

M44

R42

M40

L51

K46

M42

AH42

AH40

AG51

AG49

AK46

AK44

AR44

AR46

AN51

AN49

AN46

AN44

AK42

AK40

AH44

AH46

AM48

AM50

AL51

AL49

AJ49

AJ51

AH48

AH50

W42

R44

AT50

AT48

AR51

AR49

AU40

AU42

R19551

2

051-9276

2.7.0

19 OF 109

17 OF 72

6

6

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

6

6

6

7 16 20

17

6

6

6

6

7 16 18 19 25 35

7

7 16 17 18 19

17

6

6

8

6

8

8

8

8

8

6

7 16 17 18 19

7

17

7 16 17 18 19

17

6 17 40 42

17 26 36 40 48 61

17 55

17 26 40 61

17 40 61

17 61

6 17 36

17 23 40

NC

NCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNC

NCNC

NC

NC

NCNCNCNCNCNCNCNCNCNCNCNCNCNC

NCNC

NC

NCNCNC

NCNCNC

NCNCNC

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

IN

OUT

OUT

IN

IN

OUT

OUT

IN

IN

OUT

OUT

IN

IN

OUT

OUT

OUT

IN

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

OUT

IN

BI

IN

(5 OF 10)

USB

PCI

PME*

PLTRSTB*

PIRQA*

TP2

TP5

TP4

TP11

USB3RN4

USB3RN2

CLKOUT_PCI0

CLKOUT_PCI1

CLKOUT_PCI2

CLKOUT_PCI3

CLKOUT_PCI4

GNT1*/GPIO51

GNT2*/GPIO53

GNT3*/GPIO55

OC0*/GPIO59

OC1*/GPIO40

OC2*/GPIO41

OC3*/GPIO42

OC4*/GPIO43

OC5*/GPIO9

OC6*/GPIO10

OC7*/GPIO14

PIRQB*

PIRQC*

PIRQD*

PIRQE*/GPIO2

PIRQF*/GPIO3

PIRQG*/GPIO4

PIRQH*/GPIO5

REQ1*/GPIO50

REQ2*/GPIO52

REQ3*/GPIO54

RSVD

TP1

TP3

TP6

TP7

TP8

TP9

TP10

TP12

TP13

TP14

TP15

TP16

TP17

TP18

TP19

TP20

TP21

TP22

TP23

TP24

TP41

TP42

USB3RN1

USB3RN3

USB3RP1

USB3RP2

USB3RP3

USB3RP4

USB3TN1

USB3TN2

USB3TN3

USB3TN4

USB3TP1

USB3TP2

USB3TP3

USB3TP4

USBP0N

USBP0P

USBP10N

USBP10P

USBP11N

USBP11P

USBP12N

USBP12P

USBP1N

USBP1P

USBP2N

USBP2P

USBP3N

USBP3P

USBP4N

USBP4P

USBP5N

USBP5P

USBP6N

USBP6P

USBP7N

USBP7P

USBP8N

USBP8P

USBP9N

USBP9P

USBRBIAS

USBRBIAS*

USBP13P

USBP13N

NC

NC

BI

BI

BI

OUT

OUT

OUT

OUT

Apple Inc.


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6 3



Redundant to pull-down on audio page

Redundant to pull-up on audio page

(IPU-PCIERST#)

(IPU)

(IPD)

(IPD)

Unused

RSVD: WiFi

RSVD: SD

RSVD: BT (HS)

Camera

USB Hub (All LS/FS Devices)

Ext B (EHCI)

Ext D (EHCI)

Unused

Unused

Ext D (XHCI) (Mobiles: Trackpad?)

Ext C (XHCI/EHCI)

Ext B (XHCI)

Ext A (XHCI/EHCI)

24 67

24 67

8

8

24 67

24 67

8

8

24 67

24 67

24 67

24 67

38 67

38 67

38 67

38 67

39 67

39 67

39 67

39 67

8

8

8

8

8

8

8

8

5% 201MF

10K1/20W

10KMF 2015% 1/20W

10KMF5% 1/20W 20110K

2011/20W MF5%

5% 201MF

10K1/20W

NO STUFF

201

10KMF5% 1/20W

1/20W5% 201MF

10K1/20W5% 201MF

10K

1/20W5% 201

10KMF

1/20W5% MF

10K201

10KMF 2015% 1/20W

NO STUFF

1/20W 201

10K5% MF

18

18

18

18

6 18 39

18 33

6 18 39

10KMF 2015% 1/20W10KMF 2015% 1/20W

2015% 1/20W MF

10K

10KMF 2015% 1/20W

1/20W5% 201MF

10KNO STUFF

10KMF 2015% 1/20W

18 23

18 23

18 23

18 23

18 23

23

23

38 67

23

OMIT_TABLE

QP8D-MM915462

PCH-PPT-MB-SFF-ES1BGA

38 67

6 39 67

6 39 67

PLACE_NEAR=U1800.A33:2.54mm

22.6

1/20WMF201

1%25 26

25 68

25 68

25 68


PCH PCI/USB/TP/RSVD

JTAG_GMUX_TMS

PCH_GPIO54

AUD_IP_PERIPHERAL_DET

TBT_PWR_REQ_L

AUD_I2C_INT_L

USB3_EXTC_TX_P

PCI_INTB_L

BLC_I2C_MUX_SEL

TP_PCH_STRP_ESI_L

PCH_STRP_TOPBLK_SWP_L

USB_EXTB_EHCI_P

USB_EXTD_EHCI_N

AP_PWR_EN

BLC_GPIO

XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L

TP_USB_WLANP

TP_USB_WLANN

TP_PCH_STRP_BBS1

USB_EXTA_P

USB_EXTA_N

USB_EXTB_XHCI_P

USB_EXTB_XHCI_N

USB_EXTC_N

USB_EXTC_P

USB_EXTD_XHCI_N

USB_EXTD_XHCI_P

TP_USB_4N

TP_USB_4P

TP_USB_SDN

TP_USB_SDP

XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L

XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L

XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L

XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L

XDP_DB0_PCH_GPIO43_USB_EXTB_OC_EHCI_L

XDP_DB1_PCH_GPIO9_USB_EXTD_OC_EHCI_L

XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE

XDP_DB2_PCH_GPIO10_AP_PWR_EN

PCH_USB_RBIAS

TP_USB_13N

TP_USB_13P

USB_EXTD_EHCI_P

USB_EXTB_EHCI_N

USB_CAMERA_N

USB_CAMERA_P

USB_HUB_UP_N

USB_HUB_UP_P

TP_USB_12P

TP_USB_BT_HSN

TP_USB_BT_HSP

TP_USB_12N

TP_PCH_TP23

USB3_EXTC_RX_N

USB3_EXTB_RX_N

USB3_EXTA_RX_N

USB3_EXTA_RX_P

USB3_EXTB_RX_P

USB3_EXTD_RX_P

USB3_EXTC_RX_P

USB3_EXTA_TX_N

USB3_EXTB_TX_N

USB3_EXTC_TX_N

USB3_EXTD_TX_N

USB3_EXTB_TX_P

USB3_EXTA_TX_P

USB3_EXTD_TX_P

PCI_INTC_L

=PP3V3_S0_PCH_GPIO

PCI_INTA_L

PCI_INTD_L

LPC_CLK33M_SMC_R

TP_PCI_CLK33M_OUT2

TP_PCI_CLK33M_OUT3

LPC_CLK33M_LPCPLUS_R

PCH_CLK33M_PCIOUT

TP_PCI_PME_L

PLT_RESET_L

BLC_GPIO

USB3_EXTD_RX_N

PCH_GPIO54

BLC_I2C_MUX_SEL

JTAG_GMUX_TMS


XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE

AUD_I2C_INT_L

TBT_PWR_REQ_L




=PP3V3_S3_PCH_GPIO

=PP3V3_S0_PCH_GPIO

=PP3V3_SUS_PCH_GPIO

R20701

2

R2067 2 1

R2068 1 2

R2061 1 2

R2062 1 2

R2033 1 2

R2060 1 2

R2030 1 2

R2018 1 2

R2016 1 2

R2017 1 2

R2014 1 2

R2031 1 2

R2010 1 2

R2011 1 2

R2012 1 2

R2013 1 2

R2054 2 1

R2069 1 2

U1800

G51

E49

H48

J43

G45

F42

H42

D44

C17

A17

A13

D16

A11

B16

C23

H15

D49

C48

C47

C45

A47

C41

F45

F40

F7

H2

G46

K44

F46

AU6

AU8

BB6

BC1

BC3

BD2

BD4

BE1

BE3

BE6

BF6

BF7

AW1

BG1

BG3

BH3

BH4

BJ4

BJ5

BJ7

BK6

BL5

AW3

AY2

AY4

AY6

AY8

BA1

BA3

BH24

D20

M30

E3

AM4

AT4

AT2

AD10

B24

D24

AD44

BK24

AD46

BJ48

BL7

W40

K30

BH20

BK16

BH49

BB42

BH16

AN42

AN40

AR40

AR42

BJ25

BJ27

BJ31

BJ29

BL25

BL27

BL31

BL29

BF26

BB28

BF28

BF30

BD26

AY28

BD28

BD30

F24

H24

C31

A31

H33

F33

H30

F30

M33

K33

C25

A25

C27

A27

H28

F28

M26

K26

D28

B28

H26

F26

D32

B32

M28

K28

C29

A29

A33

C33

051-9276

2.7.0

20 OF 109

18 OF 72

23 36 61

18

18 23

67

7 16 17 18 19 25 35

6

6

18

18

18

18 23

18 23

6 18 39

18 33

6 18 39

18 23

18 23

7 25

7 16 17 18 19 25 35

7 16 17 19

OUTOUT

BI

IN

NC

IN

OUT

OUT

OUT

IN

BI

IN

IN

OUT

OUT

IN

OUT

OUT

OUT

OUT

BI

IN

OUT

NCTF

CPU/MISC

(6 OF 10)

GPIO

GPIO1

GPIO6

VSS_NCTF

VSS_NCTF

TS_VSS4

TS_VSS3

TS_VSS2

TS_VSS1

THRMTRIP*

STP_PCI*/GPIO34

SATA3GP/GPIO37

SATA2GP/GPIO36

RCIN*

PROCPWRGD

PECI

NC_1

INIT3_3V*

GPIO71

GPIO70

GPIO69

GPIO68

GPIO35

GPIO8

GPIO7

DF_TVS

A20GATE

GPIO24

GPIO27

GPIO28

BMBUSY*/GPIO0

LAN_PHY_PWR_CTRL/GPIO12

GPIO15

SATA4GP/GPIO16

GPIO17

SCLOCK/GPIO22

SLOAD/GPIO38

SDATAOUT0/GPIO39

SDATAOUT1/GPIO48

SATA5GP/GPIO49

GPIO57

D SG

D

GS

D SG

OUT IN

IN OUT

IN OUT

NC

08

NC

OUT

NC

08OUT

NC

IN

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REVISION

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6 3




TABLE_BOMGROUP_ITEM

(TBT_CIO_PLUG_EVENT_ISOL)

JTAG Isolation due to glitch in and out of sleep

NOTE: TCK from PCH is Push-Pull CMOSNOTE: TMS/TDI from PCH is Open Drain

TBT_PWR_EN goes high for JTAG Programming

NOTE: TDO from CR is Push-Pull CMOS

This has internal pull up and should not pulled low.

Systems with chip-down memory should add pull-downs on another page and set straps per software.

(IPU-RSMRST#)

Systems with no chip-down memory should pull all 4 RAMCFG GPIOs high.

(IPD-PLTRST#)

(IPD-PLTRST#)

(IPU-RSMRST#)

(IPD-PLTRST#?)

(IPU)

THIS SIGNAL IS INTENDED FOR FIRMWARE HUB AND WE ARE NOT USING IT.

(IPU-DeepS4/S5)

(IPU)

(IPD)

DF_TVS:DMI & FDI Term Voltage

Set to Vss when Low

Set to Vcc when High

Must stuff R2197 when R2180 NO STUFFed.

Stuff R2160 or R2574, not both

10 23 65 23

6 19 42

19

MF

NO STUFF

1K

201

5%1/20W

19

23

19

23

19

6 19 42 49

10 41 65

RAMCFG3:H

10K

MF201

5%1/20W 1/20W

5%

201MF

10K

RAMCFG2:H

10K

MF201

5%1/20W

RAMCFG1:H RAMCFG0:H

10K

MF201

5%1/20W

19 40

8 23

19

19 40

19 5%1/20W

201MF

1K

1/20W5%

201MF

2.2K

MF

20K1/20W5% 201

1/20W5% 201MF

100K

1/20W5% 201MF

10K

2011/20W5% MF

10K

2011/20W5% MF

100K

10KMF1/20W5% 201

10K5% 1/20W MF 201

MF5% 1/20W 201

10KNO STUFF

1/20W MF5%

100K201

MF

10K5% 2011/20W

1/20W

10K5% 201MF

1/20W

10KMF5% 201

NO STUFF

1/20W5% 201MF

10K

23 5% 1/20W

0

MF 201

35

19 23

201

10K1/20W5% MF

2011/20W5% MF

10K

2011/20W5% MF

10K

5% 1/20W 201MF

10K

1/20W5%201MF

43NO STUFF

0

MF 2015% 1/20W

1/20W5%201MF

390

10 41 65

23

19

OMIT_TABLE

PCH-PPT-MB-SFF-ES1

QP8D-MM915462BGA

SSM6N15AFE

CRITICAL

SOT563

SSM3K15FVSOD-VESM-HF

CRITICAL

SSM6N15AFE

CRITICAL

SOT563

19

5%

201MF

10K

1/20W1/20W5%

201MF

10K

33

1/20W5%

201MF

10K

1/20W5%

201MF

10K

10K

1/20W5%

201MF

10K5%1/20WMF201

19 33

16 33

X5R-CERM16V10%

0.1UF

0201SOT891

74LVC1G08CRITICAL

201

1/20W5%

MF

10K

33

74LVC1G08CRITICALSOT891

23

16VX5R-CERM

10%

0.1UF

0201

10K

1/20W5%

201MF

NO STUFF

10K

MF201

5%1/20W

33

RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:HRAMCFG_SLOT

PCH GPIO/MISC/NCTFSYNC_MASTER=J13_MLB SYNC_DATE=02/23/2012

=PP3V3_S5_PCH_GPIO

=PP3V3_SUS_PCH_GPIO

=PP3V3_S0_PCH_GPIO

XDP_FC1_PCH_GPIO0

LPCPLUS_GPIO

TBT_SW_RESET_R_L

WOL_EN

AUD_IPHS_SWITCH_EN_PCH

JTAG_ISP_TDI

=PP3V3_S0_PCH_GPIO

=PP3V3_S0_PCH_GPIO

JTAG_TBT_TCKTBT_PWR_EN

JTAG_ISP_TCK

ENET_LOW_PWR_PCH


CPU_PROC_SEL_L

=PP3V3_S0_PCH_GPIO

MLB_RAMCFG1

CPU_PECI

CPU_PWRGD

PM_THRMTRIP_L

PCH_INIT3V3_L

PCH_RCIN_L

PCH_PROCPWRGD

PCH_A20GATE

PCH_PECI

XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL

SPIROM_USE_MLB

TBT_SW_RESET_L

MLB_RAMCFG3

PM_THRMTRIP_L_R

FW_PWR_EN_PCH

TBT_SW_RESET_R_L

SMC_WAKE_SCI_L

LPCPLUS_GPIO

WOL_EN

XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH

XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL

JTAG_ISP_TDO

FW_PWR_EN_PCH

TBT_GO2SX_BIDIR

SPIROM_USE_MLB

MLB_RAMCFG2

PCH_DF_TVS



=PP3V3_TBT_PCH_GPIO

=PP3V3_TBT_PCH_GPIO

JTAG_ISP_TDO


JTAG_TBT_TDO

JTAG_TBT_TMS

SMC_RUNTIME_SCI_L

PCH_A20GATE

ODD_PWR_EN_L

DPMUX_UC_IRQ

JTAG_TBT_TDI

JTAG_ISP_TMS

PCH_RCIN_L

SMC_WAKE_SCI_L

TBT_GO2SX_BIDIR

FW_PME_L

=PP3V3_TBT_PCH_GPIO

MLB_RAMCFG0

TBT_CIO_PLUG_EVENT

TBT_CIO_PLUG_EVENT_ISOL

JTAG_ISP_TDI

XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK

XDP_DC1_PCH_GPIO35_MXM_GOOD

XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L

ODD_PWR_EN_L

XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH

XDP_FC0_PCH_GPIO15

TP_PCH_GPIO8

SMC_RUNTIME_SCI_L

DPMUX_UC_IRQ

FW_PME_L

XDP_FC1_PCH_GPIO0

R21301

2

R21721

2

R21731

2

R21741

2

R21751

2

R217812

R21791

2

R2111 2 1

R2195 2 1

R2191 1 2

R2192 1 2

R2193 1 2

R2194 1 2

R2184 1 2

R2197 1 2

R2190 1 2

R2196 1 2

R2185 1 2

R2160 1 2

R2112 2 1

R2180 1 2

R2198 2 1

R2116 2 1

R2150 1 2

R2155 1 2

R2170 1 2

R2140 1 2

R2156 1 2

U1800

U3

W1

BC7

B40

K6

B44

K15

C15

G1

W12

K17

C43

K42

A43

A45

D40

A41

H17

R6

C5

U40

AU12

AU10

U6

W6

M6

AA3

AA1

W3

U10

U1

N3

R3

BC9

AK10

AH12

AK12

AH10A4

A5

BJ51

BL1

BL3

BL4

BL48

BL49

BL51

C3

C49

C51

A48

D1

D51

E1

A49

A51

BH1

BH51

BJ1

BJ3

BJ49

Q21606

21

Q2162

3

12

Q2160

3

54

R21621

2

R21861

2

R21611

2

R21991

2

R21881

2

R21631

2

C2113 1

2

U21002

1

3

6

4

R21131

2

U21012

1

3

6

4

C2114 1

2

R21661

2

R21671

2

051-9276

2.7.0

21 OF 109

19 OF 72

5

5

7

7 16 17 18

7 16 17 18 19 25 35

19 23

6 19 42

19

19

23 25

7 16 17 18 19 25 35

7 16 17 18 19 25 35

25 33

23

8

7 20 22

10

7 16 17 18 19 25 35

8

19

19

19 23

8

41

19

19

19 33

6 19 42 49

8

7 19

7 19

7 19

7 19

7 19

19 40

19

19

19

19

19 40

19 33

19

7 19

8

19 23

NC

NC

VCC CORE

LVDS

(7 OF 10)

DMI

DFT/SPI

CRT

FDI

VCCIO

VCCCORE

VCC3_3

VCCADAC

VCCADMI_VRM

VCCAFDIPLL

VCCAFDI_VRM

VCCALVDS

VCCDFTERM

VCCDMI

VCCIO

VCCSPI

VCCTX_LVDS

VSSALVDS

VSSA_DAC

VCCAPLLEXP

VCCACLK

V_PROC_IO

VCCCLKDMI

VCCRTC

DCPSUSBYP

VCCDSW3_3

VCCAPLLDMI2

DCPRTC

VCCADPLLB

VCCADPLLA

VCCDIFFCLKN

DCPSST

V5REF

V5REF_SUS

VCCAPLL_SATA3

VCCASW

VCCIO

VCCPUSB

VCCSSC

VCCSUS3_3

VCCSUSHDA

VCCVRM

DCPSUS

USB

SATA

PCI/GPIO/LPC

(8 OF 10)

HDA

CLK/MISC

CPU

RTC

NC

NCNC

NCNC

NCNC

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6 3



AL24 left as NC per DG

PCH output, for decoupling only

NC-ed per DG

1.44 A Max, 474mA IdleVCCACLK pin left as NC per DG

PCH output, for decoupling only

55mA Max, 5mA Idle

10 mA Max, 1mA Idle

VCCAPLLDMI2 pin left as NC per DG

QP8D-MM915462

OMIT_TABLE

BGAPCH-PPT-MB-SFF-ES1PCH-PPT-MB-SFF-ES1

OMIT_TABLE

QP8D-MM915462BGA

X5R-CERM

10%0.1UF16V

0201

PLACE_NEAR=U1800.N16:2.54mm

0201

0.1UF10%16VX5R-CERM


PLACE_NEAR=U1800.U17:2.54mm16V

0.1UF10%

X5R-CERM0201

0201

1UF20%6.3VX5R



0.1UF10%16V

X5R-CERM0201

PCH POWERSYNC_MASTER=J13_MLB SYNC_DATE=09/22/2011


=PP5V_S0_PCH_V5REF

PPVOUT_S0_PCH_DCPSST

VOLTAGE=3.3VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.2 mm




PP1V05_S0_PCH_VCCCLKDMI_F

=PPVRTC_G3_PCH

TP_PPVOUT_PCH_DCPSUSBYP


MIN_NECK_WIDTH=0.2 mmVOLTAGE=3.3V

PPVOUT_G3_PCH_DCPRTCMIN_LINE_WIDTH=0.2 mm

PP1V05_S0_PCH_VCCADPLLB_F

PP1V05_S0_PCH_VCCADPLLA_F


=PP5V_SUS_PCH_V5REFSUS





TP_1V05_S0_PCH_VCCAPLLEXP






PP3V3_S0_PCH_VCCA_DAC_F



PP3V3_S0_PCH_VCC3_3_CLK_F


U1800

AB19

AC19

AF6

BK28

R40

T39

U37

V37

V39

U51

AU21

AU19

AP13

AP15

AF33

AG33

AP19

AB21

AB23

AG25

AG27

AJ21

AJ23

AJ25

AJ27

AJ29

AJ31

AK29

AK31

AC21

AK33

AM33

AM35

AC23

AE21

AE23

AF21

AF23

AG21

AG23

AJ13

AJ15

AK15

AL13

AM23

AU15

AW16

AP27

AR15

AR23

AR25

AR27

AR29

AT13

AU23

AU25

AU27

AU29

AU35

AW34

AM21

Y19

AF37

AG37

AG39

AJ37

V50

AC33

AE33

U1800

R15

U15

U17

AR33

AU31

AU33

V13

R10

N36

M37

AM17

AC51

BF40

BD40

AM2

AW31

AB27

AB29

U19

U21

V19

V21

V23

V25

Y21

Y23

Y25

Y27

AB31

Y29

Y31

AC27

AC29

AC31

AE27

AE29

AE31

R19

AP39

AC37

AE37

AE39

R12

AA13

AB15

AC13

N18

R23

R25

U23

U25

AC15

AF15

AG13

AG15

AJ17

AK21

U27

U29

N16

AC35

AM27

N27

R27

R29

R33

R35

U33

U35

V31

AC39

AE19

AF17

AW18

AW21

C22321

2

C22331

2

C2222 1

2

C2231 1

2

C2210 1

2

051-9276

2.7.0

22 OF 109

20 OF 72

7 22

22

7 20

7 20 22

7 22

22

7 16 17

7 22

22

22

7 16 22

22

7 22

7 22

7 22 25

7 20 22

7 22

7 20

7 19 22

7 20

7 22

22

7 22

7 22

22

7 22

(9 OF 10)

VSSVSS

(10 OF 10)

VSSVSS

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6 3



BGAPCH-PPT-MB-SFF-ES1

QP8D-MM915462

OMIT_TABLE

BGAQP8D-MM915462

OMIT_TABLE

PCH-PPT-MB-SFF-ES1

PCH GROUNDSSYNC_DATE=08/12/2011SYNC_MASTER=J13_MLB

U1800AA7

AA9

AB25

AP25

AP29

AP31

AP33

AP35

AP37

AP41

AP43

AP45

AP48

AB33

AP50

AR6

AR8

AR17

AR19

AR21

AR31

AR35

AR37

AT7

AB35

AT9

AT11

AT39

AT41

AT43

AT45

AU17

AU37

AV2

AV4

AB37

AV48

AV50

AW7

AW9

AW11

AW13

AW23

AW25

AW27

AW29

AB48

AW36

AW39

AW41

AW43

AW45

AY10

B6

B10

B14

B18

AB50

B22

B26

B30

B34

B38

B42

B46

BA7

BA9

BA11

AC7

BA13

BA16

BA18

BA21

BA23

BA25

BA27

BA29

BA31

BA34

AC9

BA36

BA39

BA41

BA43

BA45

BB2

BB4

BB48

BB50

BC11

AC11

BC13

BC16

BC18

BC21

AC17

AA11

AC25

AC41

AC43

AC45

AE7

AE9

AE11

AE13

AE15

AE17

AA39

AE25

AE35

AE41

AE43

AE45

AF2

AF4

AF8

AF19

AF25

AA41

AF27

AF29

AF31

AF35

AF48

AF50

AG7

AG9

AG11

AG17

AA43

AG19

AG29

AG31

AG35

AG41

AG43

AG45

AH2

AJ7

AJ9

AA45

AJ11

AJ19

AJ33

AJ35

AJ39

AJ41

AJ43

AJ45

AK2

AK4

AB2

AK17

AK19

AK23

AK25

AK27

AK35

AK37

AK48

AK50

AL7

AB4

AL9

AL11

AL39

AL41

AL43

AL45

AM15

AM19

AM25

AM29

AB17

AM31

AM37

AP2

AP4

AP7

AP9

AP11

AP17

AP21

AP23

U1800BC23

BC25

BC27

BC29

BC31

BC34

BC36

BC39

BC41

BC43

BC45

BD15

BD24

BE7

BE9

BE11

BE13

BE16

BE18

BE21

BE23

BE25

BE27

BE29

BE31

BE34

BE36

BE39

BE41

BE43

BE45

BF2

BF4

BF15

BF24

BF48

BF50

BH6

BH10

BH14

BH18

BH22

BH26

BH28

BH30

BH32

BH34

BH38

BH42

BH44

BH46

BH48

BK10

BK14

BK18

BK22

BK26

BK30

BK32

BK34

BK38

BK42

BK46

D6

D10

D14

D18

D22

D26

D30

D34

D38

D42

D46

F2

F4

F48

F50

G7

G9

G11

G13

G16

G18

G21

G23

G25

G27

G29

G31

G34

G36

G39

G41

G43

J7

J9

J11

J13

J16

J18

J21

J23

J25

J27

J29

J31

J34

J36

J39

J41

J45

K2

K4

K48

K50

L7

L9

L11

L13

L16

L18

L21

L23

L25

L27

L29

L31

L34

L36

L39

L41

L43

L45

N7

N9

N11

N13

N21

N23

N25

N29

N31

N34

N39

N41

N43

N45

P2

P4

P48

P50

R17

R21

R31

R37

T7

T9

T11

T13

T41

T43

T45

U31

U49

V2

V4

V7

V9

V11

V15

V17

V27

V29

V33

V35

V41

V43

V45

V48

Y15

Y17

Y33

Y35

Y37

051-9276

2.7.0

23 OF 109

21 OF 72

NC

NC

NC

NC

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NEED PWR CONSTRAINT

(PCH Reference for 5V Tolerance on USB)

(PCH DPLLB PWR)

PCH VCCADPLLB Filter

PCH VCCADPLLA Filter

(PCH DPLLA PWR)

69 mA

(PCH 1.05V CORE PWR)

PCH VCCCORE BYPASS

PCH VCCSUS3_3 BYPASS

(PCH HD Audio 3.3V/1.5V PWR)

PCH VCCSUSHDA BYPASS

PCH VCCIO BYPASS

1 mA

1 mA S0-S5

PCH V5REF Filter & Follower

<1 MA

NEED PWR CONSTRAINT

PCH V5REF_SUS Filter & Follower

(PCH SUSPEND USB 3.3V PWR)

(PCH USB 1.05V PWR)

(PCH Reference for 5V Tolerance on PCI)

68 mAMF-LF

0

402

5%1/16W

402

1/16WMF-LF

0

5%

22UF


20%

0603X5R-CERM1

6.3V


22UF20%

6.3VX5R-CERM1

0603


1UF

X5R0201

20%6.3V


X5R

20%6.3V

1UF

0201


1UF

X5R

20%6.3V

0201

PLACE_NEAR=U1800.AU27:2.54mm

10UF

0402-2

20%6.3V

CERM-X5R


6.3V20%

0201X5R

1UF

PLACE_NEAR=U1800.AR29:2.54mm

6.3V

1UF20%

0201X5R

6.3V


X5R0201

1UF20%

1UF

X5R

PLACE_NEAR=U1800.AR25:2.54mm

0201

20%6.3V


0402-2CERM-X5R

6.3V20%

10UF


1UF

X5R0201

20%6.3V


1UF

X5R0201

20%6.3V


0201

1UF

X5R

20%6.3V

X5R-CERM0201

PLACE_NEAR=U1800.AJ13:2.54mm0.1UF16V10%

16V10%

0201X5R-CERM

0.1UFPLACE_NEAR=U1800.V31:2.54mm

0.1UF

PLACE_NEAR=U1800.AM17:2.54mm

10%

0201

16VX5R-CERM


16V10%

0201X5R-CERM

0.1UF

X5R-CERMPLACE_NEAR=U1800.AM17:2.54mm

10%16V

0201

0.1UF20%

6.3VX5R402

4.7UF


10%

0201

16V


0.1UF

X5R-CERM

X5R0201

6.3V

1UF20%

PLACE_NEAR=U1800.Y19:2.54mm

0201

16VX5R-CERM

10%0.1UF


0201X5R

20%6.3V


1UF


1UF

X5R0201

20%6.3V

PLACE_NEAR=U1800.AG13:2.54mm

6.3V20%

0201X5R

1UF

6.3V20%

0201X5R

1UF

PLACE_NEAR=U1800.AC35:2.54mm


6.3V20%

0201X5R

1UF

PLACE_NEAR=U1800.AC37:2.54mm 6.3V

0201X5R

1UF20%

6.3V

1UF20%

0201X5R


PLACE_NEAR=U1800.AJ17:2.54mm 6.3V20%

0201X5R

1UF

CERM-X5RPLACE_NEAR=U1800.AP39:2.54mm

0402-2

10UF6.3V20%

10UH-0.12A-0.36OHM

0603

10%

X5R-CERM16V

0201

0.01UF

PLACE_NEAR=U1800.U51:2.54mmPLACE_NEAR=U1800.U51:2.54mm

0.1UF

X5R-CERM

10%16V

02010402-2

10UF20%

6.3VCERM-X5R


201

0

MF1/20W5%

SOT-363BAT54DW-X-G

100

MF

5%1/20W

201


X5R

1UF

402

10V10%

SOT-363BAT54DW-X-G

201

1/20W5%

MF

10

CERM10V20%

0.1UFPLACE_NEAR=U1800.M37:2.54mm

402

PLACE_NEAR=U1800.AF6:2.54mm 0201

10%

X5R-CERM

0.1UF16V

0201PLACE_NEAR=U1800.R40:2.54mm

X5R-CERM16V

0.1UF10%

0.1UF

X5R-CERM

PLACE_NEAR=U1800.BK28:2.54mm

16V

0201

10%

0.1UF

X5R-CERM0201

10%16V

PLACE_NEAR=U1800.T39:2.54mm

X5R6.3V

1UF20%

0201

PLACE_NEAR=U1800.BF40:2.54MM

X5R-CERM

0.1UF10%

0201

16V

PLACE_NEAR=U1800.BF40:2.54MM

6.3V PLACE_NEAR=U1800.BD40:2.54MM

0201X5R

20%1UF

PLACE_NEAR=U1800.BD40:2.54MM

0.1UF

0201

16V10%

X5R-CERM

PLACE_NEAR=U1800.AB19:2.54mm 0201X5R-CERM

0.1UF10%16V

6.3V20%

0201X5R

1UF

PLACE_NEAR=U1800.AW16:2.54mm

PLACE_NEAR=U1800.V37:2.54mm

X5R

10%

402

1UF10V

6.3V20%

CERM-X5R

10UF

0402-1

PLACE_NEAR=U1800.V37:2.54mm

10UH-0.12A-0.36OHM

0603

1

5%

MF-LF402

1/16W

201

0

MF1/20W5%

PCH DECOUPLING


MIN_LINE_WIDTH=0.5MMMIN_NECK_WIDTH=0.25MMVOLTAGE=1.05V

PP1V05_S0_PCH_VCCCLKDMI_RMIN_LINE_WIDTH=0.5MMMIN_NECK_WIDTH=0.25MMVOLTAGE=1.05VMAKE_BASE=TRUE

PP1V05_S0_PCH_VCCCLKDMI_F

PP3V3_S0_PCH_VCCA_DAC_FMAKE_BASE=TRUEMIN_LINE_WIDTH=0.4 MMMIN_NECK_WIDTH=0.2 MMVOLTAGE=3.3V

PP1V05_S0_PCH_VCCADPLLB_FMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.4 MM

VOLTAGE=1.05V

=PP3V3_S0_PCH


PP3V3_S0_PCH_VCC3_3_CLK_FMIN_LINE_WIDTH=0.4 MM

VOLTAGE=3.3V


MIN_LINE_WIDTH=0.4 MMMIN_NECK_WIDTH=0.2 MMVOLTAGE=3.3V

PP3V3_S0_PCH_VCC3_3_CLK_R=PP3V3_S0_PCH_VCC3_3_CLK









=PP1V05_S0_PCH_VCC_DMI=PP5V_S0_PCH

=PP3V3_S0_PCH_VCCADAC


=PP5V_SUS_PCH=PP3V3_SUS_PCH





=PP5V_SUS_PCH_V5REFSUS MIN_LINE_WIDTH=0.4 MM


PP1V05_S0_PCH_VCCADPLLA_F




PP5V_SUS_PCH_V5REFSUSMIN_NECK_WIDTH=0.25MM

MAKE_BASE=TRUEVOLTAGE=5V

MIN_LINE_WIDTH=0.3MM

=PP1V8_S0_PCH_VCC_DFTERM=PP1V05_S0_PCH


=PP5V_S0_PCH_V5REFMAKE_BASE=TRUE

PP5V_S0_PCH_V5REFMIN_LINE_WIDTH=0.3MM

VOLTAGE=5VMIN_NECK_WIDTH=0.25MM


=PP1V05_S0_PCH_VCCADPLL


R24601 2

R24651 2

C2420 1

2

C2428 1

2

C24961

2

C24561

2

C24261

2

C2401 1

2

C24631

2

C24071

2

C24141

2

C24291

2

C2460 1

2

C24831

2

C24821

2

C24811

2

C24401

2

C24411

2

C24301

2

C24131

2

C24171

2

C2416 1

2

C24841

2

C24421

2

C2499 1

2

C24191

2

C24761

2

C24521

2

C24751

2

C24441

2

C24341

2

C24461

2

C24691

2

C24111

2

L2406

1 2

C2455 1

2

C2451 1

2

C2450 1

2

R24501 2

D24001

6

R2405

12

C2439 1

2

D24004

3

R2404

12

C2438 1

2

C24231

2

C24851

2

C24211

2

C24241

2

C24611

2

C24021

2

C24661

2

C24651

2

C24221

2

C24181

2

C24861

2

C2453 1

2

L2451

1 2

R24511 2

R24151 2

051-9276

2.7.0

24 OF 109

22 OF 72

5

2

20

20

20

7 16

20

7 20

7

7 20

7 20 25

7 20

7 20 22

7 20 22

7 20

7 20 22

7 20 22

7 20 22 7 25

7

7 20 22

7

7

7 20 22

7 16

7 16 20

7 20

20

20

7 20 22

7 20

7 20

7 19 20

7 16

7 20 22

20

7 20 22

7

7 20 22

IN

IN

IN

IN

IN

IN

IN

OUT

IN

IN

IN

IN

OUT

OUT

NC

IN

OUT

IN

BI

IN

OUT

OUT

OUT

IN

OUT

IN

OUT

IN

IN

OUT

OUT

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

IN

IN

IN

IN

IN

IN

OUT

NC

IN

OUT

OUTOUT

OUT IN

OUTOUT

BI

IN

IN

IN

IN

IN

BI

IN

OUT

IN

IN

IN

IN

IN

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



PCH SIGNALS

OBSFN_D0

518S0847

RESET#/HOOK6VCC_OBS_CDITPCLK#/HOOK5ITPCLK/HOOK4

TDO

XDP_PRESENT#

TRSTn

(R2560-R2563)

OBSFN_C0OBSFN_A0

OBSDATA_C3OBSDATA_A3

(R2520-R2537)

VCC_OBS_AB

XDP SIGNALS

OBSDATA_A2

TMSTDI

Initially, stuffing both 33 and 0 ohms and validate whether

- Following Intel’s Debug Prot Design Guid for HR and CR v1.3

needs to split between route from PCH to J2550and path to non-XDP signal destination.

PCH/XDP Signal Isolation Notes:

- ’Output’ PCH/XDP signals require pulls. - ’Output’ non-XDP signals require pulls.

OBSDATA_D1

OBSDATA_D2OBSDATA_D3

DBR#/HOOK7

OBSDATA_D0

RESET#/HOOK6

OBSFN_B0

OBSDATA_A2

VCC_OBS_ABHOOK2

PWRGD/HOOK0

OBSDATA_B2

OBSFN_B1

VCC_OBS_CD

OBSDATA_B3

OBSDATA_B1OBSDATA_B0

it is functional in that state, else add BOM options.

doc id 404081.

- For isolated GPIOs:

HOOK2

SDASCL

OBSDATA_C0

OBSFN_B1OBSFN_B0

OBSDATA_A1

OBSFN_A1

OBSFN_D1

OBSDATA_C2

OBSDATA_C2

OBSFN_D0

ITPCLK/HOOK4

HOOK3

TCK0

SDA

HOOK1

TDITMS

TDOTRSTn

DBR#/HOOK7

ITPCLK#/HOOK5

OBSFN_D1

OBSDATA_C3

OBSDATA_C0

OBSDATA_D2

OBSDATA_D0OBSDATA_D1

XDP_PRESENT#

TCK0

OBSDATA_A0

OBSDATA_D3

HOOK1

TCK1SCL

Non-XDP Signals

PWRGD/HOOK0

OBSDATA_B3

Use with 921-0133 Adapter Flex toNOTE: This is not the standard XDP pinout.

CPU Micro2-XDP

OBSDATA_C1

OBSFN_C0OBSFN_A0

OBSDATA_A3

NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page

1K series R on PCH Support Page

OBSDATA_B1OBSDATA_B0

TCK1

OBSDATA_A1OBSDATA_A0

OBSFN_A1

support chipset debug.

OBSFN_C1

OBSDATA_C1

OBSFN_C1

OBSDATA_B2

518S0847

Use with 921-0133 Adapter Flex to

NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page

support chipset debug.

PCH SIGNALS

NOTE: This is not the standard XDP pinout.

R252x, R253x, R257x and R259x should be placed where signal path

HOOK3

(R2564-R2567)

PCH Micro2-XDP

9

10 25

10 65

10 65

10 65

10 65

10 65

9 23 65

9 65

9 65

25

16 23 68

16 23 68

16 23 68

9 65

16 23 68

9 65

23 43

23 43

10 23 25 65

XDP

0.1uF

X5R402

10%16V

XDP

0.1uF

X5R402

10%16V

17 23 40

17 25 40

10 23 65

10 23 25 65

9

10 23 65

16 65

16 65

10 23 65

10 23 65

1/16W

NO STUFF

1K

MF-LF402

5%

PLACE_NEAR=R1841.1:2.54mmXDP0

MF 2015% 1/20W

PLACE_NEAR=R1840.1:2.54mmXDP0

MF 2015% 1/20W

1/20W

XDP1K

MF 2015%

PLACE_NEAR=U1000.D44:2.54mm

XDP

MF 2015% 1/20W51

PLACE_NEAR=J2550.51:2.54mm

XDP51

MF 2015% 1/20W


XDP51

MF 2015% 1/20W

PLACE_NEAR=U1800.M15:2.54mm

XDP51

MF 2015% 1/20W


514021/16W MF-LF5%

XDP PLACE_NEAR=J2500.52:2.54mm

XDP PLACE_NEAR=U1000.K61:2.54mm51

MF 2015% 1/20W

PLACE_NEAR=U1000.H59:2.54mmXDP51

MF 2015% 1/20W

1/20W

PLACE_NEAR=U1000.J58:2.54mmXDP51

MF 2015%

XDP51

MF 2015%

PLACE_NEAR=U1000.H63:2.54mm

1/20W

3304025%

XDP

1/16W MF-LF

1KXDP

2011/20W MF5%PLACE_NEAR=U1000.B50:2.54mm

0MF 2015%

XDP

1/20WPLACE_NEAR=U4900.J3:2.54mm

XDP

1/20W MF 2015%1K

PLACE_NEAR=U1000.B46:2.54mm

XDP_CPU:BPM0

1/16W 4025% MF-LF10 65

04021/16W MF-LF5%

XDP_CPU:BPM

PLACE_SIDE=BOTTOM

4021/16W MF-LF5%0

XDP_CPU:BPM

PLACE_SIDE=BOTTOM

MF-LF

XDP_CPU:BPM

4021/16W5%0

XDP_CPU:CFG

4021/16W MF-LF5%0 5% 1/16W MF-LF

XDP_CPU:CFG

4020 1/16W5% 402MF-LF

XDP_CPU:CFG0

1/16W0

5%

XDP_CPU:CFG

402MF-LF

9 65

9 65

9 65

9 65

331/20W

XDP

MF 2015%

5%

XDP

33MF 2011/20W

5% 1/20W

XDP

33MF 201

XDP

33MF 2015% 1/20W

XDP

33MF 2015% 1/20W

XDP

33MF 2015% 1/20W

XDP

33MF 2015% 1/20W

XDP

33MF 2015% 1/20W

5% 1/20W

XDP

33MF 201

5%

XDP

33MF 2011/20W

1/20W

XDP

33MF 2015%

19 23

8 19

19 23

19

9 23 65

8 16

16 23

19

19 23

18 23

18 23

18 23

18

18

18

XDP1K

MF 2015% 1/20WPLACE_NEAR=J2550.40:2.54mm

0MF 2015% 1/20W

XDP

PLACE_NEAR=U4900.J3:2.54mm

25 40 51 61

17 23 40

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

XDP_CONNCRITICAL

DF40RC-60DP-0.4VM-ST-SM1

XDP_CONNCRITICAL

DF40RC-60DP-0.4VM-ST-SM1

1/20W 201

XDP

33MF5%

26

16 25

19 25

1/20W5% 201MF0

2015% MF0

1/20W

MF5% 2011/20W0

1/20W5% 201MF0

18 23

19 23

XDP

0.1uF

X5R402

10%16V

19 23

XDP

33MF 2015% 1/20W

XDP

33MF 2015% 1/20W

XDP

33MF 2015% 1/20W

XDP

33MF 2015% 1/20W

XDP

33MF 2015% 1/20W

XDP

33MF 2015% 1/20W

19

19 23

18

18

0MF 2015% 1/20W

9 65

16 23

2011/20W5% MF018 23 38

18 36 61

19 19 23

MF5%1/20W

201 1K1K2011/20W

MF5%

MF5% 2011/20W018 23

XDP

0.1uF

X5R402

10%16V

6 39

1/20W5% MF1K

20119 19 23

10 65

10 65

9 65

9 65

9 65

9 65

23 43

23 43

10 23 65

9 65

10 19 65

9 65

10 65

10 65


CPU & PCH XDP


XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL

XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK



XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L


TBT_CIO_PLUG_EVENT_ISOL



XDP_VR_READY

CPU_CFG<11>

XDP_BPM_L<2>

XDP_BPM_L<7>

XDP_OBSDATA_B<2>

XDP_OBSDATA_B<0>

XDP_OBSDATA_B<3>

CPU_CFG<12>CPU_CFG<13>CPU_CFG<14>CPU_CFG<15>

CPU_PWRGD

PM_PWRBTN_L

XDP_CPU_PWRBTN_L

XDP_CPU_CFG<0>XDP_DBRESET_LXDP_CPURST_L

XDP_CPU_CLK100M_P

CPU_CFG<6>

XDP_DC3_SATARDRVR_EN

=PP3V3_S5_XDP


XDP_DB1_PCH_GPIO9_USB_EXTD_OC_EHCI_L

XDP_PCH_TDO

XDP_CPU_TDOXDP_CPU_TRST_L

XDP_OBSDATA_B<1>

CPU_CFG<10>

XDP_DC1_MXM_GOODXDP_DC0_ISOLATE_CPU_MEM_L

XDP_DA1_USB_EXTB_OC_LXDP_DA0_USB_EXTA_OC_L


JTAG_ISP_TCK

DP_AUXCH_ISOL

CPU_CFG<7>

=PP1V05_SUS_PCH_JTAG

XDP_PCH_TCK

XDP_PCH_TDI

TP_XDP_PCH_HOOK5

XDP_DBRESET_L

TP_XDP_PCH_OBSFN_B<1>

PM_PWRBTN_L

XDP_PCH_S5_PWRGD

TP_XDP_PCH_OBSFN_A<0>

XDP_DD1_JTAG_ISP_TCK

XDPPCH_PLTRST_L

XDP_PCH_TDOTP_XDP_PCH_TRST_L

XDP_PCH_TMS

=PP3V3_S0_XDP

XDP_FC0

XDP_DC2_DP_AUXCH_ISOL

XDP_PCH_TMS

XDP_CPU_TCK

XDP_CPU_TRST_L

XDP_CPU_TMS

XDP_CPU_TDI

XDP_DB2_AP_PWR_EN

XDP_PCH_TCK

=SMBUS_XDP_SCL

TP_XDPPCH_HOOK2TP_XDPPCH_HOOK3

XDP_DB1_USB_EXTD_OC_EHCI_L

XDP_PCH_TDI

TP_XDP_PCH_HOOK4

TP_XDP_PCH_OBSFN_D<0>


ITPXDP_CLK100M_P

ITPXDP_CLK100M_N

CPU_RESET_L

XDP_CPU_PREQ_L

XDP_BPM_L<0>

XDP_BPM_L<3>CPU_CFG<2>

CPU_CFG<8>

CPU_CFG<3>

CPU_CFG<1>XDP_BPM_L<4>

XDP_DD3_ENET_LOW_PWR

XDP_DD0_DP_GPU_TBT_SEL

TP_XDP_PCH_OBSFN_D<1>

=SMBUS_XDP_SDA

XDP_DD1_JTAG_ISP_TCK

XDP_DD2_AUD_IPHS_SWITCH_ENXDP_DD3_ENET_LOW_PWR

XDP_CPU_TCK

XDP_DC0_ISOLATE_CPU_MEM_L

TP_XDP_PCH_OBSFN_B<0>

XDP_PCH_PWRBTN_L

XDP_DB0_USB_EXTB_OC_EHCI_L

XDP_DB3_SDCONN_STATE_CHANGE

CPU_CFG<5>

CPU_CFG<9>

USB_EXTA_OC_L

CPU_CFG<4>

XDP_DC2_DP_AUXCH_ISOLXDP_DC3_PCH_GPIO19_SATARDRVR_ENXDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL

XDP_DB3_SDCONN_STATE_CHANGEXDP_FC0

XDP_DA3_USB_EXTD_OC_L

XDP_DA0_USB_EXTA_OC_L

XDP_DB0_USB_EXTB_OC_EHCI_LXDP_DB1_USB_EXTD_OC_EHCI_L

XDP_DC1_MXM_GOOD

XDP_DC3_SATARDRVR_ENXDP_DD0_DP_GPU_TBT_SEL

XDP_DB2_AP_PWR_EN

XDP_DA2_USB_EXTC_OC_L

ALL_SYS_PWRGD

XDP_DD2_AUD_IPHS_SWITCH_EN

XDP_FC1

CPU_CFG<0>

TP_XDP_PCH_OBSFN_A<1>

XDP_DA3_USB_EXTD_OC_LXDP_DA2_USB_EXTC_OC_L

XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SELXDP_DD1_PCH_GPIO37_JTAG_ISP_TCK

XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH

XDP_DB0_PCH_GPIO43_USB_EXTB_OC_EHCI_L


XDP_DC1_PCH_GPIO35_MXM_GOODXDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L

XDP_FC1_PCH_GPIO0

XDP_FC0_PCH_GPIO15XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE

PM_PCH_SYS_PWROK

CPU_CFG<0>

XDP_BPM_L<1>


XDP_FC1

=PPVCCIO_S0_XDP

XDP_CPU_TDO

XDP_BPM_L<6>XDP_BPM_L<5>

=PPVCCIO_S0_XDP

ISOLATE_CPU_MEM_L

XDP_CPU_CLK100M_N

XDP_CPU_TDIXDP_CPU_TMS

AP_PWR_EN

USB_EXTB_OC_L

=SMBUS_XDP_SDA=SMBUS_XDP_SCL

XDP_DA2_PCH_GPIO41_USB_EXTC_OC_LXDP_DA1_USB_EXTB_OC_L

XDP_CPU_PRDY_L

XDP_FC1_PCH_GPIO0

XDP_CPU_PWRGD

C25011

2

C2500 1

2

C2580 1

2

C25811

2

R25401

2

R2515 1 2

R2516 1 2

R2505 1 2

R2550 2 1

R2551 2 1

R2552 2 1

R2556 2 1

R2510 2 1

R2511 2 1

R2512 2 1

R2513 2 1

R2514 2 1

R2504 1 2

R2501 1 2

R2502 1 2

R2500 1 2

R2560 1 2

R2561 1 2

R2562 1 2

R2563 1 2

R2566 1 2

R2565 1 2

R2564 1 2

R2567 1 2

R2524 1 2

R2525 1 2

R2526 1 2

R2527 1 2

R2530 1 2

R2532 1 2

R2533 1 2

R2534 1 2

R2535 1 2

R2536 1 2

R2537 1 2

R2584 1 2

R2585 1 2

J2500

1

10

1112

1314

1516

1718

19

2

20

2122

2324

2526

2728

29

3

30

3132

3334

3536

3738

39

4

40

4142

4344

4546

4748

49

5

50

5152

5354

5556

5758

59

6

60

6162

6364

78

9

J2550

1

10

1112

1314

1516

1718

19

2

20

2122

2324

2526

2728

29

3

30

3132

3334

3536

3738

39

4

40

4142

4344

4546

4748

49

5

50

5152

5354

5556

5758

59

6

60

6162

6364

78

9

R2521 1 2

R2596 1 2

R2572 1 2

R2570 1 2

R2576 1 2

R2528 1 2

R2529 1 2

R2520 1 2

R2522 1 2

R2523 1 2

R2531 1 2

R2575 1 2

R2590 1 2

R25801 2

R25811 2

R2592 1 2

R2574 1 2

051-9276

2.7.0

25 OF 109

23 OF 72

65

65

65

65

65

23

7

16 23 68

65

23

23

23

23

7

16 23 68

16 23 68

6

6

6

23

7

23

23

16 23 68

10 23 65

10 23 65

10 23 65

10 23 65

23

6

6

23

6

6

23

23

6

6

23

23

23

23 6

23

23

7 23

10 23 65

7 23

65

BI

BI

IN

VCC

GND

SELOE*

D+

D-

Y+

Y-

M+

M-

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

NC

NC

BI

BI

BI

BI

VDD33

PLLFILT

CRFILT

SUSP_IND/LOCAL_PWR/NON_REM0

SDA/SMBDATA/NON_REM1

SCL/SMBCLK/CFG_SEL0

HS_IND/CFG_SEL1

XTALIN/CLKIN

XTALOUT

TEST

RESET*

THRM_PAD

USBDP_UP

NC

OSC3*

OCS1*

OCS2*

USBDM_UP

RBIAS

VBUS_DET

NC

NC

NC

USBDP_DN3/PRT_DIS_P3

USBDM_DN3/PRT_DIS_M3





PRTPWR3/BC_EN3*

PRTPWR1/BC_EN1*

PRTPWR2/BC_EN2*

SYM VER 1

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_BOMGROUP_ITEM


TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

CRITICAL BOM OPTIONTABLE_5_HEAD

PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)

Apple Inc.


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R

DSIZEDRAWING NUMBER

REVISION

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6 3



TO CONNECT TP/KB TO PCH XHCI

Trackpad/Keyboard

SMC Port

TO USB HUBTO TP/KB

IPU

IPU

SEL=1 CHOOSE USB XHCI PORT

SEL=0 CHOOSE USB EHCI2 PORT

IPU

PCH GPIO60

IPU

PCH PORT 1 (XHCI)

PCH PORT 9 (EHCI2)

TO LIO CONNECTOR

LIO External D

BOM TABLE

BlueTooth

PULL-UP TO 3.3V SUS ON PCH PAGE, SEL PIN IS LEAKAGE-SAFE

NOSTUFF R2611 & R2615, STUFF R2621,R2622,R2616 & R2617

TO PCH XHCI

SDCARD(NA to J11)

NON_REM1 NON_REM0 DESCRIPTION

USB XHCI/EHCI2 PORT MUX FOR EXT B

1 1 Port 1, 2, and 3 are non removable

1 0 Port 1 and 2 are non removable

0 1 Port 1 is non removable

0 0 All ports are removable

0201

20%6.3VX5R

1UF

6 39 67

6 39 67

16

CRITICALTQFN

PI3USB102ZLE

24 67

18 67

18 67

18 67

18 67

201

5%1/20WMF

10K

16V10%

0201X5R-CERM

0.1UF

PLACE_NEAR=U2600.26:2.5MM

8 67

8 67

24 67

0.1UF

X5R-CERM

10%16V

0201

18 67

18 67

TPAD_PCH:YES

0

201

1/20WMF

5%TPAD_PCH:YES

0

5%1/20WMF201

48 67

24 40 67

48 67

TPAD_PCH:NO

201

1/20W

0

MF

5%TPAD_PCH:NO

MF1/20W5%

0

201

24 67

24 67

TPAD_PCH:YES

201

5%10K

MF1/20W

10K

TPAD_PCH:YES

201

1/20WMF

5%

1/20WMF

10K5%

201

NOSTUFF

10K

1/20W

NOSTUFF

201MF

5%

2.50X2.00MM-SM

CRITICAL

24.000MHZ-50PPM-6PF

24 40 67

18 67

1/20WMF201

1%12K

CRITICAL

18 67

0.1UF

X5R-CERM

10%16V

02011UF

0201

20%6.3VX5R

36 67

0.1UF

16V

0201

10%

X5R-CERM

BYPASS=U2600.15::2mm

0201


10%

X5R-CERM16V

0.1UF0.1UF

16V10%

0201X5R-CERM



0.1UF

X5R-CERM0201

10%16V

0.1UF

0201X5R-CERM

16V

BYPASS=U2600.5::2mm

10%0.1UF

X5R-CERM

10%16V

0201


402

20%6.3V

X5R-CERM1

4.7UF

BYPASS=U2600.5::5mm

6.3V

402


20%4.7UF

X5R-CERM1

36 67 5%

100

1/20WMF201

NP0-C0G-CERM

25V

6.0PF+/-0.1PF

201

CRITICAL

1/20W

1M

5%

MF201CRITICAL

201

25V

NP0-C0G-CERM

6.0PF+/-0.1PF

CRITICAL

QFN

OMIT_TABLE

USB2513B

CRITICAL

0201

0.1UF

16VX5R-CERM

10%

10K

1/20W5%

201MF

5%1/20WMF

10K

201

5%10K

MF1/20W

201

5%10K

1/20WMF201

HUB_NONREM0_1

10K

HUB_NONREM1_1

MF

5%1/20W

201

HUB_NONREM0_0

5%1/20WMF201

10K

HUB_NONREM1_0

5%10K

1/20WMF

201

USB HUB & MUXSYNC_DATE=08/12/2011SYNC_MASTER=J13_MLB

HUB_NONREM1_0,HUB_NONREM0_1HUB_1NONREM

HUB_NONREM1_1,HUB_NONREM0_0HUB_2NONREM

HUB_3NONREM HUB_NONREM1_1,HUB_NONREM0_1

HUB_NONREM1_0,HUB_NONREM0_0HUB_ALLREM

USBHUB2512B1338S0983 CRITICALU2600IC,USB2512B,USB 2.0 HUB CNTRL,36-QFN

IC,USB2513B,USB 2.0,HUB CNTRL,3PRT,36QFN USBHUB2513BU26001 CRITICAL338S0923

USB_HUB1_NONREM1

USB_HUB1_CFG_SEL1

USB_HUB1_NONREM0

USB_HUB1_XTAL2

USB_HUB1_CFG_SEL0

USB_HUB1_TEST

=PP3V3_S3_USBMUX

USB_TPAD_HUB_P

USB_BT_P

USB_TPAD_HUB_N

=PP3V3_S3_USB_HUB

USB_TPAD_HUB_P

USB_TPAD_HUB_N USB_TPAD_R_N

USB_TPAD_R_P

USB_EXTD_XHCI_P

USB_EXTD_XHCI_N

=PP3V3_S3_USB_HUB

USB_SMC_P

USB_HUB_RESET_L

USB_HUB1_XTAL1

USB_SDCARD_P

NC_USB_HUB1_OCS3

NC_USB_HUB1_OCS4

USB_HUB1_RBIAS

USB_HUB1_VBUS_DET

USB_HUB_UP_N

USB_HUB_UP_P

=PP3V3_S3_USB_HUB

=PP3V3_S3_USB_RESET

USB_HUB_RESET_L

USB_EXTB_XHCI_P

USB_EXTB_EHCI_P

USB_EXTB_XHCI_N

USB_EXTB_EHCI_N

USB_EXTB_SEL_XHCI

USB_SDCARD_N

TP_USB_HUB1_PRTPWR1

NC_USB_HUB1_OCS2

TP_USB_HUB1_OCS1

NC_USB_HUB1_PRTPWR4

NC_USB_HUB1_PRTPWR3

NC_USB_HUB1_PRTPWR2

VOLTAGE=1.8VMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.4MMPPUSB_HUB1_CRFILT

USB_EXTB_P

=PP3V3_S3_USB_HUB

USB_SMC_N

USB_BT_N

PPUSB_HUB1_PLLFILT

VOLTAGE=1.8VMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.4MM

USB_SMC_P

USB_EXTB_N

USB_SMC_N

C26181

2

C26171

2C26161

2

C26151

2

R26201

2

R26001

2

C2612 1

2

C2611 1

2

C2603 1

2

C2610 1

2

C2609 1

2

C2608 1

2

C2602 1

2

C2607 1

2

R26051 2

C26201

2R26301 2

C2619 1

2

U2600

14

25

8

9

20

21

13

17

19

34

12

16

18

35

26

24

22

28

11

37

1

3

6

30

2

4

7

31

27

5 10

15

23

29

36

33

32

R26071

2

R26061

2

R26031

2

R26011

2

R26041

2

R26021

2

U2660

6

7

3

4

5

8 10

9

2

1

R26121

2

C2604 1

2

C2663 1

2

R2622

1 2

R2621

1 2

R2611

1 2

R2615

1 2

R26161

2

R26171

2

R26181

2

R26191

2

Y2600

2 4

1 3

051-9276

2.7.0

26 OF 109

24 OF 72

7

7 8 24

7 8 24

24 40 67

24

7 8 24

7

24

7 8 24

24 40 67

OUT

OUT

OUT

PAD

+3.42V

VDD_25M

+V3.3A

VDDIO_25M_C

VDDIO_25M_B

VDDIO_25M_A

25MHZ_C

25MHZ_B

25MHZ_A

X1

X2

VDD_RTC_OUT

THRMGND

32KHZ_A

NCNC

OUT

OUT

OUT

OUT

OUT

OUT

IN

NC

NC

OUT

OUT

OUT

IN

IN

IN

OUT

OUT

OUT

IN

IN

BIIN

NC

OUT

OUT

08

Y1

Y2

GNDB2

VCC

A1B1A2

IN

IN

IN

OUT

D SG

D

SG

IN

OUT

D

G S

IN

OUT

OUT

OUT

IN

Apple Inc.


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outputs for power savings

No bypass necessary

internally ORed to

create VDD_RTC_OUT.

+V3.3A should be first

available ~3.3V power

TBT XTAL Power

Scrub for Layout Optimization

to reduce VBAT draw.

Coin-Cell & No G3Hot: 3.3V S5

Powered in S0

PCH uses HDA_SDO as a power-up strap. If low, ME functions normally.If high, ME is disabled. This allows for full re-flashing of SPI ROM.

Q2620 & 5V pull-up allows circuit to work regardless of HDA voltage.SMC controls strap enable to allow in-field control of strap setting.

IPD = 9-50k

NOTE: 30 PPM crystal required

SB XTAL Power

PCH S0 PWRGD

PCH Reset Button

PCH ME Disable Strap

Unbuffered

DP_AUXIO_EN Inversion

GreenClk 25MHz Power

Platform Reset Connections

For SB RTC Power

VTT voltage divider on CPU page

Coin-Cell & G3Hot: 3.42V G3Hot

No Coin-Cell: 3.42V G3Hot (no RC)

Coin-Cell: VBAT (300-ohm & 10uF RC)

System RTC Power Source & 32kHz / 25MHz Clock Generator

Buffered

Ground VDDIO of unused CLK

VBAT and +V3.3A are

No Coin-Cell: 3.3V S5

Buffered

GPIO Glitch Prevention

16 68

16 68

33 68

0201

20%

6.3VX5R

1UF

0201

20%

6.3V

1UF

X5R

CRITICAL

SLG3NB148ATQFN

25.000MHZ-12PF-20PPM

CRITICAL

SM-3.2X2.5MM

5%

12PF

25V

NP0-C0G

201

12PF

5%

25V

201

NP0-C0G

6 42 68

6 37

31

23

36

10 23

33

MF

201

1/20W5%

5%

33

1/20W

201

MF

5%

0

1/20WMF201

18 26

201MF

1/20W

1K

5%

XDP

0

5%1/20W

MF201

100K

1/20WMF201

5%

74LVC1G07SC70

10%

0201X5R-CERM

16V

0.1UF

40 68

6 42 68

16 68

PLACE_NEAR=U1800.G51:5.1mm

5%1/20W

22

MF

201

PLACE_NEAR=U1800.E49:5.1mm

5%

22

1/20W

MF201

PLACE_NEAR=U1800.G45:2.54MM:5.1mm 22

5%

1/20WMF201

18 68

18 68

18 68

17 23 40

17 25

17

NO STUFF


0

MF

1/20W

201

5%

NO STUFF

0

MF1/20W5%

201

MF

3.0K

1/20W5%

201

201

5%1/20WMF

0

X5R-CERM0201

16V10%

0.1UF

MC74VHC1G08

SC70-HF

16V

X5R-CERM

10%

0.1UF

0201

PLACE_NEAR=U1800.P12:7mm

SC70-HF

MC74VHC1G08

1K5%

1/20W

MF

201

23 40 51 61

56

17 40 10 23 65

0201

0.1UF10%

16VX5R-CERM

0.1UF

X5R-CERM

16V10%

0201

5%

201

0

MF

1/20W

201

1/20W

MF

5%

NO STUFF

1M

201

MF

1/20W

5%

0

XDP

NO STUFF

402

SILK_PART=SYS RESET

05%1/16WMF-LF

201

1/20WMF

10K5%

19 33

6 39

0201

0.1UF10%16VX5R-CERM

CRITICAL

74LVC2G08GT

SOT833

16

6 17 40 42

19 23

100K

MF201

5%1/20W

1K

MF201

5%1/20W

16 68

SSM6N37FEAPESOT563

SOT563SSM6N37FEAPE

40

63

0.1UF

X5R-CERM16V10%

0201

201

5%

MF1/20W

10K

SOD-VESM-HF

SSM3K15FV

CRITICAL

MF

10K5%

201

1/20W

NO STUFF

16 23

MC74VHC1G08SC70-HF

CRITICAL

0

1/20WMF

5%

201

40

MF

201

1/20W5%

100K

0201

10%

X5R-CERM16V

0.1UF

35

64

0

MF1/20W

201

5%

201

5%1/20W

MF

0

17 25

Clock (CK505) and Chipset Support


SYSCLK_CLK25M_X1

PM_PCH_PWROK

LPC_PWRDWN_L

PLT_RESET_L

TBT_RESET_LMAKE_BASE=TRUE

=TBT_RESET_L

SMC_LRESET_L

PLT_RST_BUF_L

BKLT_PLT_RST_L

ALL_SYS_PWRGD

CPUIMVP_PGOOD

=PP3V3_S5_PCHPWRGD

PM_S0_PGOOD

=PP3V3_S3_PCH_GPIO

AUD_IPHS_SWITCH_EN

TBT_PWR_EN_PCH TBT_PWR_EN

PM_PCH_APWROK

=PPVDDIO_S0_SBCLK

PLT_RST_CPU_BUF_LMAKE_BASE=TRUE

=PPVBAT_G3H_SYSCLK

CPU_RESET_L

LPCPLUS_RESET_LMAKE_BASE=TRUE

DP_AUXIO_EN

XDPPCH_PLTRST_L

DP_AUXCH_ISOL

=PP3V3_S0_PCH_GPIOPM_PCH_SYS_PWROK

=PP3V3_S0_SB_PM

SYS_PWROK_R

PM_PCH_PWROKMAKE_BASE=TRUE

=PP3V3_S5_PCHPWRGD


LPC_CLK33M_LPCPLUS_R

PCH_CLK33M_PCIOUT

LPC_CLK33M_SMC_R

LPC_CLK33M_LPCPLUS

PCH_CLK33M_PCIIN

SYSCLK_CLK25M_X2

SYSCLK_CLK25M_SB

LPC_CLK33M_SMC

SMC_DELAYED_PWRGD

XDP_DBRESET_L

=PP5V_S0_PCH


SPI_DESCRIPTOR_OVERRIDE_LS5V

HDA_SDOUT_R

SPI_DESCRIPTOR_OVERRIDE

SPI_DESCRIPTOR_OVERRIDE_L

SYSCLK_CLK32K_RTC

SSD_RESET_L

SYSCLK_CLK25M_TBT

PM_SYSRST_L

=PP3V3_S0_SB_PM

=PP3V3_S5_SYSCLK

SYSCLK_CLK25M_X2_R

=PP3V3_S0_RSTBUF

=PP3V3_S0_RSTBUF

AP_RESET_L

PCA9557D_RESET_L

=PPVDDIO_TBT_CLK

=PPVRTC_G3_OUT

=PP3V3_S0_SYSCLKGEN

C27021

2

C27101

2

U2700

9

8

15

12

7 10

16

13

2

17

5

1

11

6

14

4

3

Y270524

13

C2705

12

C2706

1 2

R2783

1 2

R2781

1 2

R2771

1 2

R2789

1 2

R2793

1 2

R27801

2

U2780

2

3

5

4

C2780 1

2

R2727

1 2

R2726

1 2

R2729

1 2

R27611

2

R2763

1 2

R2762

1 2

R2760

1 2

C27601

2

U2760

3

2

1

4

5

C27501

2

U2750

3

2

1

4

5

R27501

2

C2722 1

2

C2724 1

2

R2705

1 2

R27061

2

R2796

1 2

R27971

2

R27951

2

C27521

2U2752

1

5

2

6

4

8

7

3

R27201

2

R27211

2

Q2720

3

54

Q2720 6

2 1

C2739 1

2

R27301 2

Q2730 3

12

R27311

2

U2771

3

2

1

4

5

R2772

1 2R27701

2

C2771 1

2

R2788

1 2

R2773

1 2

051-9276

2.7.0

27 OF 109

25 OF 72

1

68

7 25

7 18

7

7

7 16 17 18 19 35

7 25

7 25

68

35 40 41

7 22

7 20 22

7 25

7

68

7 25

7 25

7

7

7

IN

IN

D

SG

D

S G

D

SG

D

SG

OUT

OUT

DSG

D SG

IN

IN

OUT

G

D

S

D

SG

IN

D

SG

IN

S0_READY

ISOL*

S0_EN

S3_EN

RST_IN*

GNDTHRM

VDD

VTT_EN

VDDIO_EN

RST_OUT*

PAD

OUT

OUT

IN

IN

IN

IN

OUT

IN

D

SG

D

S G

OUT

Apple Inc.


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6 3



1 0 1 1 1 1 1 1 1

0 1 1 1 1 1 CPU_MEM_RESET_L 1 1

Step ISOLATE_CPU_MEM_L PLT_RESET_L PM_SLP_S3_L PM_SLP_S4_L CPU_MEM_RESET_L MEM_RESET_L MEMVTT_EN P1V5CPU_EN

S0

2 0 0 1 1 1 1 0 1

3 0 0 0 1 X 1 0 0

4 0 0 1 1 X 1 0 1

5 0 1 1 1 0 (*) 1 1 1

6 0 1 1 1 1 1 1 1

WHEN LOW: CPU 1.5V follows S0 rails, VTT ensures clean CKE transition, MEM_RESET_L isolated.

The circuit below handles CPU and VTT power during S0->S3->S0 transitions, as well1V5 S0 "PGOOD" for CPU

75mA max load @ 0.75V

60mW max power

to

S3

to

S0

NOTE: In the event of a S3->S5 transition ISOLATE_CPU_MEM_L will still be asserted on next S5->S0

(*) CPU_MEM_RESET_L asserts due to loss of PM_MEM_PWRGD, must wait for software to clear before deasserting ISOLATE_CPU_MEM_L GPIO.

P1V5CPU_EN = (ISOLATE_CPU_MEM_L + PM_SLP_S3_L) * PM_SLP_S4_L

WHEN HIGH: CPU 1.5V remains powered in S3, VTT follows S0 rails, MEM_RESET_L not isolated.

MEMVTT ClampEnsures CKE signals are held low in S3

transition. Rails will power-up as if from S3, but MEM_RESET_L will not properly assert. Software

must deassert ISOLATE_CPU_MEM_L and then generate a valid reset cycle on CPU_MEM_RESET_L.

7 1 1 1 1 1 CPU_MEM_RESET_L 1 1

PM_MEM_PWRGD pull-up to CPU VTT rail is on CPU page

MEMVTT_EN = (ISOLATE_CPU_MEM_L + PLT_RST_L) * PM_SLP_S3_L

MEM_RESET_L = !ISOLATE_CPU_MEM_L + CPU_MEM_RESET_L

ISOLATE_CPU_MEM_L GPIO state during S3<->S0 transitions determines behavior of signals.

as isolating the CPU’s SM_DRAMRST# output from the SO-DIMMs when necessary.

17 26 36 40 48 61

10K5%1/20WMF201

CPUMEM_SLG:NO

18 25 26

SOT563SSM6N37FEAPE

CPUMEM_SLG:NO

SSM6N37FEAPESOT563

CPUMEM_SLG:NO

201MF

100K1/20W

5%

CPUMEM_SLG:NO

SOT563SSM6N37FEAPE

CPUMEM_SLG:NO

100K5%

1/20WMF201

CPUMEM_SLG:NO

SOT563

CPUMEM_SLG:NO

SSM6N37FEAPE

26 60

1/20WMF

5%

201

1K

26 27 28 29 30

CPUMEM_SLG:NO

SSM6N37FEAPESOT563

CPUMEM_SLG:NO

SSM6N37FEAPESOT563

23 26

5%

MF

100K

201

1/20W

CPUMEM_SLG:NO

10 26

10 17 65

10K5%1/20WMF201

CPUMEM_SLG:NO

MF-LF603

5%1/10W

10

SOT-563

CRITICAL

DMB53D0UV

201MF1/20W5%10K

CRITICAL

SOT-563DMB53D0UV

NO STUFF

X7R

10%

201

16V

1000PF

SSM6N37FEAPESOT563

10%1000PF

201X7R16V

NO STUFF

100K5%

MF201

1/20W

17 26 40 61

SSM6N37FEAPESOT563

201MF

1%27.4K1/20W

8 55

0201

10%

16V

X5R-CERM

0.1UF

NO STUFF

16V

10%

X7R

402

0.047UF

0

201

5%1/20WMF

CPUMEM_SLG:NO

TQFNSLG4AP022

CPUMEM_SLG:YES

8 26

26 27 28 29 30

23 26

18 25 26

17 26 40 61

17 26 36 40 48 61

26 60

10 26

10%

201X5R

6.3V0.1UF

CPUMEM_SLG:YES

SOT563SSM6N37FEAPE

CPUMEM_SLG:NO43.2K

1%1/20W

MF201

SOT563SSM6N37FEAPE

CPUMEM_SLG:NO

8 26

CPU Memory S3 Support


P1V5_S0_DIV


PLT_RESET_L

=MEM_RESET_L

ISOLATE_CPU_MEM_L

PM_SLP_S3_L

PM_SLP_S4_L

=PP3V3_S3_MEMRESET

CPU_MEM_RESET_LMAKE_BASE=TRUE

PM_SLP_S3_L

MEMVTT_EN

MEMVTT_EN

P1V5CPU_EN_L

MEMVTT_EN_L

PM_SLP_S4_L

P1V5CPU_EN

=PP1V5_S3_MEMRESET

ISOLATE_CPU_MEM_L

=MEM_RESET_L

VTTCLAMP_L

=PP5V_S3_MEMRESET

VTTCLAMP_EN

=DDRVTT_EN

P1V5CPU_EN

MEM_RESET_L=PPVTT_S0_VTTCLAMP


PM_MEM_PWRGD

PM_MEM_PWRGD_L

=PP3V3_S3_MEMRESET

PLT_RESET_L

ISOLATE_CPU_MEM_L_R

=PP5V_S3_MEMRESET

MEMRESET_ISOL_LS5V_L

MEM_RESET_L

R28051

2

Q2805 6

2 1

Q28053

54

R28101

2

Q2810 6

2 1

Q28103

54

R28011

2

Q2800 3

5 4

R28021

2

Q2800 6

2 1

R28161

2

Q2815

3

54

Q2815

6

21

R28151

2

R28501

2

Q28206

2

1

R28221

2

Q28205

3

4

C2820 1

2

Q2850 6

2 1

C2851 1

2

R28511

2

Q2850 3

5 4

R28201

2

C2816 1

2

C2817 1

2

R289012

U2800

5

9

7

8

3

1

6

11

10

4

2

C2800 1

2

R28211

2

051-9276

2.7.0

28 OF 109

26 OF 72

7 10 12 15

7 26

7

7 26

7

7

7 26

7 26

31

NF_DQ6

NF_DQ7

NF_DQ5

NF_DQ4

A1

VREFDQ

VREFCA VDD VDDQ

ODT0

ODT1

RESET*

ZQ0

A0

A2

A3

A4

A6

A10/AP

A11

A12/BC*

A13

A14

BA0

BA1

BA2

CKE1

RAS*

WE*

CAS*

CS1*

CS0*

ZQ1

DQ0

DQ1

DQ2

DQ3

DQS*

DM/TDQS

NF_TDQS*

NC

VSS

CK*

CKE0

DQS

CK

VSSQ

A8

A9

A5

A7

A15

NF_DQ6

NF_DQ7

NF_DQ5

NF_DQ4

A1

VREFDQ

VREFCA VDD VDDQ

ODT0

ODT1

RESET*

ZQ0

A0

A2

A3

A4

A6

A10/AP

A11

A12/BC*

A13

A14

BA0

BA1

BA2

CKE1

RAS*

WE*

CAS*

CS1*

CS0*

ZQ1

DQ0

DQ1

DQ2

DQ3

DQS*

DM/TDQS

NF_TDQS*

NC

VSS

CK*

CKE0

DQS

CK

VSSQ

A8

A9

A5

A7

A15

NF_DQ6

NF_DQ7

NF_DQ5

NF_DQ4

A1

VREFDQ

VREFCA VDD VDDQ

ODT0

ODT1

RESET*

ZQ0

A0

A2

A3

A4

A6

A10/AP

A11

A12/BC*

A13

A14

BA0

BA1

BA2

CKE1

RAS*

WE*

CAS*

CS1*

CS0*

ZQ1

DQ0

DQ1

DQ2

DQ3

DQS*

DM/TDQS

NF_TDQS*

NC

VSS

CK*

CKE0

DQS

CK

VSSQ

A8

A9

A5

A7

A15

NF_DQ6

NF_DQ7

NF_DQ5

NF_DQ4

A1

VREFDQ

VREFCA VDD VDDQ

ODT0

ODT1

RESET*

ZQ0

A0

A2

A3

A4

A6

A10/AP

A11

A12/BC*

A13

A14

BA0

BA1

BA2

CKE1

RAS*

WE*

CAS*

CS1*

CS0*

ZQ1

DQ0

DQ1

DQ2

DQ3

DQS*

DM/TDQS

NF_TDQS*

NC

VSS

CK*

CKE0

DQS

CK

VSSQ

A8

A9

A5

A7

A15

Apple Inc.


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SHEET


R

DSIZEDRAWING NUMBER

REVISION

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6 3



A14/A15 FOR 2G/4G MONO ONLY

CS1 IS FOR 2G DDP RANK CONTROL

NCNC

NCNC NC

NC

NC

NC

1%

240

MF 1/20W201

240

1/20W1%MF201

CERM-X5R-1201

0.47UF

4V

20%

1/20WMF

240

1%2011% 1/20W

240

MF201

512MX8-4GBIT-DDR3-1600

OMIT_TABLE

MT41K1G4

FBGA-9P5X11P65-COMBOOMIT_TABLE

FBGA-9P5X11P65-COMBO

MT41K1G4


OMIT_TABLEFBGA-9P5X11P65-COMBO

MT41K1G4


OMIT_TABLE


MT41K1G4


1% 1/20W

240

MF201

1% 1/20W

240

MF201

1% 1/20W

240

MF201

1% 1/20W

240

MF201

CERM-X5R-1201

0.47UF

4V

20% 20%

4V

CERM-X5R-1

0.47UF

201

201

20%

4V

CERM-X5R-1

0.47UF 0.47UF

CERM-X5R-1

4V

20%

201

0.47UF

CERM-X5R-1

4V

20%

201201

0.47UF

CERM-X5R-1

4V

20%

201CERM-X5R-1

0.47UF

4V

20%

20%

4V

CERM-X5R-1

0.47UF

201201CERM-X5R-1

4V

20%

0.47UF

201

0.47UF20%

4V

CERM-X5R-1201

20%

4V

CERM-X5R-1

0.47UF

SYNC_MASTER=J13_MLB

DDR3 DRAM CHANNEL A (0-31)


MEM_A_DQ<2>

MEM_A_A<7>


MEM_A_A<9>

MEM_A_CLK_P<0>

MEM_A_RAS_L

MEM_A_WE_L

MEM_A_ODT<0>




MEM_A_A<3>

MEM_A_A<4>

MEM_A_A<5>

MEM_A_A<2>

MEM_A_A<8>

MEM_A_A<4>

MEM_A_BA<0>

MEM_RESET_L

MEM_A_A<0>

MEM_A_DQ<30>

MEM_A_DQ<31>

MEM_A_DQ<24>

MEM_A_DQ<29>

MEM_A_A<1>

MEM_A_ODT<0>

MEM_A_A<0>

MEM_A_A<2>

MEM_A_A<3>

MEM_A_A<4>

MEM_A_A<5>

MEM_A_A<6>

MEM_A_A<10>

MEM_A_A<11>

MEM_A_A<12>

MEM_A_A<13>

MEM_A_A<14>

MEM_A_BA<0>

MEM_A_BA<1>

MEM_A_BA<2>

MEM_A_CKE<1>

MEM_A_WE_L

MEM_A_CAS_L

MEM_A_CS_L<1>

MEM_A_CS_L<0>

MEM_A_DQ<28>

MEM_A_DQ<25>

MEM_A_DQ<27>

MEM_A_DQ<26>

MEM_A_DQS_N<3>

MEM_A_CLK_N<0>

MEM_A_CKE<0>

MEM_A_DQS_P<3>

MEM_A_A<7>

MEM_A_DQ<18>

MEM_A_DQ<21>

MEM_A_DQ<16>

MEM_A_DQ<22>

MEM_A_A<1>

MEM_A_ODT<1>

MEM_RESET_L

MEM_A_A<0>

MEM_A_A<2>

MEM_A_A<3>

MEM_A_A<4>

MEM_A_A<5>

MEM_A_A<6>

MEM_A_A<10>

MEM_A_A<11>

MEM_A_A<12>

MEM_A_A<13>

MEM_A_BA<0>

MEM_A_BA<1>

MEM_A_BA<2>

MEM_A_CKE<1>

MEM_A_RAS_L

MEM_A_WE_L

MEM_A_CAS_L

MEM_A_CS_L<1>

MEM_A_CS_L<0>

MEM_A_DQ<19>

MEM_A_DQ<17>

MEM_A_DQ<23>

MEM_A_DQ<20>

MEM_A_DQS_N<2>

MEM_A_CLK_N<0>

MEM_A_CKE<0>

MEM_A_DQS_P<2>

MEM_A_CLK_P<0>

MEM_A_A<8>

MEM_A_A<9>

MEM_A_A<7>

MEM_A_DQ<13>

MEM_A_DQ<15>

MEM_A_DQ<11>

MEM_A_DQ<10>

MEM_A_A<1>

MEM_A_ODT<1>

MEM_A_A<2>

MEM_A_A<3>

MEM_A_A<5>

MEM_A_A<6>

MEM_A_A<10>

MEM_A_A<11>

MEM_A_A<13>

MEM_A_BA<1>

MEM_A_BA<2>

MEM_A_CKE<1>

MEM_A_RAS_L

MEM_A_CAS_L

MEM_A_CS_L<0>

MEM_A_DQ<8>

MEM_A_DQ<9>

MEM_A_DQ<12>

MEM_A_DQS_N<1>

MEM_A_CLK_N<0>

MEM_A_CKE<0>

MEM_A_DQS_P<1>

MEM_A_CLK_P<0>

MEM_A_A<9>

MEM_A_DQ<5>

MEM_A_DQ<6>

MEM_A_ODT<0>

MEM_A_ODT<1>

MEM_A_A<11>

MEM_A_A<12>

MEM_A_A<13>

MEM_A_BA<1>

MEM_A_BA<2>

MEM_A_CKE<1>

MEM_A_RAS_L

MEM_A_WE_L

MEM_A_CAS_L

MEM_A_CS_L<1>

MEM_A_CS_L<0>

MEM_A_DQ<1>

MEM_A_DQS_N<0>

MEM_A_CLK_N<0>

MEM_A_CKE<0>

MEM_A_DQS_P<0>

MEM_A_CLK_P<0>

MEM_A_DQ<4>

MEM_A_DQ<3>


MEM_A_CS_L<1>

MEM_A_ODT<1>

MEM_A_DQ<7>

MEM_A_A<14>

MEM_A_A<10>

MEM_A_A<0>

MEM_A_BA<0>

MEM_A_A<9>

MEM_A_A<7>

MEM_A_A<6>

MEM_RESET_L

MEM_A_ZQ0MEM_A_ZQ1

MEM_A_ZQ5

MEM_A_A<12>

MEM_A_A<1>

MEM_A_ZQ2

MEM_A_ZQ6 MEM_A_ZQ7

MEM_A_ZQ3

MEM_RESET_L

MEM_A_ZQ4

MEM_A_ZQ5

MEM_A_ZQ6

MEM_A_ZQ7

MEM_A_ZQ4

PP0V75_S3_MEM_VREFDQ_A =PP1V5_S3_MEM_A

PP0V75_S3_MEM_VREFCA_A

PP0V75_S3_MEM_VREFDQ_A =PP1V5_S3_MEM_APP0V75_S3_MEM_VREFDQ_A

MEM_A_ODT<0>


=PP1V5_S3_MEM_A PP0V75_S3_MEM_VREFDQ_A


=PP1V5_S3_MEM_A


R29301 2R29201 2

C2900 1

2

R29101 2R29001 2

U2930

K3

L7

H7

M7

K7

N3

N7

J7

L3

K2

L8

L2

M8

M2

N8

M3

J2

K8

J3

G3

F7

G7

G9

F9

H2

H1

B7

B3

C7

C2

C8

C3

D3

A3

79

80

81

82

E3

E8

D2

E7

A7

G1

F1

F3

N2

A2

A9

D7

G2

G8

K1

K9

M1

M9

B9

C1

E2

E9

J8

E1

A1

A8

N1

N9

B1

D8

F2

F8

J1

J9

L1

L9

B2

B8

C9

D1

D9

H3

H8

H9

U2920

K3

L7

H7

M7

K7

N3

N7

J7

L3

K2

L8

L2

M8

M2

N8

M3

J2

K8

J3

G3

F7

G7

G9

F9

H2

H1

B7

B3

C7

C2

C8

C3

D3

A3

79

80

81

82

E3

E8

D2

E7

A7

G1

F1

F3

N2

A2

A9

D7

G2

G8

K1

K9

M1

M9

B9

C1

E2

E9

J8

E1

A1

A8

N1

N9

B1

D8

F2

F8

J1

J9

L1

L9

B2

B8

C9

D1

D9

H3

H8

H9

U2910

K3

L7

H7

M7

K7

N3

N7

J7

L3

K2

L8

L2

M8

M2

N8

M3

J2

K8

J3

G3

F7

G7

G9

F9

H2

H1

B7

B3

C7

C2

C8

C3

D3

A3

79

80

81

82

E3

E8

D2

E7

A7

G1

F1

F3

N2

A2

A9

D7

G2

G8

K1

K9

M1

M9

B9

C1

E2

E9

J8

E1

A1

A8

N1

N9

B1

D8

F2

F8

J1

J9

L1

L9

B2

B8

C9

D1

D9

H3

H8

H9

U2900

K3

L7

H7

M7

K7

N3

N7

J7

L3

K2

L8

L2

M8

M2

N8

M3

J2

K8

J3

G3

F7

G7

G9

F9

H2

H1

B7

B3

C7

C2

C8

C3

D3

A3

79

80

81

82

E3

E8

D2

E7

A7

G1

F1

F3

N2

A2

A9

D7

G2

G8

K1

K9

M1

M9

B9

C1

E2

E9

J8

E1

A1

A8

N1

N9

B1

D8

F2

F8

J1

J9

L1

L9

B2

B8

C9

D1

D9

H3

H8

H9

R29011 2

R29111 2

R29211 2

R29311 2

C2901 1

2

C2902 1

2

C2910 1

2

C2911 1

2

C2912 1

2

C2920 1

2

C2921 1

2

C2922 1

2

C2930 1

2

C2931 1

2

C2932 1

2

29 OF 109

051-9276

2.7.0

27 OF 72

11 66

11 27 28 32 66

11 27 28 32 66 11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66 11 27 28 32 66

11 27 28 32 66 11 27 28 32 66

11 27 28 32 66 11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

26 27 28 29 30

11 27 28 32 66

11 66

11 66

11 66

11 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 66

11 66

11 66

11 66

11 66

11 27 28 32 66

11 27 28 32 66

11 66

11 27 28 32 66

11 66

11 66

11 66

11 66

11 27 28 32 66

11 27 28 32 66

26 27 28 29 30

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 66

11 66

11 66

11 66

11 66

11 27 28 32 66

11 27 28 32 66

11 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 66

11 66

11 66

11 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 66

11 66

11 66

11 66

11 27 28 32 66

11 27 28 32 66

11 66

11 27 28 32 66

11 27 28 32 66

11 66

11 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 66

11 66

11 27 28 32 66

11 27 28 32 66

11 66

11 27 28 32 66

11 66

11 66

11 66 11 66

11 27 28 32 66

11 27 28 32 66

11 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

26 27 28 29 30

11 27 28 32 66

11 27 28 32 66

26 27 28 29 30

27

27

27

27

27 28 31 66 7 27 28 32

27 28 31 66

27 28 31 66 7 27 28 32

27 28 31 66

11 27 28 32 66

27 28 31 66

7 27 28 32 27 28 31 66

27 28 31 66

7 27 28 32

27 28 31 66

NF_DQ6

NF_DQ7

NF_DQ5

NF_DQ4

A1

VREFDQ

VREFCA VDD VDDQ

ODT0

ODT1

RESET*

ZQ0

A0

A2

A3

A4

A6

A10/AP

A11

A12/BC*

A13

A14

BA0

BA1

BA2

CKE1

RAS*

WE*

CAS*

CS1*

CS0*

ZQ1

DQ0

DQ1

DQ2

DQ3

DQS*

DM/TDQS

NF_TDQS*

NC

VSS

CK*

CKE0

DQS

CK

VSSQ

A8

A9

A5

A7

A15

NF_DQ6

NF_DQ7

NF_DQ5

NF_DQ4

A1

VREFDQ

VREFCA VDD VDDQ

ODT0

ODT1

RESET*

ZQ0

A0

A2

A3

A4

A6

A10/AP

A11

A12/BC*

A13

A14

BA0

BA1

BA2

CKE1

RAS*

WE*

CAS*

CS1*

CS0*

ZQ1

DQ0

DQ1

DQ2

DQ3

DQS*

DM/TDQS

NF_TDQS*

NC

VSS

CK*

CKE0

DQS

CK

VSSQ

A8

A9

A5

A7

A15

NF_DQ6

NF_DQ7

NF_DQ5

NF_DQ4

A1

VREFDQ

VREFCA VDD VDDQ

ODT0

ODT1

RESET*

ZQ0

A0

A2

A3

A4

A6

A10/AP

A11

A12/BC*

A13

A14

BA0

BA1

BA2

CKE1

RAS*

WE*

CAS*

CS1*

CS0*

ZQ1

DQ0

DQ1

DQ2

DQ3

DQS*

DM/TDQS

NF_TDQS*

NC

VSS

CK*

CKE0

DQS

CK

VSSQ

A8

A9

A5

A7

A15

NF_DQ6

NF_DQ7

NF_DQ5

NF_DQ4

A1

VREFDQ

VREFCA VDD VDDQ

ODT0

ODT1

RESET*

ZQ0

A0

A2

A3

A4

A6

A10/AP

A11

A12/BC*

A13

A14

BA0

BA1

BA2

CKE1

RAS*

WE*

CAS*

CS1*

CS0*

ZQ1

DQ0

DQ1

DQ2

DQ3

DQS*

DM/TDQS

NF_TDQS*

NC

VSS

CK*

CKE0

DQS

CK

VSSQ

A8

A9

A5

A7

A15

Apple Inc.


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6 3




NCNC

NC


NC

NC

NC

NC

NC

NC NC

NC

NC

201

1/20W1%MF

240

2011/20W1%MF

240

0.47UF

201CERM-X5R-1

4V

20%

2011/20W1%MF

240

OMIT_TABLE


MT41K1G4

FBGA-9P5X11P65-COMBOFBGA-9P5X11P65-COMBO


MT41K1G4

OMIT_TABLEOMIT_TABLE


MT41K1G4



MT41K1G4

FBGA-9P5X11P65-COMBOOMIT_TABLE

201

1/20WMF

240

1%

201 1%MF

240

1/20W

1%201 1/20W

240

MF

201 1/20W1%

240

MF

201 1% 1/20W

240

MF

201CERM-X5R-1

0.47UF

4V

20% 20%

4V

0.47UF

CERM-X5R-1201 201

20%

4V

0.47UF

CERM-X5R-1201

20%

4V

0.47UF

CERM-X5R-1CERM-X5R-1

0.47UF

4V

20%

201 201

CERM-X5R-1

0.47UF

4V

20%

201

CERM-X5R-1

0.47UF

4V

20%

201

20%

4V

0.47UF

CERM-X5R-1201

20%

4V

0.47UF

CERM-X5R-1201

20%

4V

0.47UF

CERM-X5R-1201

20%

4V

0.47UF

CERM-X5R-1

DDR3 DRAM CHANNEL A (32-63)


MEM_A_A<10>

MEM_A_ZQ14

MEM_A_ZQ15

MEM_A_ZQ11

MEM_A_ZQ14

MEM_A_ZQ10MEM_A_ZQ13

MEM_A_ZQ9MEM_A_ZQ12

MEM_A_ZQ8

MEM_A_A<1>

MEM_A_ZQ13

MEM_A_ZQ15

MEM_A_ZQ12


MEM_A_ODT<0>

MEM_A_DQS_N<4>

MEM_A_DQ<38>

MEM_A_DQ<32>

MEM_A_DQ<37>

MEM_A_DQ<36>

MEM_A_ODT<0>

MEM_RESET_L

MEM_A_A<0>

MEM_A_A<2>

MEM_A_A<3>

MEM_A_A<4>

MEM_A_A<5>

MEM_A_A<6>

MEM_A_A<10>

MEM_A_A<11>

MEM_A_A<12>

MEM_A_A<13>

MEM_A_BA<0>

MEM_A_BA<1>

MEM_A_BA<2>

MEM_A_CKE<1>

MEM_A_RAS_L

MEM_A_WE_L

MEM_A_CAS_L

MEM_A_CS_L<1>

MEM_A_CS_L<0>

MEM_A_DQ<39>

MEM_A_DQ<34>

MEM_A_DQ<35>

MEM_A_CLK_N<0>

MEM_A_CKE<0>

MEM_A_DQS_P<4>

MEM_A_CLK_P<0>

MEM_A_A<8>

MEM_A_A<9>

MEM_A_A<7>MEM_A_DQ<47>

MEM_A_DQ<42>

MEM_A_DQ<40>

MEM_A_DQ<43>

MEM_A_A<1>

MEM_A_ODT<0>

MEM_A_ODT<1>

MEM_RESET_L

MEM_A_A<0>

MEM_A_A<2>

MEM_A_A<3>

MEM_A_A<4>

MEM_A_A<5>

MEM_A_A<6>

MEM_A_A<11>

MEM_A_A<12>

MEM_A_A<13>

MEM_A_BA<0>

MEM_A_CKE<1>

MEM_A_RAS_L

MEM_A_WE_L

MEM_A_CAS_L

MEM_A_CS_L<1>

MEM_A_CS_L<0>

MEM_A_DQ<41>

MEM_A_DQ<46>

MEM_A_DQ<44>

MEM_A_DQ<45>

MEM_A_DQS_N<5>

MEM_A_CKE<0>

MEM_A_DQS_P<5>

MEM_A_A<8>

MEM_A_A<9>

MEM_A_A<7>MEM_A_DQ<54>

MEM_A_DQ<52>

MEM_A_DQ<53>

MEM_A_DQ<48>

MEM_A_A<1>

MEM_A_ODT<1>

MEM_RESET_L

MEM_A_A<0>

MEM_A_A<2>

MEM_A_A<4>

MEM_A_A<5>

MEM_A_A<6>

MEM_A_A<10>

MEM_A_A<11>

MEM_A_A<12>

MEM_A_A<13>

MEM_A_BA<0>

MEM_A_BA<1>

MEM_A_BA<2>

MEM_A_CKE<1>

MEM_A_RAS_L

MEM_A_WE_L

MEM_A_CAS_L

MEM_A_CS_L<1>

MEM_A_CS_L<0>

MEM_A_DQ<49>

MEM_A_DQ<55>

MEM_A_DQ<51>

MEM_A_DQS_N<6>

MEM_A_CLK_N<0>

MEM_A_CKE<0>

MEM_A_DQS_P<6>

MEM_A_CLK_P<0>

MEM_A_A<8>

MEM_A_A<9>

MEM_A_A<7>

MEM_A_DQ<62>

MEM_A_DQ<60>

MEM_A_DQ<61>

MEM_A_DQ<58>

MEM_A_ODT<0>

MEM_A_ODT<1>

MEM_RESET_L

MEM_A_A<0>

MEM_A_A<2>

MEM_A_A<4>

MEM_A_A<5>

MEM_A_A<6>

MEM_A_A<12>

MEM_A_A<13>

MEM_A_BA<0>

MEM_A_BA<1>

MEM_A_BA<2>

MEM_A_CKE<1>

MEM_A_RAS_L

MEM_A_WE_L

MEM_A_CAS_L

MEM_A_CS_L<1>

MEM_A_CS_L<0>

MEM_A_DQ<57>

MEM_A_DQ<63>

MEM_A_DQ<56>

MEM_A_DQS_N<7>

MEM_A_CLK_N<0>

MEM_A_CKE<0>

MEM_A_DQS_P<7>

MEM_A_CLK_P<0>

MEM_A_A<8>

MEM_A_A<7>

MEM_A_DQ<33>

MEM_A_ODT<1>

MEM_A_CLK_N<0>

MEM_A_BA<2>

MEM_A_CLK_P<0>

MEM_A_BA<1>

MEM_A_A<14>



MEM_A_A<15>

MEM_A_A<14>

MEM_A_A<15>

MEM_A_A<10>

MEM_A_A<11>

MEM_A_A<9>

MEM_A_A<1>







MEM_A_DQ<50>

PP0V75_S3_MEM_VREFDQ_A

MEM_A_DQ<59>


=PP1V5_S3_MEM_A

R30301 2R30201 2R30101 2

C3000 1

2

R30001 2

U3000

K3

L7

H7

M7

K7

N3

N7

J7

L3

K2

L8

L2

M8

M2

N8

M3

J2

K8

J3

G3

F7

G7

G9

F9

H2

H1

B7

B3

C7

C2

C8

C3

D3

A3

79

80

81

82

E3

E8

D2

E7

A7

G1

F1

F3

N2

A2

A9

D7

G2

G8

K1

K9

M1

M9

B9

C1

E2

E9

J8

E1

A1

A8

N1

N9

B1

D8

F2

F8

J1

J9

L1

L9

B2

B8

C9

D1

D9

H3

H8

H9

U3010

K3

L7

H7

M7

K7

N3

N7

J7

L3

K2

L8

L2

M8

M2

N8

M3

J2

K8

J3

G3

F7

G7

G9

F9

H2

H1

B7

B3

C7

C2

C8

C3

D3

A3

79

80

81

82

E3

E8

D2

E7

A7

G1

F1

F3

N2

A2

A9

D7

G2

G8

K1

K9

M1

M9

B9

C1

E2

E9

J8

E1

A1

A8

N1

N9

B1

D8

F2

F8

J1

J9

L1

L9

B2

B8

C9

D1

D9

H3

H8

H9

U3020

K3

L7

H7

M7

K7

N3

N7

J7

L3

K2

L8

L2

M8

M2

N8

M3

J2

K8

J3

G3

F7

G7

G9

F9

H2

H1

B7

B3

C7

C2

C8

C3

D3

A3

79

80

81

82

E3

E8

D2

E7

A7

G1

F1

F3

N2

A2

A9

D7

G2

G8

K1

K9

M1

M9

B9

C1

E2

E9

J8

E1

A1

A8

N1

N9

B1

D8

F2

F8

J1

J9

L1

L9

B2

B8

C9

D1

D9

H3

H8

H9

U3030

K3

L7

H7

M7

K7

N3

N7

J7

L3

K2

L8

L2

M8

M2

N8

M3

J2

K8

J3

G3

F7

G7

G9

F9

H2

H1

B7

B3

C7

C2

C8

C3

D3

A3

79

80

81

82

E3

E8

D2

E7

A7

G1

F1

F3

N2

A2

A9

D7

G2

G8

K1

K9

M1

M9

B9

C1

E2

E9

J8

E1

A1

A8

N1

N9

B1

D8

F2

F8

J1

J9

L1

L9

B2

B8

C9

D1

D9

H3

H8

H9

R30011 2

R30111 2

R30211 2

R30311 2

C3001 1

2

C3002 1

2

C3010 1

2

C3011 1

2

C3012 1

2

C3020 1

2

C3021 1

2

C3022 1

2

C3030 1

2

C3031 1

2

C3032 1

2

051-9276

2.7.0

30 OF 109

28 OF 72

11 27 28 32 66

28

11 27 28 32 66

28

28

28

11 27 28 32 66 11 27 28 32 66

11 27 28 32 66

11 66

11 66

11 66

11 66

11 66

11 27 28 32 66

26 27 28 29 30

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 66

11 66

11 66

11 27 28 32 66

11 27 28 32 66

11 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66 11 66

11 66

11 66

11 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

26 27 28 29 30

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 66

11 66

11 66

11 66

11 66

11 27 28 32 66

11 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66 11 66

11 66

11 66

11 66

11 27 28 32 66

11 27 28 32 66

26 27 28 29 30

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 66

11 66

11 66

11 66

11 27 28 32 66

11 27 28 32 66

11 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 66

11 66

11 66

11 66

11 27 28 32 66

11 27 28 32 66

26 27 28 29 30

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 66

11 66

11 66

11 66

11 27 28 32 66

11 27 28 32 66

11 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66 11 27 28 32 66

11 27 28 32 66 11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

11 27 28 32 66

27 28 31 66

27 28 31 66 7 27 28 32

27 28 31 66

27 28 31 66 7 27 28 32

27 28 31 66

27 28 31 66 7 27 28 32

11 66

27 28 31 66

11 66

27 28 31 66

7 27 28 32

NF_DQ6

NF_DQ7

NF_DQ5

NF_DQ4

A1

VREFDQ

VREFCA VDD VDDQ

ODT0

ODT1

RESET*

ZQ0

A0

A2

A3

A4

A6

A10/AP

A11

A12/BC*

A13

A14

BA0

BA1

BA2

CKE1

RAS*

WE*

CAS*

CS1*

CS0*

ZQ1

DQ0

DQ1

DQ2

DQ3

DQS*

DM/TDQS

NF_TDQS*

NC

VSS

CK*

CKE0

DQS

CK

VSSQ

A8

A9

A5

A7

A15

NF_DQ6

NF_DQ7

NF_DQ5

NF_DQ4

A1

VREFDQ

VREFCA VDD VDDQ

ODT0

ODT1

RESET*

ZQ0

A0

A2

A3

A4

A6

A10/AP

A11

A12/BC*

A13

A14

BA0

BA1

BA2

CKE1

RAS*

WE*

CAS*

CS1*

CS0*

ZQ1

DQ0

DQ1

DQ2

DQ3

DQS*

DM/TDQS

NF_TDQS*

NC

VSS

CK*

CKE0

DQS

CK

VSSQ

A8

A9

A5

A7

A15

NF_DQ6

NF_DQ7

NF_DQ5

NF_DQ4

A1

VREFDQ

VREFCA VDD VDDQ

ODT0

ODT1

RESET*

ZQ0

A0

A2

A3

A4

A6

A10/AP

A11

A12/BC*

A13

A14

BA0

BA1

BA2

CKE1

RAS*

WE*

CAS*

CS1*

CS0*

ZQ1

DQ0

DQ1

DQ2

DQ3

DQS*

DM/TDQS

NF_TDQS*

NC

VSS

CK*

CKE0

DQS

CK

VSSQ

A8

A9

A5

A7

A15

NF_DQ6

NF_DQ7

NF_DQ5

NF_DQ4

A1

VREFDQ

VREFCA VDD VDDQ

ODT0

ODT1

RESET*

ZQ0

A0

A2

A3

A4

A6

A10/AP

A11

A12/BC*

A13

A14

BA0

BA1

BA2

CKE1

RAS*

WE*

CAS*

CS1*

CS0*

ZQ1

DQ0

DQ1

DQ2

DQ3

DQS*

DM/TDQS

NF_TDQS*

NC

VSS

CK*

CKE0

DQS

CK

VSSQ

A8

A9

A5

A7

A15

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



NC

NC

NC

NCNC

NC

NCNC

NCNC

NC



NC

201

MF 1% 1/20W

240

201

1%MF

240

1/20W

201CERM-X5R-1

0.47UF

4V

20%

201MF 1% 1/20W

240

201 MF 1%

240

1/20W



MT41K1G4

OMIT_TABLE


MT41K1G4


OMIT_TABLE


MT41K1G4

OMIT_TABLE



MT41K1G4


201 1%

240

1/20WMF

201 MF 1/20W1%

240

201 1% 1/20W

240

MF

201 1% 1/20W

240

MF

201

0.47UF

CERM-X5R-1

4V

20%0.47UF

20%CERM-X5R-1201

4V 201

20%0.47UF

CERM-X5R-1

4V201

0.47UF

4V

CERM-X5R-120% CERM-X5R-1

0.47UF

4V

20%

201

201CERM-X5R-1

0.47UF

4V

20%

201CERM-X5R-1

0.47UF

4V

20%

0.47UF20%

4V

CERM-X5R-1201 201

20%

4V

0.47UF

CERM-X5R-1201

CERM-X5R-120%

4V

0.47UF

201

20%

4V

0.47UF

CERM-X5R-1

DDR3 DRAM CHANNEL B (0-31)


PP0V75_S3_MEM_VREFDQ_B

PP0V75_S3_MEM_VREFCA_B

MEM_B_DQ<2>

=PP1V5_S3_MEM_B

MEM_B_ODT<0>

MEM_B_DQ<3>

MEM_B_DQ<0>

MEM_B_DQ<5>

MEM_B_ZQ4

MEM_B_ZQ5

MEM_B_ZQ7

MEM_B_ZQ3

MEM_B_ZQ6

MEM_B_ZQ2MEM_B_ZQ5

MEM_B_ZQ1MEM_B_ZQ4

MEM_B_ZQ0

MEM_B_A<1>

MEM_B_A<0>

MEM_B_A<5>

MEM_B_A<12>

MEM_B_A<11>

MEM_B_A<8>

MEM_RESET_L

MEM_B_ZQ6

MEM_B_ZQ7

MEM_B_A<0>

MEM_B_A<8>

MEM_B_A<6>

MEM_B_A<7>

MEM_B_A<5>

MEM_B_A<4>

MEM_B_ODT<0>

MEM_RESET_L

MEM_B_A<3>

MEM_B_A<7>

MEM_B_A<4>

MEM_B_ODT<1>

MEM_B_DQ<1>

MEM_B_DQS_P<0>

MEM_RESET_L

MEM_B_A<0>

MEM_B_A<15>

MEM_B_A<14>

MEM_B_A<15>

MEM_B_A<14>

MEM_B_A<5>

MEM_B_A<15>


MEM_B_A<14>

MEM_B_A<10>

MEM_B_BA<0>

MEM_B_CAS_L

MEM_B_A<3>

MEM_B_DQ<23>

MEM_B_DQ<17>

MEM_B_ODT<0>

MEM_B_DQ<4>

MEM_B_DQS_N<0>

MEM_B_BA<0>

MEM_B_BA<1>

MEM_B_ODT<0>

MEM_B_ODT<1>

MEM_B_A<1>

MEM_B_A<2>

MEM_B_A<3>

MEM_B_A<4>

MEM_B_A<5>

MEM_B_A<6>

MEM_B_A<10>

MEM_B_A<11>

MEM_B_A<12>

MEM_B_A<13>

MEM_B_BA<0>

MEM_B_BA<1>

MEM_B_BA<2>

MEM_B_CKE<1>

MEM_B_RAS_L

MEM_B_WE_L

MEM_B_CAS_L

MEM_B_CS_L<1>

MEM_B_CS_L<0>

MEM_B_DQ<30>

MEM_B_DQ<29>

MEM_B_DQ<28>

MEM_B_DQ<27>

MEM_B_DQ<25>

MEM_B_DQ<31>

MEM_B_DQ<26>

MEM_B_DQS_N<3>

MEM_B_CLK_N<0>

MEM_B_CKE<0>

MEM_B_DQS_P<3>

MEM_B_CLK_P<0>

MEM_B_A<8>

MEM_B_A<9>

MEM_B_A<7>

MEM_B_ODT<1>

MEM_B_A<0>

MEM_B_A<1>

MEM_B_A<2>

MEM_B_A<10>

MEM_B_A<11>

MEM_B_A<12>

MEM_B_A<13>

MEM_B_BA<0>

MEM_B_BA<1>

MEM_B_BA<2>

MEM_B_CKE<1>

MEM_B_RAS_L

MEM_B_WE_L

MEM_B_CAS_L

MEM_B_CS_L<1>

MEM_B_CS_L<0>

MEM_B_DQ<16>

MEM_B_DQ<22>

MEM_B_DQ<21>

MEM_B_DQ<20>

MEM_B_DQ<19>

MEM_B_DQ<18>

MEM_B_DQS_N<2>

MEM_B_CLK_N<0>

MEM_B_CKE<0>

MEM_B_DQS_P<2>

MEM_B_CLK_P<0>

MEM_B_A<9>

MEM_B_A<1>

MEM_B_A<2>

MEM_B_A<3>

MEM_B_A<6>

MEM_B_A<10>

MEM_B_A<11>

MEM_B_A<12>

MEM_B_A<13>

MEM_B_BA<2>

MEM_B_CKE<1>

MEM_B_WE_L

MEM_B_CS_L<1>

MEM_B_CS_L<0>

MEM_B_DQ<14>

MEM_B_DQ<9>

MEM_B_DQ<8>

MEM_B_DQ<12>

MEM_B_DQ<10>

MEM_B_DQ<13>

MEM_B_DQ<11>

MEM_B_DQ<15>

MEM_B_DQS_N<1>

MEM_B_CLK_N<0>

MEM_B_CKE<0>

MEM_B_DQS_P<1>

MEM_B_CLK_P<0>

MEM_B_A<8>

MEM_B_A<9>

MEM_B_A<2>

MEM_B_A<4>

MEM_B_A<6>

MEM_B_A<13>

MEM_B_BA<1>

MEM_B_BA<2>

MEM_B_CKE<1>

MEM_B_RAS_L

MEM_B_WE_L

MEM_B_CAS_L

MEM_B_CS_L<1>

MEM_B_CS_L<0>

MEM_B_DQ<6>

MEM_B_DQ<7>

MEM_B_CLK_N<0>

MEM_B_CKE<0>

MEM_B_CLK_P<0>

MEM_B_A<9>

MEM_B_A<7>

MEM_B_RAS_L

MEM_B_ODT<1>

PP0V75_S3_MEM_VREFDQ_B=PP1V5_S3_MEM_B




=PP1V5_S3_MEM_B

MEM_RESET_L


MEM_B_DQ<24>


=PP1V5_S3_MEM_B

R3130 1 2R3120 1 2

C3100 1

2

R3110 1 2R3100 1 2

U3100

K3

L7

H7

M7

K7

N3

N7

J7

L3

K2

L8

L2

M8

M2

N8

M3

J2

K8

J3

G3

F7

G7

G9

F9

H2

H1

B7

B3

C7

C2

C8

C3

D3

A3

79

80

81

82

E3

E8

D2

E7

A7

G1

F1

F3

N2

A2

A9

D7

G2

G8

K1

K9

M1

M9

B9

C1

E2

E9

J8

E1

A1

A8

N1

N9

B1

D8

F2

F8

J1

J9

L1

L9

B2

B8

C9

D1

D9

H3

H8

H9

U3110

K3

L7

H7

M7

K7

N3

N7

J7

L3

K2

L8

L2

M8

M2

N8

M3

J2

K8

J3

G3

F7

G7

G9

F9

H2

H1

B7

B3

C7

C2

C8

C3

D3

A3

79

80

81

82

E3

E8

D2

E7

A7

G1

F1

F3

N2

A2

A9

D7

G2

G8

K1

K9

M1

M9

B9

C1

E2

E9

J8

E1

A1

A8

N1

N9

B1

D8

F2

F8

J1

J9

L1

L9

B2

B8

C9

D1

D9

H3

H8

H9

U3120

K3

L7

H7

M7

K7

N3

N7

J7

L3

K2

L8

L2

M8

M2

N8

M3

J2

K8

J3

G3

F7

G7

G9

F9

H2

H1

B7

B3

C7

C2

C8

C3

D3

A3

79

80

81

82

E3

E8

D2

E7

A7

G1

F1

F3

N2

A2

A9

D7

G2

G8

K1

K9

M1

M9

B9

C1

E2

E9

J8

E1

A1

A8

N1

N9

B1

D8

F2

F8

J1

J9

L1

L9

B2

B8

C9

D1

D9

H3

H8

H9

U3130

K3

L7

H7

M7

K7

N3

N7

J7

L3

K2

L8

L2

M8

M2

N8

M3

J2

K8

J3

G3

F7

G7

G9

F9

H2

H1

B7

B3

C7

C2

C8

C3

D3

A3

79

80

81

82

E3

E8

D2

E7

A7

G1

F1

F3

N2

A2

A9

D7

G2

G8

K1

K9

M1

M9

B9

C1

E2

E9

J8

E1

A1

A8

N1

N9

B1

D8

F2

F8

J1

J9

L1

L9

B2

B8

C9

D1

D9

H3

H8

H9

R31011 2

R31111 2

R31211 2

R31311 2

C3101 1

2

C3102 1

2

C3110 1

2

C3111 1

2

C3112 1

2

C3120 1

2

C3121 1

2

C3122 1

2

C3130 1

2

C3131 1

2

C3132 1

2

051-9276

2.7.0

31 OF 109

29 OF 72

29 30 31

29 30 31

11 66

7 29 30 32

11 29 30 32 66

11 66

11 66

11 66

29

29

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

26 27 28 29 30

29

29

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

26 27 28 29 30

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 66

11 66

26 27 28 29 30

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66 11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 66

11 66

11 29 30 32 66

11 66

11 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 66

11 66

11 66

11 66

11 66

11 66

11 66

11 66

11 29 30 32 66

11 29 30 32 66

11 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 66

11 66

11 66

11 66

11 66

11 66

11 66

11 29 30 32 66

11 29 30 32 66

11 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 66

11 66

11 66

11 66

11 66

11 66

11 66

11 66

11 66

11 29 30 32 66

11 29 30 32 66

11 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 66

11 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

29 30 31

7 29 30 32

29 30 31

29 30 31

29 30 31

7 29 30 32

26 27 28 29 30

29 30 31

11 66

29 30 31

7 29 30 32

NF_DQ6

NF_DQ7

NF_DQ5

NF_DQ4

A1

VREFDQ

VREFCA VDD VDDQ

ODT0

ODT1

RESET*

ZQ0

A0

A2

A3

A4

A6

A10/AP

A11

A12/BC*

A13

A14

BA0

BA1

BA2

CKE1

RAS*

WE*

CAS*

CS1*

CS0*

ZQ1

DQ0

DQ1

DQ2

DQ3

DQS*

DM/TDQS

NF_TDQS*

NC

VSS

CK*

CKE0

DQS

CK

VSSQ

A8

A9

A5

A7

A15

NF_DQ6

NF_DQ7

NF_DQ5

NF_DQ4

A1

VREFDQ

VREFCA VDD VDDQ

ODT0

ODT1

RESET*

ZQ0

A0

A2

A3

A4

A6

A10/AP

A11

A12/BC*

A13

A14

BA0

BA1

BA2

CKE1

RAS*

WE*

CAS*

CS1*

CS0*

ZQ1

DQ0

DQ1

DQ2

DQ3

DQS*

DM/TDQS

NF_TDQS*

NC

VSS

CK*

CKE0

DQS

CK

VSSQ

A8

A9

A5

A7

A15

NF_DQ6

NF_DQ7

NF_DQ5

NF_DQ4

A1

VREFDQ

VREFCA VDD VDDQ

ODT0

ODT1

RESET*

ZQ0

A0

A2

A3

A4

A6

A10/AP

A11

A12/BC*

A13

A14

BA0

BA1

BA2

CKE1

RAS*

WE*

CAS*

CS1*

CS0*

ZQ1

DQ0

DQ1

DQ2

DQ3

DQS*

DM/TDQS

NF_TDQS*

NC

VSS

CK*

CKE0

DQS

CK

VSSQ

A8

A9

A5

A7

A15

NF_DQ6

NF_DQ7

NF_DQ5

NF_DQ4

A1

VREFDQ

VREFCA VDD VDDQ

ODT0

ODT1

RESET*

ZQ0

A0

A2

A3

A4

A6

A10/AP

A11

A12/BC*

A13

A14

BA0

BA1

BA2

CKE1

RAS*

WE*

CAS*

CS1*

CS0*

ZQ1

DQ0

DQ1

DQ2

DQ3

DQS*

DM/TDQS

NF_TDQS*

NC

VSS

CK*

CKE0

DQS

CK

VSSQ

A8

A9

A5

A7

A15

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



NC

NCNC

NCNC

NC NC

NCNC

NC NC



NC

201

240

1% 1/20WMF201MF 1% 1/20W

240

0.47UF

201

4V

CERM-X5R-120%

201 1%

240

MF 1/20W



MT41K1G4

OMIT_TABLE



MT41K1G4


MT41K1G4



MT41K1G4


201

1/20WMF 1%

240

MF201 1%

240

1/20W

240

201 1% 1/20WMF

201 1/20W1%

240

MF

201 1/20W1%

240

MF

0.47UF

4V

CERM-X5R-120%

201

0.47UF

CERM-X5R-120%

201

4V

0.47UF

4V

20%

201

CERM-X5R-1

0.47UF

4V

CERM-X5R-120%

201

201

20%CERM-X5R-1

4V

0.47UF

20%CERM-X5R-1

4V

0.47UF

201

20%

4V

0.47UF

CERM-X5R-1201 201

0.47UF

4V

CERM-X5R-120%

0.47UF

4V

CERM-X5R-120%

201

0.47UF

4V

CERM-X5R-120%

201

0.47UF

4V

CERM-X5R-120%

201


DDR3 DRAM CHANNEL B (32-63)


=PP1V5_S3_MEM_BPP0V75_S3_MEM_VREFDQ_B


MEM_B_DQ<61>

MEM_B_DQ<57>

MEM_B_A<0>

MEM_B_A<7>

=PP1V5_S3_MEM_B




=PP1V5_S3_MEM_BPP0V75_S3_MEM_VREFDQ_B

MEM_B_ODT<1>

MEM_B_ODT<0>

=PP1V5_S3_MEM_B

MEM_B_ZQ9

MEM_B_ZQ14

MEM_B_ODT<0>

MEM_B_DQ<36>

MEM_B_DQ<34>

MEM_B_DQS_P<4>

MEM_B_A<0>MEM_B_ZQ15

MEM_B_ZQ11

MEM_B_ZQ14

MEM_B_ZQ10MEM_B_ZQ13

MEM_B_ZQ12

MEM_B_ZQ8

MEM_B_DQS_N<4> MEM_B_A<10>

MEM_B_A<11>

MEM_B_A<13>

MEM_B_A<14>

MEM_B_DQ<38>

MEM_B_ZQ13

MEM_B_ZQ15

MEM_B_ZQ12

MEM_B_A<4>

MEM_B_DQ<51>

MEM_B_WE_L

MEM_B_A<0>

MEM_B_CKE<1>

MEM_B_A<15>

MEM_B_A<14>

MEM_B_A<15>


MEM_B_A<15>

MEM_B_A<14>

MEM_B_A<2>

MEM_B_A<3> MEM_B_DQ<32>

MEM_B_DQ<37>

MEM_B_ODT<1> MEM_B_ODT<0>

MEM_B_ODT<1>

MEM_RESET_L

MEM_B_A<1>

MEM_B_A<2>

MEM_B_A<3>

MEM_B_A<4>

MEM_B_A<5>

MEM_B_A<6>

MEM_B_A<10>

MEM_B_A<11>

MEM_B_A<12>

MEM_B_A<13>

MEM_B_BA<0>

MEM_B_BA<1>

MEM_B_BA<2>

MEM_B_RAS_L

MEM_B_CAS_L

MEM_B_CS_L<1>

MEM_B_CS_L<0>

MEM_B_DQ<58>

MEM_B_DQ<56>

MEM_B_DQ<59>

MEM_B_DQ<60>

MEM_B_DQ<62>

MEM_B_DQ<63>

MEM_B_DQS_N<7>

MEM_B_CLK_N<0>

MEM_B_CKE<0>

MEM_B_DQS_P<7>

MEM_B_CLK_P<0>

MEM_B_A<8>

MEM_B_A<9>

MEM_B_A<7>

MEM_B_ODT<0>

MEM_B_ODT<1>

MEM_RESET_L

MEM_B_A<0>

MEM_B_A<6>

MEM_B_A<10>

MEM_B_A<11>

MEM_B_A<12>

MEM_B_A<13>

MEM_B_BA<0>

MEM_B_BA<1>

MEM_B_BA<2>

MEM_B_CKE<1>

MEM_B_RAS_L

MEM_B_WE_L

MEM_B_CAS_L

MEM_B_CS_L<1>

MEM_B_CS_L<0>

MEM_B_DQ<53>

MEM_B_DQ<55>

MEM_B_DQ<48>

MEM_B_DQ<50>

MEM_B_DQ<54>

MEM_B_DQ<52>

MEM_B_DQS_N<6>

MEM_B_CLK_N<0>

MEM_B_CKE<0>

MEM_B_DQS_P<6>

MEM_B_CLK_P<0>

MEM_B_A<8>

MEM_B_A<9>

MEM_RESET_L

MEM_B_A<1>

MEM_B_A<2>

MEM_B_A<3>

MEM_B_A<4>

MEM_B_A<5>

MEM_B_A<12>

MEM_B_BA<0>

MEM_B_BA<1>

MEM_B_BA<2>

MEM_B_CKE<1>

MEM_B_RAS_L

MEM_B_WE_L

MEM_B_CAS_L

MEM_B_CS_L<1>

MEM_B_CS_L<0>

MEM_B_DQ<43>

MEM_B_DQ<41>

MEM_B_DQ<42>

MEM_B_DQ<47>

MEM_B_DQ<44>

MEM_B_DQ<45>

MEM_B_DQ<46>

MEM_B_DQ<40>

MEM_B_DQS_N<5>

MEM_B_CLK_N<0>

MEM_B_CKE<0>

MEM_B_DQS_P<5>

MEM_B_CLK_P<0>

MEM_B_A<8>

MEM_B_A<9>

MEM_B_A<7>

MEM_B_A<1>

MEM_B_A<5>

MEM_B_A<6>

MEM_B_A<10>

MEM_B_A<11>

MEM_B_A<12>

MEM_B_A<13>

MEM_B_BA<0>

MEM_B_BA<1>

MEM_B_BA<2>

MEM_B_CKE<1>

MEM_B_RAS_L

MEM_B_WE_L

MEM_B_CAS_L

MEM_B_CS_L<1>

MEM_B_CS_L<0>

MEM_B_DQ<33>

MEM_B_DQ<35>

MEM_B_DQ<39>

MEM_B_CLK_N<0>

MEM_B_CKE<0>

MEM_B_CLK_P<0>

MEM_B_A<8>

MEM_B_A<9>

MEM_B_A<7>

MEM_RESET_L


MEM_B_A<4>

MEM_B_A<3>

MEM_B_A<2>

MEM_B_A<1>

MEM_B_DQ<49>


R3230 1 2R3220 1 2R3210 1 2

C3200 1

2

R3200 1 2

U3230

K3

L7

H7

M7

K7

N3

N7

J7

L3

K2

L8

L2

M8

M2

N8

M3

J2

K8

J3

G3

F7

G7

G9

F9

H2

H1

B7

B3

C7

C2

C8

C3

D3

A3

79

80

81

82

E3

E8

D2

E7

A7

G1

F1

F3

N2

A2

A9

D7

G2

G8

K1

K9

M1

M9

B9

C1

E2

E9

J8

E1

A1

A8

N1

N9

B1

D8

F2

F8

J1

J9

L1

L9

B2

B8

C9

D1

D9

H3

H8

H9

U3200

K3

L7

H7

M7

K7

N3

N7

J7

L3

K2

L8

L2

M8

M2

N8

M3

J2

K8

J3

G3

F7

G7

G9

F9

H2

H1

B7

B3

C7

C2

C8

C3

D3

A3

79

80

81

82

E3

E8

D2

E7

A7

G1

F1

F3

N2

A2

A9

D7

G2

G8

K1

K9

M1

M9

B9

C1

E2

E9

J8

E1

A1

A8

N1

N9

B1

D8

F2

F8

J1

J9

L1

L9

B2

B8

C9

D1

D9

H3

H8

H9

U3210

K3

L7

H7

M7

K7

N3

N7

J7

L3

K2

L8

L2

M8

M2

N8

M3

J2

K8

J3

G3

F7

G7

G9

F9

H2

H1

B7

B3

C7

C2

C8

C3

D3

A3

79

80

81

82

E3

E8

D2

E7

A7

G1

F1

F3

N2

A2

A9

D7

G2

G8

K1

K9

M1

M9

B9

C1

E2

E9

J8

E1

A1

A8

N1

N9

B1

D8

F2

F8

J1

J9

L1

L9

B2

B8

C9

D1

D9

H3

H8

H9

U3220

K3

L7

H7

M7

K7

N3

N7

J7

L3

K2

L8

L2

M8

M2

N8

M3

J2

K8

J3

G3

F7

G7

G9

F9

H2

H1

B7

B3

C7

C2

C8

C3

D3

A3

79

80

81

82

E3

E8

D2

E7

A7

G1

F1

F3

N2

A2

A9

D7

G2

G8

K1

K9

M1

M9

B9

C1

E2

E9

J8

E1

A1

A8

N1

N9

B1

D8

F2

F8

J1

J9

L1

L9

B2

B8

C9

D1

D9

H3

H8

H9

R32011 2

R32111 2

R32211 2

R32311 2

C3201 1

2

C3202 1

2

C3210 1

2

C3211 1

2

C3212 1

2

C3220 1

2

C3221 1

2

C3222 1

2

C3230 1

2

C3231 1

2

C3232 1

2

051-9276

2.7.0

32 OF 109

30 OF 72

29 30 31

7 29 30 32 29 30 31

29 30 31

11 66

11 66

11 29 30 32 66

11 29 30 32 66

7 29 30 32

29 30 31

29 30 31

29 30 31

7 29 30 32 29 30 31

11 29 30 32 66

11 29 30 32 66

7 29 30 32

30

11 29 30 32 66

11 66

11 66

11 66

11 29 30 32 66

11 66 11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 66

30

30

30

11 29 30 32 66

11 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66 11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66 11 66

11 66

11 29 30 32 66 11 29 30 32 66

11 29 30 32 66

26 27 28 29 30

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 66

11 66

11 66

11 66

11 66

11 66

11 66

11 29 30 32 66

11 29 30 32 66

11 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

26 27 28 29 30

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 66

11 66

11 66

11 66

11 66

11 66

11 66

11 29 30 32 66

11 29 30 32 66

11 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

26 27 28 29 30

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 66

11 66

11 66

11 66

11 66

11 66

11 66

11 66

11 66

11 29 30 32 66

11 29 30 32 66

11 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 66

11 66

11 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

26 27 28 29 30

11 29 30 32 66 11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 29 30 32 66

11 66

29 30 31

OUT

V-

V+

V-

V+

V-

V+

IN

NC

NC

DSG

DSG

V-

V+

NC

RESET*

A0

A1

A2

SCL

SDA

P0

P1

P2

P5

P6

P7

P3

P4

THRM

VCC

GNDPAD

NC

NC

IN

BI

VDD

VOUTD

VOUTC

VOUTB

VOUTASCL

SDA

A0

A1

GND

IN

BI



Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



Signal aliases required by this page:

VREFCA:LDO - LDO outputs sent to CA inputs.

Required zero ohm resistors when no VREF margining circuit stuffed

VREFDQ:M1_M3 - CPU margined DDR voltage divider sent to DQ inputs.

- =I2C_VREFDACS_SCL- =I2C_VREFDACS_SDA

10mA max load

Power aliases required by this page:

- =PP3V3_S3_VREFMRGN- =PPVTT_S3_DDR_BUF- =PPDDR_S3_MEMVREF

Addr=0x98(WR)/0x99(RD)

both at the same time!

8.59mV / step @ output

+61uA - -61uA (- = sourced)

1.5V (DAC: 0x3A)


1.267V (DAC: 0x8B)

MEM VREG

DDR3 (1.5V) 7.70mV per step

PCA9557D Pin:

BOM options provided by this page:

0.000V - 3.300V (0x00 - 0xFF)

Nominal value

DAC range:

VRef current:

DAC Channel:

MEM A VREF DQ

1

A B

2

MEM A VREF CA

C

3 4

C

5

D

0.000V - 3.000V (0x00 - 0x74)

1.056V - 1.442V (+/- 180mV)

+6.0mA - -5.0mA (- = sourced)


6

D

- =I2C_PCA9557D_SCL- =I2C_PCA9557D_SDA

DDRVREF_DAC - Stuffs Apple margining circuit.

VREFDQ:LDO_DAC - Margined LDO outputs sent to DQ inputs.

VREFDQ:LDO - LDO outputs sent to DQ inputs.

NOTE: CPU DAC output step sizes:

RST* on ’platform reset’ so that system

NOTE: Margining will be disabled across all

watchdog will disable margining.

Addr=0x30(WR)/0x31(RD)

(OD)Page Notes

NOTE: MEMVREG and FRAMEBUF share

a DAC output, cannot enable

MEM B VREF DQ

Margined target: 1.000V - 2.000V (+/- 500mV)

GPU Frame Buffer (1.8V, 70% VRef)

DDR3L (1.35V) 6.99mV per step

VREFCA:LDO_DAC - DAC margined LDO outputs sent to CA inputs.

DAC step size:

soft-resets and sleep/wake cycles.

VREFDQ:M1_DAC - DAC margined DDR voltage divider sent to DQ inputs.

MEM B VREF CA

0.75V (DAC: 0x3A)

0.300V - 1.200V (+/- 450mV)

0.000V - 1.501V (0x00 - 0x74)

+3.4mA - -3.4mA (- = sourced)

buffers at once or VRef source may be overloaded.

NOTE: Must not enable more than two SO-DIMM margining

55

10%

X5R6.3V

DDRVREF_DAC

0.1UF

201

DDRVREF_DAC

PLACE_NEAR=R7315.2:1mm

201MF

1/20W

33.2K

1%

DDRVREF_DAC

201

MF

1/20W

5%

100K

DDRVREF_DAC

MAX4253UCSP

DDRVREF_DAC

UCSPMAX4253

DDRVREF_DAC

MAX4253UCSP

1/20W

PLACE_NEAR=U2900.J8:2.54mm

1%

201MF

200

VREFCA:LDO_DAC

NONE

OMIT

NONE

402

NONE

SHORT

NONE

NONE

NONE

402

SHORT

OMIT

25

VREFDQ:LDO_DAC

PLACE_NEAR=U2900.E1:2.54mm

1%

MF201

1/20W

200


MF

1/20W

VREFDQ:LDO_DAC

1%

133

201

MF

1/20W

100K5%

201

DDRVREF_DAC

1K1%1/20W

201MF

VREFDQ:M1_M3

PLACE_NEAR=Q3320.6:1mm

VREFDQ:M1_M3


0.1UF

16V

0201X5R-CERM

10%


VREFDQ:M1_M3

1%1K

1/20WMF201

SOT563

SSM6N15AFE

VREFDQ:M1_M3

CRITICAL

SOT563

SSM6N15AFE

VREFDQ:M1_M3

CRITICAL

1/20W

1K


VREFDQ:M1_M3

201

1%

MF

0201

VREFDQ:M1_M3

0.1UF10%16VX5R-CERM


201

PLACE_NEAR=R3311.2:1mm1%1K

1/20WMF

VREFDQ:M1_M3


201MF1/20W5%0

VREFDQ:LDO_DAC

UCSP

DDRVREF_DAC

MAX4253

PLACE_NEAR=U3100.J8:2.54mm200

1/20WMF201

1%

VREFCA:LDO_DAC

133

1%1/20W

MF201


VREFCA:LDO_DAC

DDRVREF_DAC

201

5%

100K

1/20W

MF

NOSTUFFPLACE_NEAR=R3309:1mm

201MF1/20W5%0

DDRVREF_DAC

201

MF

1/20W

100K5%

133

VREFCA:LDO_DAC

MF1/20W

1%

201

PLACE_NEAR=R3309.2:1mmDDRVREF_DAC

PCA9557

CRITICAL

QFN

43

43

DDRVREF_DAC

MSOP

DAC5574

CRITICAL

43

43

DDRVREF_DAC

0201X5R-CERM16V10%0.1UF

DDRVREF_DAC

2.2UF

CERM402-LF

20%6.3V

10%

0201X5R-CERM

16V

0.1UF

DDRVREF_DAC

DDRVREF_DAC

0201X5R-CERM

16V10%

0.1UF

FSB/DDR3/FRAMEBUF Vref Margining


VREFDQ:M1_DAC4118S0012 RES,MF,1KOHM,1,1/20W,0201 R3321,R3322,R3311,R3312

117S0002 VREFDQ:LDOR3303,R3360RES,MF,1/20W,0.0 OHM,5,0201,SMD2

VREFDQ:M1_DACR33041118S0303 RES,MF,332OHM,1,1/20W,0201

117S0002 2 VREFCA:LDOR3309,R3305RES,MF,1/20W,0.0 OHM,5,0201,SMD

VREFMRGN_CA_SODIMMB_EN

VREFMRGN_CA_SODIMMA_EN

MIN_LINE_WIDTH=0.3 mm

PP3V3_S3_VREFMRGN_CTRL


VREFMRGN_MEMVREG_EN

PCA9557D_RESET_L

=PPVTT_S3_DDR_BUF



VOLTAGE=0.75V





VREFMRGN_DQ_SODIMMA_BUF

VREFMRGN_CA_SODIMMB_BUF

=PPDDR_S3_MEMVREF


PP3V3_S3_VREFMRGN_DAC

VOLTAGE=3.3V

DDRREG_FB




=I2C_VREFDACS_SDA

=I2C_VREFDACS_SCL

PPCPU_MEM_VREFDQ_A


PPCPU_MEM_VREFDQ_B PP0V75_S3_MEM_VREFDQ_B

VREFMRGN_SODIMMA_DQ

VREFMRGN_DQ_SODIMMA_EN



=PPDDR_S3_MEMVREF

VREFMRGN_MEMVREG_BUF

=I2C_PCA9557D_SDA

VREFMRGN_CA_SODIMMA_BUF

VREFMRGN_SODIMMS_CA

=PP3V3_S3_VREFMRGN

VREFMRGN_MEMVREG_FBVREF

=I2C_PCA9557D_SCL

U3301

3

4

5

8

6

7

9

10

11

12

13

14

15

1

2

17

16

C3303 1

2

C3302 1

2

R3301

12

R3310

1 2

U3300

9

10

3

6

7

8

1

2

4

5

C33011

2

C3300 1

2

C3305 1

2 R3314

1 2

R33131

2

U3302

C3

C2

C1

C4

B1

B4

U3302

A3

A2

A1

A4

B1

B4

U3304

C3

C2

C1

C4

B1

B4

R3309

1 2

R3318

1 2

R3319

1 2

R3303

1 2

R3304

1 2

R33071

2

R33211

2

C33201

2

R33221

2

Q3320

6

21

Q3320

3

54

R33111

2

C33101

2

R33121

2

R33601

2

U3304

A3

A2

A1

A4

B1

B4

R3305

1 2

R3306

1 2

R33151

2

R33611

2

051-9276

2.7.0

33 OF 109

31 OF 72

7 55

27 28 66

29 30

29 30 31

7 31

27 28 31 66

9

26 31

9 29 30 31

26 31

27 28 31 66

7 31

7

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



JEDEC recommends 30 Ohm term to VTT for CS,CKE,ODT and 36 Ohm for BA,A,RAS,CAS,WE

2 CAPS ALONG PACKAGE EDGE

MEM CLOCK TERMINATIONPlace RC end termination after last DRAMPlace Source Cterm at neckdown at first DRAM

COLUMN OF THREE CAPS BETWEEN PACKAGES







20%0.47UF

201CERM-X5R-14V

20%0.47UF

201CERM-X5R-14V

20%0.47UF

201CERM-X5R-14V

20%0.47UF

201CERM-X5R-14V

4VCERM-X5R-1201

0.47UF20%

365%1/32W 4X0201

361/32W5% 4X0201

CERM402-LF

20%2.2UF6.3V

364X02015%1/32W364X02011/32W5%

365%1/32W 4X0201

5%1/32W36

4X0201

1/32W5%36

4X0201

11 29 30 66

11 29 30 66

11 29 30 66

11 29 30 66

11 29 30 66

11 29 30 66

11 29 30 66

11 29 30 66

11 29 30 66

6.3V

2.2UF

CERM

20%

402-LF

11 29 30 66

11 29 30 66

11 29 30 66

11 29 30 66

11 29 30 66

11 29 30 66

11 29 30 66

11 29 30 66

11 29 30 66

11 29 30 66

11 29 30 66

11 29 30 66

11 29 30 66

4V

201

0.47UF

CERM-X5R-1

20%

0.47UF4VCERM-X5R-1201

20%

201

20%

CERM-X5R-14V

0.47UF

0.47UF20%

CERM-X5R-1201

4V

4VCERM-X5R-1

0.47UF20%

201

402-LF

2.2UF6.3V20%

CERM

402-LF

2.2UF6.3V20%

CERM

4VCERM-X5R-1201

0.47UF20%20%

0.47UF4VCERM-X5R-1201

201

20%0.47UF

CERM-X5R-14V

2.2UF6.3V20%

402-LFCERM

4VCERM-X5R-1201

0.47UF20%

11 27 28 66

11 27 28 66

11 27 28 66

11 27 28 66

11 27 28 66

11 27 28 66

20%2.2UF

402-LFCERM6.3V

11 27 28 66

11 27 28 66

11 27 28 66

11 27 28 66

11 27 28 66

11 27 28 66

11 27 28 66

11 27 28 66

2.2UF20%

CERM6.3V

402-LF

2.2UF20%

402-LFCERM6.3V

11 27 28 66

11 27 28 66

11 27 28 66

11 27 28 66

11 27 28 66

11 27 28 66

11 27 28 66

0.1UF

MEM_A_CLK_TERM_R

10%X5R

6.3V201

0.1UF

201

10%X5R

6.3V

30

5%1/20WMF201

CERM25V5%

3.3PF

201

1/20W5%

30

MF201

30

201

5%1/20WMF

201CERM25V5%

3.3PF

30

201

1/20WMF

5%

6.3V

2.2UF20%

402-LFCERM

6.3V

2.2UF20%

402-LFCERM

4X020136

1/32W5%

4X020136

1/32W5%

1/32W5%36

4X0201

5%1/32W 4X020136

5%1/32W 4X020136

5%1/32W36

4X0201

5%1/32W 4X020136

CERM402-LF

6.3V20%2.2UF

1/32W5% 4X020136

4X02011/32W5%36

4X02011/32W5%36

5%36

1/32W 4X0201

1/32W5% 4X02013636

5%1/32W 4X0201

1/32W36

5% 4X0201361/32W5% 4X0201

1/32W 4X02015%36

4X020136

5%1/32W

20%2.2UF6.3V

402-LFCERM

4X020136

1/32W5%

4X020136

5%1/32W

4X020136

5%1/32W

4X02015%36

1/32W

1/32W 4X02015%36

1/32W36

4X02015%

4X020136

5%1/32W

4X02015%36

1/32W

4X02011/32W36

5%

4X02015%36

1/32W

2.2UF6.3VCERM402-LF

20%

4X02011/32W36

5%

4X02011/32W5%3636

4X02011/32W5%

364X02015%1/32W

364X02015%1/32W

1/32W36

4X02015%

CERM6.3V

2.2UF20%

402-LF

5%36

1/32W 4X0201

2.2UF6.3V

402-LF

20%

CERM

CERM6.3V20%2.2UF

402-LF

6.3V20%2.2UF

402-LFCERM

CERM6.3V20%2.2UF

402-LF

6.3V

2.2UF20%

CERM402-LF

402-LF

20%6.3VCERM

2.2UF

6.3V20%

CERM402-LF

2.2UF

20%2.2UF6.3V

402-LFCERM

11 27 28 66

11 27 28 66

4X020136

1/32W5%11 27 28 66

11 29 30 66

4X02015%1/32W3611 29 30 66

4X02015%1/32W36

4X020136

1/32W5%

4X020136

1/32W5%

4X020136

1/32W5%

2.2UF

CERM6.3V20%

402-LF

11 27 28 66

11 27 28 66

11 27 28 66

11 27 28 66

201

4VCERM-X5R-1

0.47UF20%

4X020136

5%1/32W

5% 4X02011/32W36

1/32W 4X02015%36

5% 4X02011/32W36

11 29 30 66

6.3V

2.2UF20%

402-LFCERM

11 29 30 66

11 29 30 66

11 29 30 66

0.47UF

201

20%

CERM-X5R-14V

402-LFCERM

20%2.2UF6.3V

402-LF

6.3V

2.2UF20%

CERM

402-LF

2.2UF20%6.3VCERM

402-LFCERM6.3V

2.2UF20%

6.3V

2.2UF20%

402-LFCERM

20%6.3V

402-LFCERM

2.2UF

CERM402-LF

20%2.2UF6.3V

2.2UF

402-LF

6.3V20%

CERM

2.2UF20%6.3VCERM402-LF

20%2.2UF6.3VCERM402-LF

402-LFCERM6.3V20%2.2UF

20%

CERM402-LF

6.3V

2.2UF

6.3V20%

CERM

2.2UF

402-LF

20%6.3VCERM402-LF

2.2UF

CERM402-LF

20%6.3V

2.2UF

CERM

20%2.2UF6.3V

402-LF

2.2UF6.3VCERM402-LF

20%

6.3V

2.2UF20%

402-LFCERM

2.2UF20%

CERM402-LF

6.3V

CERM402-LF

20%2.2UF6.3V

CERM402-LF

20%2.2UF6.3V

CERM402-LF

20%2.2UF6.3V

CERM

20%2.2UF6.3V

402-LF

6.3V

2.2UF20%

402-LFCERM

CERM402-LF

20%2.2UF6.3V

2.2UF

CERM402-LF

20%6.3V

2.2UF6.3V20%

402-LFCERM

CERM6.3V20%

402-LF

2.2UF

6.3V

2.2UF20%

402-LFCERM

20%6.3V

2.2UF

CERM402-LF

CERM

20%6.3V

2.2UF

402-LF

6.3V

2.2UF

402-LF

20%

CERM

6.3V

2.2UF20%

402-LFCERM

CERM402-LF

20%2.2UF6.3V

2.2UF

CERM402-LF

20%6.3V

CERM402-LF

20%2.2UF6.3V

6.3V

2.2UF20%

CERM402-LF

2.2UF

402-LF

6.3V20%

CERM

6.3V20%

402-LFCERM

2.2UF

0.47UF

201

4V20%

CERM-X5R-1

CERM-X5R-1

20%0.47UF

201

4V36

5%1/32W 4X0201

4X020136

5%1/32W

402-LFCERM

2.2UF6.3V20%

364X02015%1/32W

364X02015%1/32W

4X02011/32W36

5%20%0.47UF

201CERM-X5R-14V

20%0.47UF

201CERM-X5R-14V

DDR3 DRAM Channel B (32-63)

SYNC_MASTER=K21_MLB SYNC_DATE=12/13/2010

=PP1V5_S3_MEM_B

=PP1V5_S3_MEM_A

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_A_CLK_N<0>

MEM_A_CLK_P<0>

VOLTAGE=0V

VOLTAGE=0V

MEM_B_CLK_TERM_R

=PP1V5_S3_MEM_B

MEM_A_WE_LMEM_A_CKE<0>

MEM_A_A<7>

MEM_A_CS_L<0>

MEM_A_BA<0>

MEM_A_ODT<0>

MEM_A_A<12>

MEM_A_A<2>

MEM_A_A<14>

MEM_A_A<11>

MEM_A_A<10>

MEM_A_A<8>

MEM_A_A<5>

MEM_A_RAS_L

MEM_A_CAS_L

MEM_A_A<1>

MEM_A_A<3>

MEM_A_BA<1>

MEM_A_A<13>

MEM_A_A<9>

MEM_A_A<0>

MEM_A_A<4>

MEM_A_A<6>

MEM_A_BA<2>

MEM_A_CKE<1>

MEM_A_ODT<1>

MEM_A_CS_L<1>

MEM_A_A<15>

=PP0V75_S0_MEM_VTT_B

=PP0V75_S0_MEM_VTT_A

MEM_B_A<8>

MEM_B_CKE<0>

MEM_B_A<7>

MEM_B_BA<0>

MEM_B_A<13>

MEM_B_BA<1>

MEM_B_ODT<0>

MEM_B_A<5>MEM_B_WE_L

MEM_B_A<11>

MEM_B_A<9>

MEM_B_A<2>

MEM_B_A<15>

MEM_B_CKE<1>

MEM_B_A<6>

MEM_B_A<1>

MEM_B_RAS_L

=PP1V5_S3_MEM_A

MEM_B_BA<2>

MEM_B_A<0>

MEM_B_A<12>

MEM_B_CS_L<0>

MEM_B_A<10>

MEM_B_CS_L<1>

MEM_B_ODT<1>

MEM_B_CAS_L

MEM_B_A<3>

MEM_B_A<4>

MEM_B_A<14>

C34201

2

C34211

2

C34101

2

C34111

2

C34121

2

C34001

2

C34011

2

C34241

2

C34251

2

C34141

2

C34151

2

C34161

2

C34041

2

C34051

2

C34501

2

C34511

2

C34401

2

C34411

2

C34421

2

C34301

2

C34311

2

C34541

2

C34551

2

C34441

2

C34451

2

C34461

2

C34341

2

C34351

2

C34221

2

C34231

2

C34701

2

C34711

2

C34721

2

C3402

C34031

2

C34261

2

C34271

2

C34741

2

C34751

2

C34761

2

C34061

2

C34071

2

C34521

2

C34531

2

C34901

2

C34911

2

C34921

2

C34321

2

C34331

2

C34561

2

C34571

2

C34941

2

C34951

2

C34961

2

C34361

2

C34371

2

C34811

2

C34601

2

RP3410 3 6

RP3409 3 6

RP3411 2 7

RP3408 4 5

RP3411 3 6 C34621

2

C34641

2

C34671

2

C34611

2

C34631

2

C34651

2

C34661

2

RP3408 3 6

RP3410 4 5

RP3408 1 8

RP3410 2 7

RP3414 2 7

RP3413 2 7

RP3414 1 8

C34831

2

C34851

2

C34801

2

C34821

2

C34841

2

C34871

2

C34861

2

C34881

2

C34891

2

C3469

1 2

C3479

1 2

R34681 2

C3468 1

2 R34691 2

R34781 2

C3478 1

2 R34791 2

RP3401 4 5

RP3402 2 7

RP3406 2 7

RP3403 1 8

RP3402 1 8

RP3401 2 7

RP3403 2 7

RP3407 3 6

RP3406 1 8

RP3406 4 5

RP3402 3 6

RP3404 3 6

RP3403 4 5

RP3404 1 8

RP3407 2 7

RP3402 4 5

RP3403 3 6

RP3407 1 8

RP3404 2 7

RP3404 4 5

RP3401 3 6

RP3401 1 8

RP3406 3 6

RP3413 1 8

RP3410 1 8

RP3409 1 8

RP3413 3 6

RP3413 4 5

RP3409

4 5

RP3408 2 7

RP3409 2 7

RP3414 4 5

RP3411 1 8

RP3414 3 6

C34081

2

C34091

2

C34181

2

C34191

2

C34281

2

C34291

2

C34381

2

C34391

2

RP3407 4 5

RP3411 4 5

RP3405 1 8

RP3405 2 7

RP3405 3 6

RP3405 4 5

C34931

2

RP3412 1 8

RP3412 2 7

RP3412 3 6

RP3412 4 5

C34771

2

051-9276

2.7.0

34 OF 109

32 OF 72

7 29 30 32

7 27 28 32

11 29 30 66

11 29 30 66

11 27 28 66

11 27 28 66

7 29 30 32

7

7

7 27 28 32

OUT

OUT

BI

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI

BI

IN

IN

IN

IN

OUT

PETN_3

PETN_2

PETP_2

PETP_1

PETN_1

PETP_0

PETN_0

MONOBS_N

MONDC0

MONDC1

PERN_3

PERP_3

PERN_2

PERP_2

PERN_1

PERP_1

PERP_0

PERN_0

MONOBS_P

TMU_CLK_IN

TMU_CLK_OUT

DPSRC_3_P

DPSRC_2_P

DPSRC_3_N

DPSRC_1_P

DPSRC_2_N

DPSRC_1_N

DPSRC_0_P

DPSRC_AUX_P

DPSRC_0_N

DPSRC_HPD_OD

DPSRC_AUX_N

GPIO_2/GO2SX

GPIO_15

GPIO_9/OK2GO2SX_OD*

GPIO_14

GPIO_8/EN_CIO_PWR_OD*

GPIO_7/CIO_SCL_OD

GPIO_6/CIO_SDA_OD

GPIO_5/CIO_PLUG_EVENT

GPIO_4/WAKE_N_OD

GPIO_3

PB_CIO3_TX_N/DP_SRC_2_N

PB_CONFIG2/CIO_2_LSOE

PB_CIO2_RX_N

PB_CONFIG1/CIO_2_LSEO

PB_CIO2_RX_P

PB_CIO2_TX_P/DP_SRC_0_P

PB_CIO2_TX_N/DP_SRC_0_N

PB_CIO3_TX_P/DP_SRC_2_P

PB_DPSRC_3_N

PB_DPSRC_1_N

PB_DPSRC_1_P

PB_LSRX/CIO_3_LSOE

PB_CIO3_RX_N

PB_LSTX/CIO_3_LSEO

PB_CIO3_RX_P

PB_DPSRC_3_P

GPIO_11/PB_CIO_SEL/BYP1

GPIO_13/PB_DP_PWRDN/BYP2

GPIO_1/PB_HV_EN/BYP0

PB_DPSRC_HPD

PB_AUX_N

PB_AUX_P

THERMDA

EE_DI

EE_DO

EE_CS_N

TDI

EE_CLK

TDO

DPSNK0_2_P

DPSNK0_3_N

DPSNK0_1_P

DPSNK0_2_N

DPSNK0_0_P

DPSNK0_1_N

DPSNK0_AUX_P

DPSNK0_0_N

DPSNK0_HPD

DPSNK0_AUX_N

DPSNK1_3_N

DPSNK1_3_P

DPSNK1_2_N

DPSNK1_2_P

DPSNK1_1_N

DPSNK1_1_P

DPSNK1_0_N

DPSNK1_0_P

DPSNK1_AUX_N

DPSNK1_AUX_P

DPSNK1_HPD

PA_CIO0_TX_N/DP_SRC_0_N

PA_CIO0_TX_P/DP_SRC_0_P

PA_CIO0_RX_N

PA_CIO0_RX_P

PA_CONFIG2/CIO_0_LSOE

PA_CONFIG1/CIO_0_LSEO

PA_CIO1_TX_N/DP_SRC_2_N

PA_CIO1_TX_P/DP_SRC_2_P

PA_CIO1_RX_N

PA_CIO1_RX_P

PA_LSRX/CIO_1_LSOE

PA_LSTX/CIO_1_LSEO

PA_DPSRC_1_N

PA_DPSRC_1_P

PA_DPSRC_3_N

PA_DPSRC_3_P

PA_AUX_P

PA_DPSRC_HPD

PA_AUX_N

GPIO_10/PA_CIO_SEL/BYP1

GPIO_0/PA_HV_EN/BYP0

GPIO_12/PA_DP_PWRDN/BYP2

PETP_3

RSENSE

REFCLK_100_IN_P

REFCLK_100_IN_N

XTAL_25_IN

XTAL_25_OUT

TMS

TCK

TEST_EN

TEST_PWR_GOOD

DPSNK0_3_P

PWR_ON_POC_RSTN

PERST_N

NC

RBIAS

PCIE_RST_0_N

PCIE_RST_1_N

PCIE_RST_3_N

PCIE_RST_2_N

PCIE_CLKREQ_OD_N

EN_LC_PWR

PCIE RESET

PCIE GEN2

MISC

(SYM 1 OF 2)

CLOCKS

JTAG/TEST PORT

RECEIVE

TRANSMIT

EEPROM

SINK PORT 0

SINK PORT 1

SOURCE PORT 0

PORT3

PORT2

PORT0

PORT1

DISPLAYPORT

PORTS

OUT

NC

IN

IN

IN

OUT

OUT

OUT

IN

BI

BI

OUT

OUT

OUT

OUT

IN

OUT

IN

IN

OUT

OUT

IN

OUT

IN

IN

OUT

OUT

OUT

OUT

OUT

IN

BI

BI

OUT

OUT

OUT

OUT

IN

OUT

IN

IN

OUT

OUT

IN

OUT

IN

IN

OUT

OUT

D

C

Q

S*

W*

HOLD*

PADVSS THM

VCC

IN

OUT

IN

OUT

BI

IN

OUT

OUT

OUT

OUT

IN

OUT

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



(TBT_EN_CIO_PWR_L)

R3681 for CYA,

allows separation

of GPIO_2/GPIO_9

Stuff one of R3861/2.

if necessary.

(FORCE_PWR)

5 - PCIE_RST_1_N

6 - PCIE_RST_2_N

7 - PCIE_RST_3_N

4 - GPIO_5

2 - GPIO_2

3 - GPIO_3

0 - GPIO_13

1 - GPIO_1

NOTE: The following pins require testpoints:

15 - PB_LSRX

14 - PB_LSTX

13 - GPIO_10

12 - GPIO_12

11 - GPIO_0

10 - GPIO_14

9 - GPIO_11

8 - GPIO_15

DEBUG: For monitoring clock

Use AA8 GND ball for THERM_DN

DEBUG: For monitoring current/voltage

(TBT_SPI_CS_L)

Not used in host mode.

SNK0 AC Coupling

SNK1 AC Coupling

(TBT_SPI_MISO)

DEBUG: For monitoring clock

DEBUG: For monitoring current/voltage

(TBT_SPI_CLK)

(TBT_SPI_MOSI)

For unused port, pull CONFIG1, CONFIG2, LSRX, HPD and CIO_SEL low (10k). All other port signals can be NC.

1/20WMF

3.3K5%

201

8

8

1/20WMF

05%

201

1/20W5%

MF

100K

201

100K

1/20W5%

MF201

1/20WMF

05%

201

3.3K

1/20WMF

5%

201

X5R-CERM02010.1UF16V10%

8 68

8 68

8 68

8 68

8 68

8 68

8 68

8 68

8 68

8 68

X5R-CERM02010.1UF16V10%

X5R-CERM02010.1UF16V10%

X5R-CERM02010.1UF16V10%

X5R-CERM02010.1UF16V10%

0201X5R-CERM0.1UF16V10%

X5R-CERM02010.1UF16V10%

X5R-CERM02010.1UF16V10%

1/20WMF

1%1K

201

X5R-CERM02010.1UF16V10%

X5R-CERM02010.1UF16V10%

X5R-CERM02010.1UF16V10%

X5R-CERM02010.1UF16V10%

X5R-CERM02010.1UF16V10%

X5R-CERM02010.1UF16V10%

X5R-CERM02010.1UF16V10%

0201X5R-CERM0.1UF16V10%

X5R-CERM02010.1UF16V10%

X5R-CERM02010.1UF16V10%

X5R-CERM02010.1UF16V10%

X5R-CERM02010.1UF16V10%

8 68

8 68

8 68

8 68

8 68

8 68

8 68

8 68

8 68

8 68

35

19

19

19

19

CRITICAL

OMIT_TABLE

FCBGACACTUSRIDGE4C

35

25 68

1/20WMF

5%10K

201

1/20WMF

1%

806

201

1K5%1/20WMF201

NO STUFF

10K

MF1/20W

5%

201

16 68

16 68

33 63

63

33 35 63

63

63 69

63 69

63 69

63 69

63 69

63 69

63

63

63 69

63 69

63 69

63 69

63

63

63 69

63 69

63 69

63 69

33

8

33

8

8 69

8 69

8 69

8 69

8 69

8 69

8

8

8 69

8 69

8 69

8 69

8

8

8 69

8 69

8 69

8 69

0201

1UF20%

6.3V

X5R CRITICAL

MLPM95256-RMC6XG

OMIT_TABLE

OMIT

NONENONE

NOSTUFFNONE

402

35

X5R-CERM0201

NO STUFF

0.1UF

16V10%

5%1/20W

47K

MF201

35

MF-LF1/16W

5%100K

402

19 25

41

43

43

18

33

100K

1/20W5%

MF201

MF

5%1/20W

10K

201

10K

1/20W5%

MF201

MF

5%1/20W

10K

201

MF

5%10K

1/20W

201

33

19

19 33

MF

5%1/20W

10K

NO STUFF

201

10K

1/20W5%

MF201

10K

1/20W5%

MF201

MF1/20W5%0

201

35

0201X5R-CERM0.1UF

16V10%

X5R-CERM02010.1UF

16V10%

0201X5R-CERM0.1UF

16V10%

0201X5R-CERM0.1UF

16V10%

1/20WMF

3.3K5%

201

0201X5R-CERM0.1UF

16V10%

0201X5R-CERM0.1UF

16V10%

X5R-CERM02010.1UF

16V10%

X5R-CERM02010.1UF

16V10%

0201X5R-CERM0.1UF

16V10%

X5R-CERM02010.1UF

16V10%

X5R-CERM02010.1UF

16V10%

1/20WMF

5%3.3K

201

0201X5R-CERM0.1UF

16V10%

0201X5R-CERM0.1UF

16V10%

X5R-CERM02010.1UF

16V10%

0201X5R-CERM0.1UF

16V10%

0201X5R-CERM0.1UF

16V10%

8 68

8 68

8 68

8 68

8 68

8 68

8 68

8 68

8 68

8 68

8 68

8 68

8 68

8 68

8 68

8 68


Thunderbolt Host (1 of 2)

DP_TBTSNK0_ML_N<3>

TP_DP_TBTSRC_AUXCH_CP

TP_DP_TBTSRC_AUXCH_CN

DP_TBTSRC_HPD

=TBT_WAKE_L

TBT_CIO_PLUG_EVENT

=I2C_TBTRTR_SDA

=I2C_TBTRTR_SCL

TBT_PWR_EN

TBT_GO2SX_BIDIR

=PP3V3_TBTLC_RTR

TBT_B_R2D_C_P<1>TBT_B_R2D_C_N<1>

TBT_B_D2R_P<1>TBT_B_D2R_N<1>

TBT_B_LSRXTBT_B_LSTX

DP_TBTPB_ML_C_P<1>

=PP3V3_S4_TBT

DP_TBTPA_HPD

TBT_B_CONFIG1_BUF

DP_TBTPB_ML_C_P<3>

TP_DP_TBTSRC_ML_CP<0>

TP_DP_TBTSRC_ML_CN<1>

TBT_EN_LC_PWR

TBTROM_HOLD_L

TBTROM_WP_L

=PP3V3_TBTLC_RTR

PCIE_TBT_R2D_C_P<3>

=PP3V3_S4_TBT

DP_TBTSNK0_ML_P<0>

DP_TBTSNK0_ML_N<0>

DP_TBTSNK1_ML_P<2>

TBT_SPI_CS_L

TBT_SPI_CLK

DP_TBTSNK0_ML_N<2>

=PP3V3_TBTLC_RTR

PCIE_TBT_R2D_C_P<1>

PCIE_TBT_R2D_C_N<0>

PCIE_TBT_R2D_C_P<0>

DP_TBTSNK0_ML_C_P<3>

PCIE_TBT_D2R_P<2>

PCIE_TBT_D2R_P<1>

PCIE_TBT_D2R_N<0>

PCIE_TBT_D2R_P<0>

PCIE_TBT_D2R_N<1>

PCIE_TBT_D2R_N<3>

PCIE_TBT_R2D_C_N<1>




DP_TBTSNK0_ML_C_N<0>




DP_TBTSNK0_AUXCH_C_P

DP_TBTSNK0_AUXCH_C_N


DP_TBTSNK1_AUXCH_C_P



DP_TBTSNK1_AUXCH_N

DP_TBTSNK0_ML_P<1>

DP_TBTSNK1_ML_P<3>



DP_TBTSNK0_ML_C_N<2> DP_TBTSNK0_ML_N<2>

DP_TBTSNK0_ML_N<1>

DP_TBTSNK1_ML_N<0>

DP_TBTSNK1_ML_P<2>

DP_TBTSNK1_ML_N<3>

DP_TBTSNK1_AUXCH_P

DP_TBTSNK1_ML_N<2>

DP_TBTSNK1_ML_N<1>

DP_TBTSNK1_ML_P<1>

PCIE_TBT_D2R_P<3>

DP_TBTSNK1_ML_P<0>

PCIE_TBT_R2D_C_P<2>

DP_TBTSNK0_AUXCH_P

DP_TBTSNK0_ML_N<3>

DP_TBTSNK0_ML_P<3>

PCIE_TBT_D2R_N<2>

SYSCLK_CLK25M_TBT


TP_TBT_PCIE_RESET2_L



TBT_RBIAS

TBT_PCIE_RESET_L

DP_TBTSNK0_ML_P<3>

JTAG_TBT_TCK

JTAG_TBT_TMS

TBT_RSENSE

PCIE_TBT_D2R_C_P<3>

TBT_A_DP_PWRDN

TBT_A_HV_ENTBT_A_CIO_SEL

DP_TBTPA_AUXCH_C_NDP_TBTPA_AUXCH_C_P

DP_TBTPA_ML_C_P<3>DP_TBTPA_ML_C_N<3>

DP_TBTPA_ML_C_P<1>DP_TBTPA_ML_C_N<1>

TBT_A_LSTXTBT_A_LSRX

TBT_A_D2R_N<1>

TBT_A_R2D_C_P<1>TBT_A_R2D_C_N<1>

TBT_A_CONFIG2_RC

TBT_A_D2R_P<0>

TBT_A_R2D_C_P<0>

DP_TBTSNK1_HPD

DP_TBTSNK1_ML_P<0>

DP_TBTSNK1_ML_N<0>

DP_TBTSNK1_ML_P<1>

DP_TBTSNK1_ML_N<1>

DP_TBTSNK1_ML_N<2>

DP_TBTSNK1_ML_P<3>

DP_TBTSNK1_ML_N<3>

DP_TBTSNK0_AUXCH_N

DP_TBTSNK0_HPD

DP_TBTSNK0_ML_N<0>

DP_TBTSNK0_AUXCH_P

DP_TBTSNK0_ML_N<1>

DP_TBTSNK0_ML_P<0>

DP_TBTSNK0_ML_P<1>

DP_TBTSNK0_ML_P<2>

JTAG_TBT_TDO

JTAG_TBT_TDI

TBT_SPI_MISO

TP_TBT_THERM_DP

DP_TBTPB_AUXCH_C_PDP_TBTPB_AUXCH_C_N

DP_TBTPB_HPD

TBT_B_HV_EN

TBT_B_DP_PWRDNTBT_B_CIO_SEL

TBT_B_R2D_C_P<0>

PCIE_TBT_R2D_N<0>

PCIE_TBT_R2D_P<0>

PCIE_TBT_R2D_P<1>

PCIE_TBT_R2D_N<1>

PCIE_TBT_R2D_P<2>

PCIE_TBT_R2D_N<2>

PCIE_TBT_R2D_P<3>

PCIE_TBT_R2D_N<3>

TP_TBT_MONDC1

TP_TBT_MONDC0

PCIE_TBT_D2R_C_N<0>

PCIE_TBT_D2R_C_P<0>

PCIE_TBT_D2R_C_N<1>

PCIE_TBT_D2R_C_P<1>

PCIE_TBT_D2R_C_P<2>

PCIE_TBT_D2R_C_N<2>

PCIE_TBT_D2R_C_N<3>

TBT_MONOBSN

TBT_MONOBSP

DP_TBTSNK1_AUXCH_N

TBT_B_CONFIG2_RC

DP_TBTSNK1_AUXCH_P

TBT_A_D2R_P<1>

TBT_B_R2D_C_N<0>

DP_TBTPB_ML_C_N<1>

DP_TBTPB_ML_C_N<3>

DP_TBTSNK0_AUXCH_N

DP_TBTSNK0_ML_P<2>


DP_TBTSNK1_AUXCH_C_N

TBT_A_CONFIG1_BUF

TBT_A_D2R_N<0>

TBT_A_R2D_C_N<0>

TBT_B_D2R_P<0>TBT_B_D2R_N<0>

TBT_TEST_EN

TBT_TEST_PWR_GOOD


=TBT_CLKREQ_L

PCIE_TBT_R2D_C_N<2>

PCIE_TBT_R2D_C_N<3>

TBT_A_HV_EN

TBT_B_HV_EN

TBT_GPIO_14

TBT_GPIO_9

TBT_GO2SX_BIDIR

TBT_DDC_XBAR_EN_L

TBT_SPI_MOSI


PCIE_CLK100M_TBT_P

PCIE_CLK100M_TBT_N


TBT_B_DP_PWRDN

TBT_A_DP_PWRDN

TBT_PWR_REQ_L

TBT_DDC_XBAR_EN_L

TBT_GPIO_14

TBT_GPIO_9

TBT_EN_CIO_PWR_LMAKE_BASE=TRUE

TP_TBT_XTAL25OUT

SYSCLK_CLK25M_TBT_R

TBT_TMU_CLK_OUT

TBT_TMU_CLK_IN

TBT_PWR_ON_POC_RST_L





R36901

2

R36921

2

R36911

2

R36551

2

C3601 1 2

C3600 1 2

C3602 1 2

C3603 1 2

C3604 1 2

C3605 1 2

C3606 1 2

C3607 1 2

C3640 1 2

C3641 1 2

C3642 1 2

C3643 1 2

C3645 1 2

C3644 1 2

C3646 1 2

C3647 1 2

R36251

2

R3630 1

2

R3631 1

2

R36291

2

R36931

2

C3629 1 2

C3628 1 2

C3627 1 2

C3626 1 2

C3625 1 2

C3624 1 2

C3623 1 2

C3622 1 2

C3621 1 2

C3620 1 2

C3630 1 2

C3631 1 2

C3632 1 2

C3633 1 2

C3634 1 2

C3635 1 2

C3636 1 2

C3637 1 2

C3638 1 2

C3639 1 2

U3600

D19

E20

D17

E18

D15

E16

D13

E14

B5

A6

U6

D11

E12

D9

E10

D7

E8

D5

E6

B3

A4

T5

B9

A8

B11

A10

B13

A12

B15

A14

D3

C2

V3

W4

AD3

R4

P5

K5

G2

M3 L2

H3 L4

T3

V5

M1

Y1

W2

J4

AA2

AB1

AC2

P3

M5

AD23

AC24

W16

W18

F1

F3

E22

G22

E24

G24

J22

L22

J24

L24

K1

G4

B17

A16

B19

A18

H1

J6

N2

E2

D1

N22

R22

N24

R24

U22

W22

U24

W24

P1

H5

B21

A20

B23

A22

K3

G6

L6

W6

N6

T1

Y5

U2

AA10

AB13

AA16

AB19

AB9

AA12

AB15

AA18

R6

AD7

AD11

AD15

AD19

AD5

AD9

AD13

AD17

J2W20

AD21

AB21

U20

AA6

V1

R2

N4

AB5

Y7

AB3

Y3

AA4

AA24

AB23

R36981

2 R36951 2

R36961

2

R36991

2

C36901

2

U36906

5

7

2

1

9

8

4

3

R36151

2

C3610 1

2

R36101

2

R3632 1

2

R36971

2

R36851

2

R36881

2

R36871

2

R36861

2

R36821

2

R36831

2

R36801

2

R36811

2

051-9276

2.7.0

36 OF 109

33 OF 72

U4

33 68

7 33 34 35

7 33 34 35

7 33 34 35

7 33 34 35

33 68

33 68

33 68

69

69

33 68

7 33 34 35

33 68

33 68

33 68

33 68

33 68

33 68

33 68

33 68

33 68

33 68

33 68

33 68

33 68

33 68

33 68

33 68

33 68

68

33 68

33 68

33 68

33 68

33 68

33 68

33 68

33 68

33 68

33 68

33 68

33 68

33 68

33 68

69

46

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

33 68

33 68

33 68

33 68

33 35 63

33

33

33

19 33

33

69

33

33 63

33

68

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VCC1P0_DPAUX

VCC1P0_DPAUX

VCC3P3_POC

VSSPE

VCC1P0_PE

VCC1P0_PE

VCC1P0_PE

VCC1P0_PE

VCC1P0_PE

VCC1P0_PE

VCC1P0_PE

VCC1P0_PE

VCC1P0_PE

VCC1P0_PE

VCC1P0_PE

VCC1P0_PE

VCC1P0_PE

VCC1P0_PE

VCC1P0

VCC1P0

VCC3P3_DP

VCC3P3_DP

VCC3P3_DP

VCC3P3_CIO

VCC3P3_CIO

VCC3P3_CIO

VCC3P3

VCC3P3

VCC1P0

VCC1P0

VCC1P0

VCC1P0

VCC1P0

VCC1P0

VCC1P0

VCC1P0

VCC1P0

VCC1P0

VCC1P0

VCC1P0

VCC1P0

VCC1P0

VCC1P0_ON

VCC1P0_ON

VCC1P0_ON

VCC1P0_ON

VCC1P0_ON

VCC1P0_ON

VCC1P0_ON

VCC1P0_ON

VCC1P0_ON

VCC1P0_ON

VCC3P3

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VCC3P3_DP

VCC3P3_DPAUX

(SYM 2 OF 2)

VCC

GND

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EDP: 10 mA

???? mA (Single Port)

250 mA (Dual Port)

EDP: 1000 mA

???? mA (Single-Port)2700 mA (Dual-Port)EDP: 3000 mA

??? mA (Single-Port)250 mA (Dual-Port)

EDP: 240 mA

20%

X5R6.3V

1.0UF

0201-MUR

6.3VCERM-X5R0402-1

10UF20%

20%

X5R6.3V

1.0UF

0201-MUR

20%

X5R6.3V

1.0UF

0201-MUR

6.3V20%1.0UF

X5R0201-MUR

1.0UF20%

X5R0201-MUR

6.3VCERM-X5R

20%6.3V

0402-1

10UF

20%10UF

0402-1CERM-X5R

6.3V

X5R6.3V20%1.0UF

0201-MUR

CRITICAL

OMIT_TABLE

CACTUSRIDGE4CFCBGA

6.3VCERM-X5R0402-1

10UF20%20%

X5R6.3V

1.0UF

0201-MUR

20%

X5R6.3V

1.0UF

0201-MUR

0201-MURX5R

20%6.3V

1.0UF

20%

X5R

1.0UF

0201-MUR

6.3V

X5R6.3V

0201-MUR

20%1.0UF

X5R6.3V

1.0UF20%

0201-MUR

1.0UF

0201-MUR

6.3VX5R

20%

6.3VX5R0201-MUR

1.0UF20%

X5R0201-MUR

1.0UF20%6.3V

20%6.3V

1.0UF

0201-MURX5R

20%

X5R6.3V

1.0UF

0201-MUR

20%

X5R6.3V

1.0UF

0201-MUR

20%

X5R6.3V

1.0UF

0201-MUR

20%

X5R6.3V

1.0UF

0201-MUR

Thunderbolt Host (2 of 2)


=PP3V3_TBTLC_RTR

=PP1V05_TBTCIO_RTR

=PP1V05_TBTLC_RTR

=PP3V3_S4_TBT

C37141

2

C37101

2

C37121

2

C37181

2

C37131

2

C3700 1

2

C3701 1

2

U3600K11

K15

R10

R14

T11

U10

V11

W10

L10

L14

M11

M15

N10

N14

P11

P15

G8

H9

J10

J12

J14

J16

J8

K17

T15

U14

V7

W8

G10

G12

V15

V19

W12

W14

G14

G16

G18

H19

K19

M19

P19

T19

M7

P7

T7

L18

N18

R18

H11

H13

H15

H17

H7

K7

AD1

K13

N16

N8

P13

P17

P9

R12

R16

R8

T13

T17

K9

T9

U12

U16

U8

V9

L12

L16

L8

M13

M17

M9

N12

A2

A24

AC12

AC14

AC16

AC18

AC20

AC22

AC4

AC6

AC8

B1

AA14

B7

C10

C12

C14

C16

C18

C20

C22

C24

C4

AA20

C6

C8

D21

D23

E4

F11

F13

F15

F17

F19

AA22

F21

F23

F5

F7

F9

G20

H21

H23

J18

J20

AA8

K21

K23

L20

M21

M23

N20

P21

P23

R20

T21

AB11

T23

U18

V13

V17

V21

V23

Y11

Y13

Y15

Y17

AB17

Y19

Y21

Y23

Y9

AB7

AC10

C37601

2

C3772 1

2

C3771 1

2

C3770 1

2

C3790 1

2

C37291

2

C37321

2

C37301

2

C3744 1

2

C3743 1

2

C3742 1

2

C3741 1

2

C3740 1

2

C3745 1

2

C37051

2

C3773 1

2

C3774 1

2

051-9276

2.7.0

37 OF 109

34 OF 72

7 33 35

7

7

7 33 35

IN

D

G S

D

S G

D

S G

IN

S

G

D

NC

VIN

FBX

EN/UVLO

INTVCC

VC

RT

SS

SYNC

SW

SGND GND

NC

SNS1

SNS2

OUT

IN

RESET*

OUT

EN

MR*

GNDTHRM

IN

VDD

SENSE+-

PAD

(OD)

0.7V

DLY

IN

OUT

IN

GND

VOUT

ON

VIN

GND

VOUT

ON

VIN

D SG

OUTSENSE

THRM

RESET*

CT

GND

MR*

VDD

PAD

VOUT

GNDON

VIN

D

SG

IN

IN

D

GS

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UVLO(rising) = UVLO(falling) + (2uA * R1)

UVLO(falling) = 1.22 * (R1 + R2) / R2

Power aliases required by this page:

- =PP3V3_TBT_P3V3TBTFET (3.3V FET Input)

- =PP1V05_TBT_FET (1.05V FET Output)

TBTBST:Y - Stuffs 18V boost circuitry.

SGND shorted to

1.05V TBT "LC" Switch

Part

1.05V TBT "CIO" Switch

GND inside package,

TPS3808G25

(IPU)

Max Current = 4A (85C)

@ 1.05V

R(on)

Type Load Switch

11.5 mOhm Max

8 mOhm Typ

U3820TPS22920

@ 1.0V

R(on)

Part

TBT 15V Boost RegulatorSI8409DB:

Vds(max): -30V

Max Vgs: 10V

for 2S.

<R1>

- =PP3V3_S0_TBTPWRCTL8-13V Input

Changes required

no XW necessary.

- =PPVIN_SW_TBTBST (8-13V Boost Input)

BOM options provided by this page:

- =TBT_CLKREQ_L

Type


RC guarantees minimum 5ms to reach 0.5V

C3816 must be 10%

- =PP1V05_TBT_P1V05TBTFET (1.05V FET Input)

Page Notes

- =PP18V_TBT_REG (18V Boost Output)

- =TBT_RESET_L

- =PP3V3_TBT_FET (3.3V FET Output)

Signal aliases required by this page:

Vt = 2.33V +/- 2%

Delay = 27.3ms

Intel investigating whether RC is sufficient.

C3825 value may need tuning

Pull-up: R3610

Vgs(max): +/-12V

Supervisor & CLKREQ# Isolation

TBT "POC" Power-up Reset

Id(max): 3.7A @ 70C

Vgs(th): -1.4V

add property on another page.Voltage not specified here,

Rds(on): 46mOhm @ 4.5V Vgs

<R2>

UVLO = 4.55V (falling), 4.95 (rising)

DLY = 60 ms +/- 20%

Vout = 15.1V

Max Current = 1.0A

Freq = 300KHz

<Rb>

<Ra>

Vout = 1.6V * (1 + Ra / Rb)

28.6 mOhm Max

20.3 mOhm Typ

Load Switch

TPS22924C

U3815

Pull-up provided by SB page.

Platform (PCIe) Reset

U3810

25.8 mOhm Max

Load Switch

18.5 mOhm Typ

TPS22924CPart

Type

R(on)

@ 2.5V


3.3V TBT "LC" Switch

X5R-CERM

6.3V

10%

1.0UF

02010201

1.0UF10%

6.3V

X5R-CERM

201MF

1/20W5%

0

100K

201

5%1/20W

MF

1/20W

SMC_DELAYED_PWRGD

=PP15V_TBT_REG


TBTBST_VSNS

MIN_LINE_WIDTH=0.5 mmGND_TBTBST_SGND

VOLTAGE=0VMIN_NECK_WIDTH=0.25 mm


TBTBST_FBX

TBTBST_EN_UVLO


PPVIN_SW_TBTBSTMIN_LINE_WIDTH=0.5 mm

PP1V05_TBTLC


TBTBST_INTVCCMIN_LINE_WIDTH=0.2 mm


TBTBST_VC

TBTBST_VC_RC

TBTBST_PWREN_DIV_L

TBT_A_HV_EN

TBTBST_PWREN_L

TBTBST_RT

TBTBST_SS

TBTBST_SNS1MIN_LINE_WIDTH=0.2 mmMIN_NECK_WIDTH=0.2 mm

TBT_PWR_ON_POC_RST_L

TBTPOCRST_MR_L

TBT_SW_RESET_L

=PP3V3_S0_PCH_GPIO

TBTPOCRST_CT

TBT_CLKREQ_L

=PP3V3_S0_TBTPWRCTL

TBT_PCIE_RESET_L

=TBT_CLKREQ_L

TBT_CLKREQ_ISOL_LMAKE_BASE=TRUE

=PP3V3_TBTLC_RTR

TBT_EN_LC_PWR

TBTBST_SHDN_DIV

TBTBST_BOOSTMIN_LINE_WIDTH=0.5 mm

DIDT=TRUESWITCH_NODE=TRUEMIN_NECK_WIDTH=0.25 mm

=PPVIN_SW_TBTBST

=PP1V05_TBTLC_FET

=PP3V3_S4_TBT

=PP1V05_TBTCIO_FET

TBT_EN_CIO_PWR

=PP3V3_TBTLC_RTR

TBT_EN_CIO_PWR_L




TBTBST_VSNS_RC

TBTBST_SNS2


TBT Power Support


0603

10UF

X5R-CERM

20%25V

0603X5R-CERM

20%10UF

25V

0603X5R-CERM

20%10UF

25VX5R-CERM0603

25V

10UF20%

25VX5R-CERM

20%10UF

0603

25V

10UF20%

X5R-CERM0603

20%10UF

X5R-CERM0603

25V

402X5R-CERM

2.2UF20%10V

402

10VX5R-CERM

2.2UF20%

10%16VX7R

330PF

201

201MF

1/20W5%

10K

SSM3K15AMFVAPEVESM

1%

201MF

1/20W

36.5K

1/16W1%

MF-LF402

49.9K

19

33

SOT563SSM6N37FEAPE

0.0047UF10%25V

402CERM

6.3V

X5R-CERM

10%

1.0UF

0201

CRITICAL

TPS22920CSP

10%0.1UF

X5R-CERM0201

16V

CRITICAL

QFNTPS3808

33

SOT563

SSM6N37FEAPE100K

MF201

5%1/20W

6.3V

X5R-CERM

10%

1.0UF

0201

10%

6.3V

X5R-CERM

1.0UF

0201

TPS22924CSP

CRITICAL

33

16

25

10%

0201X5R-CERM

16V

0.1UF

SLG4AP016V

CRITICAL

TDFN

100K5%

201

1/20WMF

33

33

CRITICAL

PIMB062D-SM

6.8UH-4.0A

133K1/16W

402

1%

MF-LF

201

1/20WMF

1%10K

150K1/20W

201

5%

MF

3300PF

10V

201X7R

10%

X7R

10%50V

402

0.001UF

DFLS230L

CRITICAL

POWERDI-1235%0

MF1/20W

201

PLACE_NEAR=C3895.1:2 mm

SM

LT3957

CRITICAL

QFN

CERM402

50V5%22PF

0603

20%

X5R-CERM

10UF

25V

10UF

0603

20%25V

X5R-CERM

1/20W

200K1%

MF201

CRITICAL

SI8409DBBGA

402X5R-CERM

2.2UF20%10V

5%

201

47PF

25VNP0-C0G

25VX5R-CERM0603

10UF20%

1%1/16WMF-LF

402

15.8K

CERM

100PF

402

50V5%

NO STUFF

41 40 25

201

330K

MF1/20W5%

6.3V

0.33UF

CERM-X5R

10%

402

41.2K

1/20W

201

1%

MF

SSM6N37FEAPESOT563

SOT563SSM6N37FEAPE

201MF

5%330K

1/20WMF201

1%73.2K

SOD-VESM-HF

SSM3K15FV

25V10%

402X5R

0.1UF1/20W

201

5%

MF

470K

63 33

=TBT_RESET_L

TBT_EN_LC_ISOL

TBT_EN_LC_RC1V05

CSPTPS22924

CRITICAL

=PP3V3_TBTLC_FET

NO STUFF

TBT_EN_LC_RC3V3

R38801

2

C38801

2

Q38053

12

R38921

2

R38871

2

Q38883

54

Q38886

21

R38941

2

C38941

2

R38881

2

C38891

2

R38961

2

C38951

2

C38871

2

C3892 1

2

Q3880

23

1

4

R38911

2

C3890 1

2

C3891 1

2

C38881

2

U389025

31

12

13

14

15

16

17

28

1

2

10

35

36

33

6

3

4 23

24

37

32

8 9

20

21

38

34

30

27

XW3895

12

R38891

2

D3895A

K

C38991

2

C38931

2

R38811

2

R38931

2

R38951

2

L3895

1 2

R38071

2

U3800

6

5

7

3

8

4

2

9

1C3800 1

2

U3810

C1

C2

A2

B2

A1

B1

C3810 1

2

U3815

C1

C2

A2

B2

A1

B1

C3815 1

2

C3816 1

2

R38301

2

Q3825

3

54

U3830

3

5

4

62

7

1

C3830 1

2

U3820

D1

D2

A2

B2

C2

A1

B1

C1

C3820 1

2

C38311

2

R38201

2

Q3825 6

21

R38901 2

R38161

2

Q3840

3

12

R38401

2

C3825 1

2

C3882 1

2

C3881 1

2

C3896 1

2

C3897 1

2

C38981

2

C38841

2

C38851

2

C389B 1

2

C389A 1

2

R381112

C38111

2

051-9276

2.7.0

38 OF 109

35 OF 72

7

7 6

7 6

25 19 18 17 16 7

7

35 34 33 7

7

7

34 33 7

7

35 34 33 7

35 7

35 7

7 7

OUT

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

RESET*

OUT

EN

MR*

GNDTHRM

IN

VDD

SENSE +-

PAD

(OD)

0.7V

DLYOUT

IN

IN

OUT

BI

BI

VCC

GND

SEL OE*

D+

D-

Y+

Y-

M+

M-

OUT

D

G S

IN

G

SD

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6 3



3V S3 WLAN FET

DMP2018LFK

LOADING 0.750 A (EDP)

14-20 mOHM @2.5V

AIRPORT

RDS(ON)

MOSFET

P-TYPECHANNEL

514S0335

DLY = 60 MS +/- 20%

L USB_BT_WAKE

H USB_BT

SEL OUTPUT

BLUETOOTH

6 17

61

PLACEMENT_NOTE=Place close to J4001.

201 X5R10% 6.3V

0.1UF

16 68

16 68

0.1UF

PLACEMENT_NOTE=Place close to J4001.

6.3V10% 201X5R

6 16 68

6 16 68

PLACEMENT_NOTE=Place close to Q4050.

0.1UF

X5R6.3V10%

201

6 16 68

6 16 68

CRITICAL

0.0201%

0.25W

805MF-LF

45 71

45 71

SLG4AP016VTDFN

CRITICAL201

6.3V10%

X5R

0.1UF

16

25

18 23 61

5%

201MF

100K1/20W

100K

MF201

1%1/20W

201

1/20W1%

MF

232K


6.3V10%

201

0.1UF

X5R

CRITICAL

F-RT-SM1

SSD-K99

6 40 41

10UF

X5R603

20%10V

PLACEMENT_NOTE=Place close to Q4050.

0.1UF

0201X5R-CERM

16V10%

5%

0

201MF

1/20W

MF

1%

201

1/20W

15K

NOSTUFF

1/20W

15K

201MF

1%

NOSTUFFBTPWR:S4

MF1/20W

15K1%

201

24 67

24 67

201

10%6.3V

0.1UF

X5R

CRITICAL

PI3USB102ZLE

TQFN

41 BTPWR:S4


NOSTUFF

CERM16V10%

0.01UF

402

BTPWR:S4

0

MF201

1/20W5%

17 26 40 48 61

BTPWR:S3

201MF

1/20W5%015K

1/20W1%

MF201

NOSTUFF

1/20W

15K

201MF

1%

NOSTUFFNOSTUFF

201

1%15K

1/20WMF

BTPWR:S4

MF-LF

5%

0

1/16W

402

BTPWR:S3

402MF-LF1/16W

0

5%

CRITICAL

DMP2018LFKDFN2563-6

0.033UF

402

16V10%

X5R

100K

1/20W5%

201MF

5%1/20W

201MF

10K


X21 WIRELESS CONNECTOR

USB_BT_CONN_NUSB_BT_CONN_P

PP3V3_S3RS4_BT_FMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.5 mmVOLTAGE=3.3V

=PP3V3_S3_BT

AP_CLKREQ_Q_L

PCIE_AP_R2D_C_P

PCIE_AP_D2R_P

PP3V3_S3RS4_BT_F

USB_BT_WAKE_N

WIFI_EVENT_L

PCIE_AP_R2D_N

AP_RESET_CONN_L

PP3V3_WLAN_F

BTMUX_SEL

USB_BT_N

=PP3V3_S3_WLAN

PCIE_WAKE_L

PCIE_AP_D2R_N

USB_BT_WAKE_P

ISNS_AIRPORT_N

=PP3V3_S4_BT

PM_SLP_S4_L

=BT_WAKE_L

USB_BT_P

AP_CLKREQ_LAP_CLKREQ_L_RP3V3WLAN_VMON

AP_RESET_L

PCIE_CLK100M_AP_N

PCIE_AP_R2D_C_N

AP_PWR_EN

PCIE_AP_R2D_P

PCIE_CLK100M_AP_P

PM_WLAN_EN_L

ISNS_AIRPORT_P

MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=1 mm

VOLTAGE=3.3V PP3V3_WLAN_F


PP3V3_WLAN_R

MIN_LINE_WIDTH=1 mm

P3V3WLAN_SS

=PP3V3_S3_WLAN

C4021 1

2

C4051 1

2R40501 2

R40511

2

C4030

1 2

C40311 2

R4052

1 2

3 4

U4002

6

5

7

3

8

4

2

9

1

C4053 1

2

R40531

2

R40551

2

R40541

2

C40321

2

J4001

19

20

21

1

10

11

12

13

14

15

16

17

18

2

3

4

5

6

7

8

9

C40201

2 C40501 2

R409012

R40141

2

R40131

2

R40121

2

C40101

2

U4010

6

7

3

4

5

810

9

2

1

Q40103

12

C4011 1

2

R40111 2

R40181

2

R40171

2

R40161

2

R40151

2

R40011 2

R40021 2

Q4050

4

3

1

2

051-9276

2.7.0

40 OF 109

36 OF 72

6 67

6 67

6 36

7

6

6 36

67

6 68

6

6 36 41

7 36

67

7

6 68

6 36 41 7 36

OUT

OUT

OUT

OUT

IN

IN

A1_P

A1_N

SEL

XSD

B0_P

B1_P

B0_N

B1_N

C0_P

C1_P

C0_N

C1_N

VDD

VDD

VDD

VSS

VSS

VSS

THRM

A0_P

A0_N

PAD

OUT

OUT

IN

IN

IN

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

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Per PCIe Spec, only TX side should have AC cap

514S0393

353S3361

PCIE/SATA GUMSTICK2 CONNECTOR

PLACE_NEAR=J4501.1:3mm

0603

CRITICAL

FERR-70-OHM-4A

45 71

45 71

10V10%

0201X5R-CERM

0.1UF10%10VX5R-CERM

0.1UF

0201

8 65

8 65

8 65

8 65

X5R-CERM0201

10%

PLACE_NEAR=U4510.1:2 mm

10V

0.1UF

0201

10%

X5R-CERM16V

0.01UF


CRITICAL

CBTL02043ABQVQFN

16 67

16 67

16 67

16 67

6 40 41

6 40

1/20W

201MF

5%10K

0.1UF

X5R-CERM 020116V10%

6 8 65

6 8 65

8 65

8 65

020110% 16VX5R-CERM

0.1UF

201

470K1/20WMF

5%

0.1UF

X5R-CERM10% 020116V

10%X5R-CERM16V

0.1UF

0201

0.1UF

16V 0201X5R-CERM

10%

0.1UF

10%X5R-CERM16V 0201

X5R-CERM020116V

0.01UF

10%

X5R-CERM020116V

0.01UF

10%

X5R-CERM020110% 16V

0.01UF

X5R-CERM020110% 16V

0.01UF

10%10V

0.1UF


0201X5R-CERM

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

SSD-J5F-RT-SM

GND_VOID=TRUE

GND_VOID=TRUE

CRITICAL

6 25

6 16

6 16 65

6 16 65

60 61

5%

0

1/20WMF201

CERM-X5R1206-1

20%100UF

6.3V

0612

CRITICAL

0.0021%1WMF

NOSTUFF

6.3V20%

1206-1

100UF

CERM-X5R

SYNC_MASTER=J13_MLB

SSD CONNECTOR


PP3V3_S0_SSD_FLT

MIN_NECK_WIDTH=0.150mmMIN_LINE_WIDTH=0.6mm

VOLTAGE=3.3V

PP3V3_S0_SSD_R

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.6mmMIN_NECK_WIDTH=0.150mm

PCIE_SSD_R2D_MUX_IN_P

SATA_SSD_R2D_N

ISNS_SSD_N

ISNS_SSD_P

=PP3V3_S0_SSD

SATA_SSD_R2D_P

PCIE_SSD_D2R_MUX_OUT_N

SATA_SSD_D2R_MUX_OUT_P

PCIE_SSD_R2D_C_P<1>

=PP3V3_S0_SATAMUX

SMC_OOB1_TX_L

SMC_OOB1_RX_L

SSD_RESET_L

PCIE_SSD_R2D_N<1> PCIE_SSD_R2D_C_N<1>

SSD_P3V3S0_EN =P3V3S0_EN

SATA_SSD_R2D_MUX_IN_P

SATAMUX_EN_L

SATA_HDD_D2R_P

SATA_HDD_D2R_N

SATA_HDD_R2D_C_NSATA_SSD_R2D_MUX_IN_N

PCIE_SSD_D2R_N<0>

PCIE_SSD_D2R_P<0>

SATA_SSD_D2R_MUX_OUT_N

PCIE_SSD_R2D_C_P<0>

PCIE_SSD_R2D_C_N<0>

PCIE_SSD_D2R_MUX_OUT_P

SATA_HDD_R2D_C_P

PCIE_SSD_R2D_MUX_IN_N

SATA_SSD_D2R_N

PCIE_SSD_R2D_P<1>

PCIE_CLK100M_SSD_P

PCIE_CLK100M_SSD_N

SATA_PCIE_SEL

SATA_SSD_D2R_P

SSD_CLKREQ_L

PCIE_SSD_D2R_N<1>

PCIE_SSD_D2R_P<1>

L4500

1 2

C45021

2

C45011

2

C45141

2

C45191

2

U4510

4

3

8

7

18

19

16

17

14

15

12

13

9

21

1 610

5

11

20

2

R45101

2

C4521 1 2

C4520 1 2

R45051

2

C4518 1 2

C4517 1 2

C4513 1 2

C4512 1 2

C4516 1 2

C4515 1 2

C4511 1 2

C4510 1 2

C45051

2

J4501

27

28

29

30

31

32

33

34

35

1

10

11

12

13

14

15

16

17

18

19

2

20

21

22

23

24

25

26

3

4

5

6

7

8

9

R45201 2

C45031

2

R4599

12

34

C45041

2

051-9276

2.7.0

45 OF 109

37 OF 72

6

65

6 67

7

6 67

65

67

7

6 65

6

67

67

67

65

65

6 67

6 65

6

6 67

SYM_VER-1

OUT

OUT

IN

IN

L2

L1

L2

L1

NC

NC

GND

VBUS

IO

IO

NC

NC

GND

SSRX-

SXRX+

GND

D+

GND

SSTX+

SSTX-

D-

VBUS

BI

BI

IN

OUT

IN

OUT

GNDTHRM

OUT2

OUT1

ILIM

IN_0

IN_1

EN2

FAULT1*

FAULT2*

EN1

PAD

VCC

GND

SELOE*

D+

D-

Y+

Y-

M+

M-

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Mojo SMC Debug Mux

SEL=0 Choose SMC

SEL=1 Choose USB

Right USB Port A

USB Port Power Switch

Current limit per port (R4600): 2.18A min / 2.63A max

APN: 514-0819

16V

0.01UF

X5R-CERM0201

10% CRITICAL

90-OHMDLP0NS

18 67

18 67

18 67

18 67

0.1UF

X5R10% 6.3V

201

GND_VOID=TRUE

0.1UF

10% 6.3V201

GND_VOID=TRUEX5R

80OHM-25%-100MA

GND_VOID=TRUE

CRITICAL

0504

GND_VOID=TRUE

CRITICAL

050480OHM-25%-100MA

CRITICALSLP1210N6

RCLAMP0582N

0

MF201

5%1/20W

CRITICAL

F-RT-THUSB3.0-J11-J13

TSSLP-2-1ESD0P2RF-02LS

CRITICAL

CRITICAL


CRITICAL


CRITICAL


20%6.3V

CERM-X5R0402-2

10UF0.1UF10%

X5R-CERM16V

0201

18 67

18 67

0.1UF

10V10%

X5R-CERM0201

MOJO:YES

MOJO:YES

201

10K5%1/20WMF

40 41 67

40 41 67

40

23

20%6.3V

CERM-X5R0402-2

10UF

TPS2561DR

CRITICAL

SON

MOJO:YES

TQFN

SIGNAL_MODEL=MOJO_MUX

CRITICAL

PI3USB102ZLE

23.2K1%

MF-LF402

1/16W

POLY-TANTCASE-B2-SM1

20%6.3V

220UF-35MOHM

CRITICAL

CRITICAL

0603

FERR-120-OHM-3A

External A USB3 Connector


USB2_EXTA_MUXED_P

USB2_EXTA_MUXED_N

USB2_EXTA_MUXED_F_N

USB2_EXTA_MUXED_F_P

MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.15 mmVOLTAGE=5V

PP5V_S3_RTUSB_A_ILIM

USB3_EXTA_RX_N

USB3_EXTA_TX_F_N

USB3_EXTA_TX_F_P

USB3_EXTA_RX_F_P

USB3_EXTA_RX_F_N

USB3_EXTA_RX_P

VOLTAGE=5VMIN_NECK_WIDTH=0.375 mmMIN_LINE_WIDTH=0.5 mmPP5V_S3_RTUSB_A_F

USB_EXTA_P

USB_EXTA_N

USB_ILIM

USB3_EXTA_TX_C_N

USB3_EXTA_TX_C_P

=USB_PWR_EN

=PP5V_S3_RTUSB

USB_EN2

SMC_DEBUGPRT_RX_L

SMC_DEBUGPRT_TX_L

USB3_EXTA_TX_P

USB3_EXTA_TX_N

SMC_DEBUGPRT_EN_L

=PP3V42_G3H_SMCUSBMUX

USB_EXTA_OC_L

C4695 1

2

C46911

2

C4650 1

2

R46501

2

C4690 1

2

U4600

4

5

10

6

1

7

2

3

9

8

11

U4650

6

7

3

4

5

8 10

9

2

1

R46001

2

C46961

2

L4605

1 2

C4605 1

2 L4600

1 2

34

C4620

1 2

C4621

1 2

L4610

1 2

34

L4620

1 2

34

D4600

1

452 3

6

R46011

2

J4600

5

6

4

7

10

11

12

13

14

15

16

17

18

9

3

2

8

1

D4610

1

2

D4620

1

2

D4611

1

2

D4621

1

2

051-9276

2.7.0

46 OF 109

38 OF 72

67

67

67

67 67

67

67

67

67

67

6 39 61

7

7

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ON MLB SIDE AS LIO CAN’T FIT CAPS

LIO CONNECTOR998-4617 (HIROSE 3.0mm RCPT)

TSSLP-2-1

CRITICAL

ESD0P2RF-02LS

ESD0P2RF-02LS

CRITICAL

TSSLP-2-1

ESD0P2RF-02LS

CRITICAL

TSSLP-2-1

16VX5R-CERM

0201

10%


0.1UF

0.1UF10%16V

X5R-CERM0201


0.1UF10%16V

0201X5R-CERM PLACE_NEAR=J4700.5:1.5mm

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

CRITICAL

F-ST-SMDF40CG3.0-48DS-0.4V

GND_VOID=TRUE

X5R-CERM

0.1UF16V10% 0201

GND_VOID=TRUE

X5R-CERM10%16V 0201

0.1UF

GND_VOID=TRUE

2015%MF

0

1/20W

X5R-CERM0201

0.1UF

GND_VOID=TRUE

10%16V

NOSTUFF

2015%

GND_VOID=TRUE

0

1/20WMF

NOSTUFF

10% X5R-CERM

16V

GND_VOID=TRUE

0.1UF0201CRITICAL


SYNC_MASTER=N/A SYNC_DATE=N/A

LIO CONNECTORS

SMC_BC_ACOK

USB_EXTB_NSPKRAMP_INR_N

=PP3V42_G3H_ONEWIRE

SPKRAMP_INR_P

=USB_PWR_EN

USB_CAMERA_N

USB_EXTB_OC_L

SYS_ONEWIRE

=I2C_MIKEY_SCL

=I2C_LIO_SDA


HDA_RST_L

HDA_BIT_CLK

HDA_SDOUT

USB3_EXTB_RX_N

USB3_EXTB_RX_P

USB3_EXTB_TX_P

USB3_EXTB_TX_N

HDA_SYNC

USB_CAMERA_P

=PP3V3R1V5_S0_AUDIO

=I2C_MIKEY_SDA

=I2C_LIO_SCL

=PP3V3_S0_AUDIO

AUD_GPIO_3

AUD_I2C_INT_L

USB3_EXTB_TX_C_N

USB3_EXTB_RX_RC_P

USB_EXTB_P

AUD_IPHS_SWITCH_ENHDA_SDIN0

USB3_EXTB_RX_RC_N

USB3_EXTB_TX_C_P

C4720 1

2

C4710 1

2

C4700 1

2 J4700

1

10

11 12

13 14

15 16

19

2

20

21 22

23 24

25 26

27 28

29

3

30

31 32

35 36

37 38

39

4

40

41 42

43 44

45 46

47 48

49

5

50

51 52

6

7 8

9

C4721

1 2

C4722

1 2

R47101 2

C4731

1 2

R47201 2

C47321 2

D4711

1

2 D4710

1

2

D4720

1

2 D4721

1

2

051-9276

2.7.0

47 OF 109

39 OF 72

6 40 41

6 24 67

6 50 71

6 7

6 50 71

6 38 61

6 18 67

6 23

6 40

6 43

6 43

6 18

6 16 68

6 16 68

6 16 68

18 67

18 67

18 67

18 67

6 16 68

6 18 67

6 7

6 43

6 43

6 7

6 50

6 18

6 67

6 24 67

6 25

6 16 68

6 67

LPC0AD3

LPC0CLK

LPC0FRAME*

LPC0AD1

LPC0AD2

AIN08

AIN07

LPC0CLKRUN*

LPC0PD*

AIN13

AIN14

PM7/FAN0TACH0

PM6/FAN0PWM0

AIN04

C1-

I2C2SDA

AIN05

AIN09

AIN11

AIN21

AIN23

PK7/FAN0TACH1

AIN15

AIN06

AIN10

AIN20

AIN22

T1CCP1/PJ1

PK5

LPC0AD0

AIN12

PECI0RX

PECI0TX

PK6/FAN0PWM1

LPC0RESET*

PQ0/IRQ124

PP6/IRQ122

PN3/FAN0TACH2

I2C0SDA

AIN01

AIN00

PQ1/IRQ125

I2C0SCL

U1TX/PB1

USB0DP

USB0DM

AIN03

AIN02

T0CCP1/PB7

T0CCP0/PB6

PQ2/IRQ126

U1RX/B0

LPC0SCI*

AIN17

AIN16

PN2/FAN0PWM2

WT4CCP1/PH7

AIN18

AIN19

WT4CCP0/PH6

WT3CCP1/PH5

WT5CCP1/PM3

LPC0SERIRQ

PH3/FAN0TACH5

WT3CCP0/PH4

PH2/FAN0PWM5

PP3/IRQ119

PP4/IRQ120

C0-

WT2CCP0/PH0

WT2CCP1/PH1

PQ5/IRQ129

PP7/IRQ123

WT0CCP0/PG4

I2C3SDA

SSI1FSS/PF3

PC5/C1+

U0RX

SSI0RX/PA4

PP5/IRQ121

PQ7/IRQ131

WT0CCP1/PG5

I2C3SCL

SSI1CLK/PF2

PN4/FAN0PWM3

PP1/IRQ117

U0TX

SSI0CLK/PA2

SSI0FSS/PA3

I2C1SCL

PP2/IRQ118

PQ6/IRQ130

I2C4SDA

SSI1RX/PF0

PN7/FAN0TACH4

PP0/IRQ116

SSI0TX/PA5

I2C1SDA

I2C5SDA

PQ3/IRQ127

PQ4/IRQ128

I2C4SCL

I2C2SCL

SSI1TX/PF1

PN6/FAN0PWM4

PN5/FAN0TACH3

I2C5SCL

T3CCP0/PJ4/C2+

T3CCP1/PJ5/C2-

PF4

PF5

T1CCP0/PJ0

T2CCP0/PJ2

T2CCP1/PJ3

C0+

(1 OF 2)

VDDC

VREFA-

SWO/TDO

TDI

RST*

HIB*

WAKE*

XOSC0

VREFA+

VDDA

GNDA

PK4/RTCCLK

GND

NC

OSC0

XOSC1

SWCLK/TCK

SWDIO/TMS

OSC1

VBAT

VDD

(2 OF 2)

IN

IN

BI

BI

BI

BI

IN

IN

IN

BI

OUT

IN

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

IN

OUT

IN

IN

OUT

OUT

OUT

IN

NC

OUT

NC

BI

OUT

IN

OUT

OUT

IN

OUT

OUT

IN

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

BI

IN

OUT

IN

OUT

IN

NC

OUT

IN

IN

OUT

OUT

IN

IN

IN

IN

OUT

BI

IN

OUT

BI

BI

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(OD)

NC FOR ENG PKG

NC FOR ENG PKG

NC FOR STACK BRD

NC FOR STACK BRD

NC FOR STACK BRD

NC FOR STACK BRD

NC FOR ENG PKG

1.2V FOR ENG PKG

(OD)

NC FOR ENG PKG

NC FOR ENG PKG

NC FOR ENG PKG

NC FOR STACK BRD

NC FOR STACK BRD

NC FOR STACK BRD

NC FOR STACK BRD

NC FOR STACK BRD

NC FOR STACK BRD

NC FOR STACK BRD

(OD)

(OD)

(OD)

(OD)

(OD)

(OD)

(OD)

(OD)

(OD)

(OD)

(OD)

(OD)

(OD)

NOTE:

NOTE:

(OD)

SMS Interrupt can be active high or low, rename net accordingly.

those designated as inputs require pull-ups.pins designed as outputs can be left floating,Unused pins have "SMC_Pxx" names. Unused

If SMS interrupt is not used, pull up to SMC rail.

NC FOR STACK BRD

NC FOR STACK BRD

NC FOR STACK BRD

NC FOR STACK BRD

BGA

LM4FSXAH5BB

OMIT_TABLE

BGA

LM4FSXAH5BB

OMIT_TABLE

PLACE_NEAR=U4900.A1:4MM

SM

6 41 42 52

41 68

1M

MF201

5%1/20W

0.1UF10VX5R-CERM

10%

0201

0.1UF10V10%

0201X5R-CERM

10%10V

0201

0.1UF

X5R-CERM10V10%0.1UF

0201X5R-CERM

0.1UF10V

0201X5R-CERM

10%10V

0.1UF

X5R-CERM

10%

0201

10V10%0.1UF

0201X5R-CERM

6 16 42 68

6 16 42 68

6 16 42 68

6 16 42 68

25 68

6 16 42 68

25

6 16 42

6 17 42

6 17 25 42

19

43 70

43 70

43 70

43 70

43 70

43 70

43 70

43 70

41

41

43 70

43 70

41

41

41

41

41

41

41

41

41

41

41

41

41

41

41

41

41

41

41

41

41

41

41

41

61

17

25 35 41

41

38 41 67

38 41 67

8

41 68

41 68

41 68

41 68

38

41

23 25 51 61

41

17 23

17 25

17 41 61

19

41

41

6 41 42

6 41 42

41

41

41

48

47

47

41

6 41 48

6 41 48 51

41

6 39 41

41

17 26 61

17 26 36 48 61

17 61

6 41 48

41

41 61

41 61

6 36 41

41

41

41

41

61

25

0402

30-OHM-1.7A

10 41 56 65

6 37

41

6 37 41

6 39

17 23 25

10 65

41

41

0.1UF10VX5R-CERM

10%

02010201

10%

X5R-CERM10V

0.1UF10V

0.1UF10%

0201X5R-CERM

10V10%

0201X5R-CERM

0.1UF10V

0.1UF

X5R-CERM

10%

0201NOSTUFF0201-1

20%1.0UF

X5R-CERM10V

X5R-CERM10V10%0.1UF

02010201X5R6.3V

1UF20%

41

8

41

41

X5R-CERM0201-1

20%1.0UF10V

0201-1

10VX5R-CERM

1.0UF20%

20%1UF6.3V

0201X5R

PLACE_NEAR=U4900.D1:1MMPLACE_NEAR=U4900.D2:1MM

10%

201X5R

0.01UF10V

PLACE_NEAR=U4900.D1:1MMPLACE_NEAR=U4900.D2:1MM

41

SMCSYNC_MASTER=J30_MLB SYNC_DATE=07/26/2011

SMC_VCCIO_CPU_DIV2SMC_S5_PWRGD_VIN

CPU_CATERR_LCPU_THRMTRIP_3V3

SMC_PM_G2_ENPM_DSW_PWRGD

SMC_ADC17

SMC_ADC14SMC_ADC13SMC_ADC12

SMC_ADC16SMC_ADC15

SMC_ADC9SMC_ADC8

LPC_CLK33M_SMC

GND_SMC_AVSS

PP3V3_S5_AVREF_SMC

PP3V3_S5_SMC_VDDAMIN_LINE_WIDTH=0.25MM

VOLTAGE=3.3VMIN_NECK_WIDTH=0.1MM

LPC_AD<3>

SMC_GFX_THROTTLE_L

SMC_ADC3SMC_ADC2

SMC_TMSSMC_TCK

=PP3V3_S5_SMCSMC_ADC6

USB_SMC_P

SMC_TX_L

USB_SMC_N

SMC_RX_LSMC_OOB1_RX_L

SMC_DEBUGPRT_EN_L

SMC_ADAPTER_EN

SMC_OOB1_TX_L

PM_PWRBTN_L

ALL_SYS_PWRGD

SPI_SMC_CLK

SMC_RUNTIME_SCI_L

SMC_LRESET_L

SMC_DELAYED_PWRGD

PM_SLP_S3_L

NC_SMC_XOSC1

SMC_ONOFF_LPM_SLP_S5_LPM_SLP_S4_L

G3_POWERON_L

SMBUS_SMC_3_SDASMBUS_SMC_3_SCL

SMBUS_SMC_2_S3_SCLSMBUS_SMC_1_S0_SDA

SMBUS_SMC_0_S0_SCL

LPC_PWRDWN_L

PM_PCH_SYS_PWROK

SPI_SMC_MOSI

SMC_PROCHOT

SPI_SMC_MISO

SMC_BATLOW_L

PM_SYSRST_L

SMC_ADC18

SMC_SYS_LEDSMC_DEBUGPRT_TX_L

SMC_ADC1

SMC_ADC22

SMC_ADC10

SMC_ADC23

SMC_ADC11

SMC_ADC4

SMC_ADC7

SMC_XTAL

WIFI_EVENT_LSMC_WAKE_L

SMC_FAN_0_CTL

IR_RX_OUT_RC

LPC_AD<2>

SMC_ADC5

NC_SMC_HIB_L

SMC_RESET_L

SMC_TDISMC_TDO

LPC_AD<1>

SMC_MPM5_LED_PWR

SMBUS_SMC_4_ASF_SCL

SPI_SMC_CS_L

MEM_EVENT_L

SMC_BC_ACOK

SMC_ADC20

CPU_PROCHOT_L

SMC_MPM5_LED_CHG

SMBUS_SMC_5_G3_SDASMBUS_SMC_5_G3_SCL

SMC_FAN_1_CTLSMC_FAN_0_TACH

SMBUS_SMC_4_ASF_SDA

LPC_AD<0>

LPC_SERIRQ

SMC_ADC0

SMC_WAKE_SCI_L

SMBUS_SMC_1_S0_SCL

SMC_CLK32K

SMC_SYS_KBDLED

SMC_FAN_1_TACH

SMBUS_SMC_0_S0_SDA

SMC_ADC19

SMC_ADC21

PP1V2_S5_SMC_VDDCMIN_LINE_WIDTH=0.25MM

VOLTAGE=1.2VMIN_NECK_WIDTH=0.1MM

SPI_DESCRIPTOR_OVERRIDE_L

SMC_PECI_L

SMC_S4_WAKESRC_EN

SMS_INT_L

SMC_LID

SMC_PME_S4_DARK_LSMC_PME_S4_WAKE_L

SMC_ODD_DETECTHISIDE_ISENSE_OCSYS_ONEWIRE

SMC_T25_EN_L

CPU_PECI_R

SMC_EXTAL

SMBUS_SMC_2_S3_SDA

SMC_DP_HPD_LSMC_BIL_BUTTON_L

ENET_ASF_GPIOSMC_THRMTRIP

SYS_TDM_ONEWIRE

PM_CLKRUN_L

SMC_DEBUGPRT_RX_L

SMC_GFX_OVERTEMP

BDV_BKL_PWM

S5_PWRGD

LPC_FRAME_L

U4900

E2

E1

F2

F1

B3

A3

B4

A4

B5

A5

B6

A6

C1

C2

B1

B2

G2

G1

H1

H2

B7

A7

B8

A8

K2

K1

L2

E10

D13

M4

N2

N8

M8

L8

K8

N7

M7

N4

N3

B13

A13

C12

D11

H12

G11

D12

F13

C13

F12

H13

L1

C4

C6

L9

K9

J4

J2

B12

C11A12

H11

L13

G3

D10

L11N12

N11

M11

M13L12

M5

J12

J13

L5

D8

K6

D4

E4

F5

N5N6

K5

M6

L6

M2

M3

L4

N1

L10

K10

M9

N9

F4

F3

C9

B9

A9

C8

D5

C5

L3

M1

F11

E11

E13

E12

K7

L7

K3

K4

J3

H4

H3

G4

H10

U4900

A1

C7

K11

D9

E5

F9

H5

H9

J5

J8

J11

C3E3

M12

G12G13

B11

G10 C10

A10

A11

B10

K12

D7

E6

E8

E9

F10

J7

J9

J10

D3

J1

J6

K13

D6

D1

D2

N13

M10

N10

XW490012

R49021

2

C49061

2

C49051

2

C49091

2

C49081

2

C49041

2

C49031

2

C49071

2

L4901

1 2

C49171

2

C49161

2

C49151

2

C49141

2

C49131

2

C49101

2

C49011

2

C49021

2

C49111

2

C49121

2

C49211

2

C49201

2

051-9276

2.7.0

49 OF 109

40 OF 72

A2

41

41

41 44 45

41

6 41 42

6 41 42

7 41

24 67

24 67

41

6 41 42

6 41 42

41

41

IN

OUT

BI

IN

IN

IN

REFOUT

MR1*

THRMGND

RESET*

DELAY

MR2*

VINV+

SN0903048

PAD

OUT

IN OUT

OUT

IN OUT

OUTIN

OUTIN

OUTIN

OUTIN

OUT

IN

D

GS

D

G S

D

S G

D

S G

BIOUT

IN

OUT

IN

IN

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



NOTE: Internal pull-ups are to VIN, not V+.

SMC12 Eng Pkg Support

Used on mobiles to support SMC reset via keyboard.MR1* and MR2* must both be low to cause manual reset.

Eng Package requires 1.2V ON SMC_ADC23 pin.

BATLOW# Isolation

Debug Power "Buttons"

ADC10 and ADC11 are shared

(IPU)

Desktops: 5VMobiles: 3.42V

Module has 3.3K PU

Internal 20K pull-up on

Note:

From SMC

To SMC

SMC12 PECI Support

with comparators on Stack Board.

PM_BATLOW_L in PCH.

(IPU)

From/To CPU/PCH

SMC12 SPI Support

values:5,6,8,10,12,16,18,20,24,25 MHzSMC USB Clock require these crystal

SMC Crystal Circuit

SMC Reset "Button", Supervisor & AVREF Supply

Series resistors are no stuffed until thetopology of 2 SPI Masters are verified.

1/20W MF10K

2015%

MF1/20W 201100K

5%10KMF 2011/20W5%

MF 2011/20W5%100K

10K2015% 1/20W MF10K

1/20W5% MF 201

MF10K

5% 1/20W 20110K1/20W MF 2015%

10KMF5% 1/20W 201

40 41

19

OMIT

SILK_PART=PWR_BTN

PLACE_SIDE=TOP

1/10W5%

603MF-LF

0

10 40 56 65

40

1/20W

NO STUFF

5% MF10K

201

MF10K

1/20W 2015%

MF1/20W1%

201

2.49K

12PF

NP0-C0G201

5%25V

100K1/20W MF 2015%100K1/20W 2015% MF

MF 2015%10K

1/20W

SILK_PART=PWR_BTN

1/10W5%

603MF-LF

0

OMIT

PLACE_SIDE=BOTTOM

0

603MF-LF

OMIT

5%1/10W

SILK_PART=SMC_RST

PLACEMENT_NOTE=Place R5001 on BOTTOM side

6 40 41 48

6 48

0.01UF10%10VX5R201

CERM-X5R

0.47UF10%

6.3V

402

CRITICAL

DFNVREF-3.3V-VDET-3.0V

201

10%

X5R10V

0.01UF

MF1/20W5%100K

201

6 40 42 52

17 68 5%

22

1/20WPLACE_NEAR=U1800.D3:5.1mm MF 20140 68

5% 201MF1/20W100K

6 40 48

201

100K

MF

5%1/20W

40 61 17

100K

MF201

5%1/20W

NOSTUFF

0

MF-LF402

5%1/16W

20110K

MF5% 1/20W

201MF5% 1/20W100K

10K1/20W5% 201MF

1/20WMF

1K5%

201

12PF25V5%

201NP0-C0G

NO STUFF100K5% 1/20W MF 201

42 49 68 PLACE_NEAR=U6100.2:1MM

24.9

MF1/20W1%

201

40 68

42 49 68 PLACE_NEAR=U6100.5:1MM

15

MF1/20W5%

201

40 68

42 49 68 PLACE_NEAR=U6100.6:1MM

15

1/20W5%

201MF

40 68

42 49 68

MF1/20W

15PLACE_NEAR=U6100.1:1MM

5%

201

40 68

SMC_PACKAGE:ENG

05%

MF201

1/20W

1/20W

100K1%

MF201

MF1/20W1%

201

100K

10K1/20W5% 201MF

6 40 41 48

40

NOSTUFF

201

1/20WMF

5%1.6K

0

201

1/20WMF

5%

201

5%1/20WMF

330

NO STUFFMF 2015%

10K1/20W

MF100K

2015% 1/20W

VESM

SSM3K15AMFVAPE

CRITICAL

VESM

CRITICAL

SSM3K15AMFVAPE

CRITICALSOT563SSM6N15AFE

SSM6N15AFESOT563

CRITICAL

100K1/20W5% MF 201

NO STUFF33K5% 1/20W MF 201

10 19

65 40


201

43

MF1/20W5%

10 19 65

DFN1006-3MMBT3904LP-7

CRITICAL

40 41

10UF

X5R-CERM0402-1

20%10V

5%

3.3K

MF201

1/20W

33

36

5% 201100K

1/20W MF

CRITICAL

3.2X2.5MM-SM12.000MHZ-30PPM-10PF

SMC SupportSYNC_DATE=10/06/2011SYNC_MASTER=J13_MLB

SPI_SMC_MISO

SPI_MLB_CS_L

SPI_SMC_CLK

SPI_MLB_MOSI

=CHGR_ACOK

SMC_ADC19

SMC_ADC20

SMC_3V3S0_ISENSEMAKE_BASE=TRUE

MAKE_BASE=TRUESMC_WLAN_ISENSE

NC_SCM_ADC17MAKE_BASE=TRUE

MAKE_BASE=TRUESMC_LCDBKLT_ISENSE

PM_THRMTRIP_R_L

SMC_ADC4

=PP3V3_S5_SMC

SMC_EXTAL

SMC_XTAL_R

MAKE_BASE=TRUENC_BDV_BKL_PWM

MAKE_BASE=TRUENC_HISIDE_ISENSE_OC

NC_SMC_DP_HPD_LMAKE_BASE=TRUE

NC_ENET_ASF_GPIOMAKE_BASE=TRUE

MEM_EVENT_L

PM_THRMTRIP_L

SMC_GFX_ISENSEMAKE_BASE=TRUE

=BT_WAKE_LMAKE_BASE=TRUE

SMC_PME_S4_WAKE_L

SPI_SMC_MOSI

=TBT_WAKE_LSMC_PME_S4_DARK_LMAKE_BASE=TRUE

SYS_TDM_ONEWIRE

SMBUS_SMC_4_ASF_SCL

MAKE_BASE=TRUENC_SMBUS_SMC_4_ASF_SDA

HISIDE_ISENSE_OC

SMC_DP_HPD_L

NC_SMC_GFX_THROTTLE_LMAKE_BASE=TRUE

SMC_VCCIO_CPU_DIV2

SMC_BC_ACOKMAKE_BASE=TRUE

ENET_ASF_GPIO

SMC_GFX_THROTTLE_L

SMC_FAN_1_TACH

SMC_ADC17

SMC_ADC21

SMC_GFX_OVERTEMP

CPU_PECI_R

SMC_PME_S4_DARK_L

MAKE_BASE=TRUESMC_GFX_VSENSE

PM_THRMTRIP_L_R

SMC_TCKSMC_TDISMC_TDO

SMC_DEBUGPRT_RX_L

SMC_LID

SMC_ONOFF_L

SMC_ODD_DETECT

=PP3V3_SUS_SMC

SPI_SMC_CS_L

=PP3V3_S4_SMC

SMC_MPM5_LED_CHG

SMC_ADC3

SMC_ADC15

SMC_PECI_L

CPU_PECI

SMC_PECI_L_R

=PPVCCIO_S0_SMC

NC_SMC_ADC21MAKE_BASE=TRUE

CPU_THRMTRIP_3V3

SMC_THRMTRIP

SPI_MLB_CLK

SMC_ADC5

SMC_DCIN_ISENSEMAKE_BASE=TRUE

SMC_ADC14

MAKE_BASE=TRUESMC_OTHER_HI_ISENSEMAKE_BASE=TRUESMC_HS_COMPUTING_ISENSESMC_ADC8

SMC_DCIN_VSENSEMAKE_BASE=TRUE

SMC_HDD_ISENSEMAKE_BASE=TRUE

=PPVCCIO_S0_SMC

WIFI_EVENT_L

MAKE_BASE=TRUESMC_VCCSA_VSENSE

=PP3V3_S5_SMCBATLOW

PM_BATLOW_L

SMC_TPAD_RST_L

CPU_PROCHOT_L

SMC_PROCHOT

SMC_BATLOW_L

SMC_PBUS_VSENSEMAKE_BASE=TRUE

SMC_XTAL

SMC_ADC9

MAKE_BASE=TRUESMC_CPU_ISENSE

SMC_ADC23

MAKE_BASE=TRUESMC_CPUVCCIO_ISENSE

MAKE_BASE=TRUESMC_CPU_SA_ISENSE

SMC_ADC12

SMC_ADC10

SMC_ADC11

SMC_ADC13

SMC_ADC16

BDV_BKL_PWM

PP3V3_S5_AVREF_SMCMIN_LINE_WIDTH=0.4 mm


SMC_ADC0

SMC_T25_EN_L

SMC_1V5S3_ISENSEMAKE_BASE=TRUE

MAKE_BASE=TRUESMC_BMON_ISENSESMC_ADC7

SMC_ADC22

MAKE_BASE=TRUENC_SMC_T25_EN_L

PM_CLK32K_SUSCLK_R SMC_CLK32K

SMBUS_SMC_4_ASF_SDA


NC_SMC_MPM5_LED_PWRMAKE_BASE=TRUE

MAKE_BASE=TRUENC_SMC_MPM5_LED_CHG

NC_SYS_TDM_ONEWIREMAKE_BASE=TRUE

SMC_RESET_L


SMC_ADC6

SMC_CPU_VSENSEMAKE_BASE=TRUE

SMC_OOB1_TX_L

SMC_S5_PWRGD_VIN

SMC_BIL_BUTTON_LSMC_BC_ACOK

SMS_INT_L

SMC_ADC23

SMC_FAN_1_CTL

MAKE_BASE=TRUENC_SMC_FAN_1_TACH

NC_SMC_FAN_1_CTLMAKE_BASE=TRUE

MAKE_BASE=TRUENC_SMC_GFX_OVERTEMP

SPI_MLB_MISO

MAKE_BASE=TRUENC_SMBUS_SMC_4_ASF_SCL

SMC_ADC2

SMC_ADC1

SMC_ONOFF_L

MAKE_BASE=TRUESMC_ADC23

SMC_RX_L

G3_POWERON_L

SMC_TX_L

SMC_DEBUGPRT_TX_L

SMC_TMS

SMC_ADAPTER_EN

CPU_THRMTRIP_3V3

SMC_ROMBOOT

SMC_S4_WAKESRC_EN

SMC_DELAYED_PWRGD

SMC_THRMTRIP

PP3V3_WLAN_F

SMC_MPM5_LED_PWR

=PP3V3_S0_SMC

=PP3V3_S5_SMC=PP3V3_S4_SMC

SMC_ADC18

MAKE_BASE=TRUENC_SMC_ADC22

PP1V2_S5_SMC_VDDC

SMC_MANUAL_RST_L

GND_SMC_AVSSMIN_LINE_WIDTH=0.4 mmMIN_NECK_WIDTH=0.1 mmVOLTAGE=0V

=PPVIN_S5_SMCVREF

SMC_ONOFF_L

R5070 1 2

R5071 1 2

R5073 1 2

R5074 1 2

R5077 1 2

R5078 1 2

R5079 1 2

R5080 1 2

R5085 1 2

R50151

2

R5089 1 2

R5081 1 2

R50101 2

C50111

2

R5087 1 2

R5092 1 2

R5072 1 2

R50161

2

R50011

2

C5001 1

2

C5020 1

2 U5010

4

2

6

7

8

5

9

1 3

C50261

2

R50001

2

R50121 2

R5090 1 2

R50821

2

R50401

2

R50411 2

R5075 1 2

R5076 1 2

R5086 1 2

R50881

2

C50101

2

R5068 1 2

R50211 2

R50221 2

R50231 2

R50241 2

R50991

2

R50971

2

R50961

2

R5093 1 2

R50531

2

R50521 2

R50511

2

R5014 1 2

R5017 1 2

Q5040

3

12

Q50503

1 2

Q50596

21

Q50593

54

R5067 1 2

R5066 1 2

R50341 2

Q50581

3

2

C5025 1

2

R50581 2

R5091 1 2

Y5010

2 4

1 3

051-9276

2.7.0

50 OF 109

41 OF 72

44 52

40

40

44

45

45

40

7 40 41

40

40

44

40 41

40

40

40

40

40

6 39 40 41

40

40

40

40

40

40

40 41

44

6 40 42

6 40 42

6 40 42

38 40 67

6 40 48 51

6 40 41 48

40

7

7 41

40

40

40

7 41 40

45

40

45

45 40

44

45

7 41

6 36 40

44

7

44

40

40

44

40 41

44

44

40

40

40

40

40

40

40

40

40

45

45 40

40

40

40

44

6 37 40

40

40

6 39 40 41

40

40 41

40

40

40

40 41

6 40 42

40

6 40 42

38 40 67

6 40 42

17 40 61

40 41

6 42

40 61

25 35 40

40 41

6 36

40

7

7 40 41

7 41

40

40

40 44 45

7

OUTIN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

IN

OUT

IN

BI

BI

OUT

IN

BI

IN

IN

OUT

BI

BI

IN

OUTIN

OUTIN

INOUT

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

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C

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SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



SPI Bus Series Termination

998-4235

LPC+SPI Connector

201

435%1/20W


LPCPLUS

MF

41 49 68

201MF

1/20WPLACE_NEAR=R5127.2:5mm

43

5%

PLACE_NEAR=U1800.W8:5mm

15

MF

5%

201

1/20W

16 68

201

435%1/20W


LPCPLUS

MF201

1%24.9


LPCPLUS

1/20WMF

6 40 41

6 40 41

6 40 41

6 40 41

6 41

6 40 41 52

6 40 41

6 19

6 25 68

6 16 40 68

6 16 40 68

6 42

6 16 40 68

6 25 68

6 16 40 68

6 40 41

6 17 25 40

6 16 40

6 42

6 42

6 17 40

6 19 49

6 16 40 68

6 42

DF40C-30DP-0.4VM-ST-SM

CRITICAL

LPCPLUS

41 49 68

MF1/20W5%

15PLACE_NEAR=U1800.AB8:5mm

201

16 68

41 49 68

15

201MF

1/20W5%

PLACE_NEAR=U1800.AD12:5mm

16 68

41 49 68

1/20W1%

24.9

PLACE_NEAR=U6100.2:5mm

MF201

16 68

201

1/20W5%

43


MF

201

435%1/20WMF

LPCPLUS


201

5%1/20W


43

MF

LPC+SPI Debug Connector


SPI_ALT_MOSI

SPI_ALT_MISO

LPC_AD<2>

=PP5V_S0_LPCPLUS

SPI_ALT_CS_L

LPC_FRAME_L

SPIROM_USE_MLB

PM_CLKRUN_L

SPI_ALT_CLK

SPI_ALT_CS_L

SPI_MLB_CS_LSPI_CS0_R_L

SMC_TX_L

TP_SMC_MD1

TP_SMC_TRST_L

SMC_TDO

LPCPLUS_GPIO

LPC_AD<3>

SPI_ALT_MOSI

LPC_AD<0>

LPC_CLK33M_LPCPLUS

SMC_TMS

SMC_RX_L

SMC_ROMBOOT

SMC_RESET_L

SMC_TCK

LPC_SERIRQ

SPI_ALT_CLK

SPI_ALT_MISO

=PP3V3_S5_LPCPLUS

LPCPLUS_RESET_L SMC_TDI

LPC_PWRDWN_L

LPC_AD<1>

SPI_MOSI_R

SPI_CLK_R

SPI_MISO

SPI_CS0_L

SPI_MLB_CLK

SPI_MLB_MISO

SPI_MLB_MOSI

SPI_CLK

SPI_MOSI

R51101 2

R51111 2

R51231 2

R51201 2

R51251

2

R51211 2

R51261

2

R51221 2

R51121 2

R51271

2

R51281

2

J5100

1

10

11 12

13 14

15 16

17 18

19

2

20

21 22

23 24

25 26

27 28

29

3

30

31 32

33 34

4

5 6

7 8

9

051-9276

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6 42

6 42

6

6

6 7

68

68

68

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DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



Margin Control

access PCH

PCH S0 "SMLink 1" Connections

(Write: 0x88 Read: 0x89)

PCH S0 "SMLink 0" Connections

Internal DP

(MASTER)

J2600 & J2650

Left I/O Board

U6800

Mikey

SMC "3" SMBus S3 Connections

SMC "5" SMBus G3H Connections



SMC

DVR - (Write: 0x4E Read: 0x4F) Y Y Y Y N

NOTE: SMC RMT bus remains powered and may be active in S3 state

Parade T-con - (0x10-0x1F or 0x30-0x3F) Y N * N *

SMC S0 "1" SMBus Connections

Finstack Temp - (Write: 0x92 Read: 0x93)

ALS - (write: 0x72 Read: 0x73)

(Write: 0xXXX Read: 0xXXX)

TBT



Cougar-Point

TBT & Inlet Temp

Samsung LGD Samsung LGD AUO

K21 K78

J9000

(See Table)

Internal DP


EMC1704: U5400

Trackpad

J5700


U3300


U3301

(MASTER)

SMC Battery Charger

Cougar-Point

SMLink 1 is slave port to

XDP Connectors

(MASTER)

SMC

U4900

Cougar-Point

U1800

(MASTER)

SMC

U4900

(MASTER)

(See Table)

SMC

U1800

Battery

(MASTER)

(MASTER)

U4900

J6955

Battery

U1800

VRef DACs

(MASTER)

U4900

U4900

CPU Temp

J4700

(See Table)

Left I/O Board

LED BACKLIGHT

(WRITE: 0x58 READ: 0x59)

U9701

EMC1414-A: U5570


ISL6258 - U7000

Battery Manager - (Write: 0x16 Read: 0x17)

(* = Multiple options)


U3600

Analogix T-con - (Write: 0x7B/0x87 Read: 0x7C/0x88) N Y * Y *

PCH S0 SMBus "0" Connections

201

4.7K5%1/20WMFMF

4.7K

201

5%1/20W

2.0K1/20W

MF201

5%2.0K

MF

5%1/20W

201

1/20W

1K

201

5%

MF201

5%

MF

1K1/20W

201MF

5%1/20W

4.7K

201

4.7K

MF1/20W

5%

201MF

1/20W5%

8.2K

201MF

8.2K1/20W5%

1K

MF201

5%1/20W1/20W

MF

1K5%

201

201MF

5%2.0K

1/20W

2.0K

1/20W5%

MF201


SMBus Connections

=PP3V3_S0_SMBUS_PCH

MAKE_BASE=TRUE

SMBUS_PCH_CLK

=I2C_CPUTHMSNS_SCL

=I2C_CPUTHMSNS_SDA

=I2C_LIO_SDA

=I2C_LIO_SCL

=SMBUS_CHGR_SCL

=I2C_BKL_1_SDA

=PP3V3_S3_SMBUS_SMC_MGMT

SML_PCH_0_DATAMAKE_BASE=TRUE

=SMBUS_BATT_SDA

=SMBUS_BATT_SCL

=PP3V42_G3H_SMBUS_SMC_BSA

=PP3V3_S0_SMBUS_PCH

=I2C_VREFDACS_SCL

=SMBUS_CHGR_SDA

=I2C_VREFDACS_SDA

=SMBUS_XDP_SDA

=I2C_PCA9557D_SDA

=I2C_TBT_INLET_THMSNS_SDA

=I2C_TPAD_SDA

=I2C_BKL_1_SCL

=PP3V3_S3_SMBUS_SMC_A_S3

=I2C_TBT_INLET_THMSNS_SCL

=I2C_TPAD_SCL

SMBUS_SMC_2_S3_SCLMAKE_BASE=TRUE

SMBUS_SMC_2_S3_SDAMAKE_BASE=TRUE

MAKE_BASE=TRUE

SMBUS_SMC_3_SCL

SMBUS_SMC_3_SDAMAKE_BASE=TRUE

MAKE_BASE=TRUE

SMBUS_SMC_5_G3_SDA

SMBUS_SMC_5_G3_SCLMAKE_BASE=TRUE

=I2C_TBTRTR_SCL

MAKE_BASE=TRUE

SMBUS_SMC_1_S0_SDA

MAKE_BASE=TRUE

SMBUS_SMC_1_S0_SCL

=PP3V3_S0_SMBUS_SMC_B_S0

=I2C_TCON_SDA

=I2C_TCON_SCL

=I2C_TBTRTR_SDA

=I2C_MIKEY_SCL

=SMBUS_XDP_SCL

MAKE_BASE=TRUE

SMBUS_PCH_DATA

=PP3V3_S0_SMBUS_SMC_0_S0

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SCL

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SDA

=I2C_MIKEY_SDA

SML_PCH_1_CLK

SML_PCH_0_CLKMAKE_BASE=TRUE

SML_PCH_1_DATA

=I2C_PCA9557D_SCL

R52611

2

R52601

2

R52801

2

R52811

2

R52701

2

R52711

2

R52511

2

R52501

2

R52101

2

R52111

2

R52011

2

R52001

2

R52911

2

R52901

2

051-9276

2.7.0

52 OF 109

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46

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6 39

52

64

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6 51

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31

52

31

23

31

45

6 48

64

7

45

6 48

40 70

40 70

40 70

40 70

40 70

40 70

33

40 70

40 70

7

62

62

33

6 39

23

16 68

7

40 70

40 70

6 39

16 68

16 68

16 68

31

OUT

IN

OUT

S

S

D

N-CHANNEL

G

D

G

P-CHANNEL

OUTIN

IN

V+

REFIN+

IN- OUT

GND

OUT

OUT

IN

IN

IN

IN

V+

V-THRM

V+

V-THRM

OUT

S

S

D

N-CHANNEL

G

D

G

P-CHANNEL

OUT

IN

IN

OUT

IN

IN

V-

V++

-

V-

V++

-

OUT

IN

IN

OUT

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6 3



Max VOut: 2.18V at 27.2A

CPU Vcore Voltage Sense / Filter

Sense R is R7140

EDP: 6ASense R is 1mOhm

Sense R is R7831

Scale: 2.5A / V

CPU SA Current Sense / Filter

EDP: 18A TDP: 15.3ASense R is 0.75mOhm

Scale: ???A / V

Gain:???EDP: 5A

Sense R is R7550

Gain:110.181x

Max VOut: ???V at ???A

Gain:???

Max VOut: ???V at ???A

Sense R is 1mOhm

Sense R is R7640, 2mOhm


Scale: 8.24A / V

Max VOut: 3.3V at 19.77V Input

RTHEVENIN = 4573 Ohms

Enables PBUS VSense

EDP: 8.5A TDP :7.225A

Gain:161.765x

Gain: 200x

3.3V S0 FET Current Sense / Filter

Scale: ???A / V

Scale: 12.1A / VMax VOut: 2.73V at 39.934A

EDP: 33A TDP :28.05A

CPU VCore Load Side Current Sense / Filter

RTHEVENIN = 4573 Ohms

VCCSA Voltage Sense / Filter

CPU 1.05V VCCIO Current Sense / Filter

(200V/V)

Sense R is 0.75mOhmSense R is R7510

PBUS Voltage Sense Enable & Filter

DC-In Voltage Sense Enable & Filter

Max VOut: 3.3V at 19.77V Input

GFX/IG VCore Load Side Current Sense / Filter

GFX/IG Vcore Voltage Sense / Filter

divider when in S0.

Enables DC-In VSense

Enables DC-In VSense

divider when AC present.

divider when SUS present.

41

0.22UF

0201

6.3V20%

X5R

PLACE_NEAR=U4900.C1:5MM

4.53K

1%


201MF

1/20W

61 1%

MF201

100K1/20W

100K1%

1/20WMF201

41

20%

0201X5R6.3V

0.22UF


PLACE_NEAR=U4900.A3:5MM27.4K1/20W

MF201

1%


201

5.49K1%

MF1/20W

NTUD3169CZSOT-963

41

1/20W

201MF

4.53K

1%

VCCIOISNS_ENGPLACE_NEAR=U4900.A6:5MM

VCCIOISNS_ENG

6.3V

0201

20%

X5R

0.22UF


6.3VX5R

0.1UF10%

201

VCCIOISNS_ENG

58 71

58 71

SC70

VCCIOISNS_ENG

CRITICAL

INA210PLACE_NEAR=R7640.3:5MM


PLACE_NEAR=U4900.E1:5MM

1%

4.53K

MF1/20W

201

41

41

PLACE_NEAR=U4900.E1:5MMPLACE_NEAR=U4900.M11:5MM

0.22UF6.3V20%

X5R0201

PLACE_NEAR=U4900.H1:5MMPLACE_NEAR=U4900.M13:5MM

0201

6.3VX5R

20%0.22UF

PLACE_NEAR=U5340.8:3MM

10%

X5R6.3V

201

0.1UF

PLACE_NEAR=U4900.H1:5MM

4.53K

201MF

1/20W1%

57 71

57 71

56 57 71

57 71

CRITICAL

OPA2333DFN

CRITICAL

OPA2333DFN

41

1%

MF201

1/20W PLACE_NEAR=U4900.F1:5MM

27.4K

20%

0201

0.22UF

6.3VX5R

PLACE_NEAR=U4900.F1:5MM

1%

MF1/20W

5.49K

201


100K1%

MF1/20W

201

NTUD3169CZSOT-963

MF

1%

201

1/20W

100K

41

20%0.22UF

X5R6.3V

0201

PLACE_NEAR=U4900.C2:5MM201

1/20WMF

1%

4.53K


0.1UF10%


X5R201

6.3V

53 71

53 71

41

0.22UF

PLACE_NEAR=U4900.B1:5MM

20%

X5R6.3V

0201


MF201

1%1/20W

4.53K

60 71

60 71

SC70-5OPA333DCKG4

CRITICAL

CRITICAL

SC70-5OPA333DCKG4


0.1UF

201X5R6.3V10%

41

1%


201

4.53K

MF1/20W

0.22UF


20%6.3VX5R0201

SM

PLACE_NEAR=R7140.2:5 MM

0201

1/20W

4.42K

0.1%

MF


MF0201

1/20W


4.42K

0.1%


0201MF

1/20W0.1%

4.42K

PLACE_NEAR=R7550.4:5MM MF0201

1/20W

4.42K

0.1%

0201

487K0.1%

MF1/20W

MF

715K

0.1%1/20W

0201

SIGNAL_MODEL=EMPTY

0201

0.1%

MF

487K

1/20WSIGNAL_MODEL=EMPTY

715K

MF1/20W0.1%

0201


1.82K

0201MF

0.1%1/20W


0201

1.82K

0.1%1/20WMF


1.82K

0201

0.1%1/20WMF


0201

1.82K

0.1%1/20WMF

MF0201

1/20W0.1%1.00M

0201

SIGNAL_MODEL=EMPTY

1.00M

1/20WMF

0.1%

0201 SIGNAL_MODEL=EMPTY

1.00M

1/20WMF

0.1%

1.00M

0201MF1/20W0.1%

NOSTUFF

201

05%

MF1/20W

41 52

61

201

1/20WMF

5%0

SM

PLACE_NEAR=R7550.2:5 MM

41

4.53K

1/20W

201MF

1%

PLACE_NEAR=U4900.E2:5MM

0.22UF20%6.3VX5R0201

PLACE_NEAR=U4900.E2:5MMPLACE_NEAR=R7510.2:5 MM

SM


Voltage & Load Side Current Sensing

DCINVSENS_EN

PM_SUS_EN

=PPDCIN_S5_VSENSE

PDCINVSENS_EN_L_DIV

=CHGR_ACOK

DCIN_S5_VSENSE

CPUIMVP_ISUM_IOUT

CPUIMVP_ISUM_R_N

CPUIMVP_ISUM_R_P

CPUIMVP_ISUMG_R_PCPUIMVP_ISUMG_IOUT

CPUIMVP_ISUMG_R_N

GND_SMC_AVSS

GND_SMC_AVSS

SMC_VCCSA_VSENSE

=PP3V3_S0_SAISNS

VCCSAISNS_R_N

VCCSAISNS_R_P

SMC_CPUVCCIO_ISENSE

CPUVSENSE_IN

DCINVSENS_EN_L

SMC_DCIN_VSENSE

GND_SMC_AVSS

=PBUSVSENS_EN

PBUSVSENS_EN_L

PBUS_S0_VSENSE

GND_SMC_AVSS

=PPBUS_S0_VSENSE

SMC_PBUS_VSENSE

GFXVSENSE_IN SMC_GFX_VSENSE

GND_SMC_AVSS

GND_SMC_AVSS

SMC_CPU_SA_ISENSE

SMC_GFX_ISENSE

GND_SMC_AVSS

GND_SMC_AVSS

CPUVCCIOS0_CS_N

CPUVCCIOS0_CS_PGND_SMC_AVSS

CPUIMVP_ISNS1_N

CPUIMVP_ISNS1G_N

=PPGFXVCORE_S0_VSENSE

SMC_3V3S0_ISENSE

=PP3V3_S0_IMVPISNS

CPUIMVP_ISNS1_P

=PPCPUVCORE_S0_VSENSE

=PP3V3_S0_3V3S0ISNS

GND_SMC_AVSS

=PP3V3_S0_CPUVCCIOISNS ISNS_3V3S0_P

ISNS_3V3S0_N

ISENSE_3V3S0_IOUT

ISNS_3V3S0_R_N

ISNS_3V3S0_R_P

CPUVCCIO_IOUT

CPUIMVP_ISNS1G_P

ISENSE_SA_IOUT

PBUSVSENS_EN_L_DIV

VCCSAS0_CS_N

VCCSAS0_CS_P=PPVCCSA_S0_VSENSE VCCSAVSENSE_IN

SMC_CPU_VSENSE

SMC_CPU_ISENSE

C53301

2

R53301 2

XW53301 2

R53201 2

C53201

2

XW53201 2

R53021

2

R53011

2

C53041

2

R53031

2

R53041

2

Q5300

6

3

2

5

1

4

R53611 2

C53611

2

C53601

2U5360

2

5

4

6

1

3

R53411 2

C53411

2

C53511

2

C53401

2

R53511 2

U5340

3

2

1

94

8

U5340

5

6

7

94

8

R53131

2

C53141

2

R53141

2

R53121

2

Q5310

6

3

2

5

1

4

R53111

2

C53711

2

R53711 2

C53701

2

C53811

2

R53811 2

U53701

3

4

2

5

U53801

3

4

2

5

C53801

2

R53401 2

C53501

2

XW53401 2

R53421 2

R53431 2

R53521 2

R53531 2

R53441

2

R53551 2

R53451 2

R53541

2

R53721 2

R53731 2

R53821 2

R53831 2

R53741

2

R53751 2

R53851 2

R53841

2

R53151

2

R53161

2

051-9276

2.7.0

53 OF 109

44 OF 72

71

71

71

71

40 41 44 45

40 41 44 45

71

71

40 41 44 45

40 41 44 45

7

40 41 44 45

40 41 44 45

40 41 44 45

40 41 44 45

40 41 44 45

7

7

7

7

40 41 44 45

7

71

7

OUT

OUTIN

OUT

OUT

OUT

OUT

IN

IN

V+

REFIN+

IN- OUT

GND

V+

REFIN+

IN- OUT

GND

V+

REFIN+

IN- OUT

GND

IN

IN

IN

IN

IN

IN

OUTIN

IN

OUTIN-

IN+ REF

V+

GND

BI

BI

BI

BI

BI

BI

OUT

V+

REFIN+

IN- OUT

GNDIN

OUT

ALERT*

THERM*/ADDRDP1

SMCLK

SMDATA

VDD

DN1

DP2/DN3

DN2/DP3GND

IN

V+

REFIN+

IN- OUT

GND

Apple Inc.


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Max Vdiff: 24 mV

SCALE: 5A/ V

(For R and C)

Write Address: 0x98

LCD Backlight Driver Input Current Sense / Filter

From charger

Scale: 2.78A / V


ISL6259 Gain: 36x

EDP Current: 310A

Charger BMON (Production) Solution

MAX VOUT: 3.1V at 16.5A

GAIN: 50X

PLACEMENT_NOTEs:

(For R and C)

GAIN: 500X


EDP Current: 2.36A

(For R and C)

EDP Current: 0.750 A

(For R and C)

PLACEMENT_NOTEs:

Max Vdiff: 6.7 mV

EDP Current: 0.67 A

Max Vdiff: 7.0 mV

MAX VOUT: 3V AT 0.825A


Scale: 0.25A / V

Gain: 200x

PLACEMENT_NOTEs:

EDP Current: 12 A

PLACEMENT_NOTEs:

(For R and C)

PLACEMENT_NOTEs:

(200V/V)

(500V/V)


EDP Current: 3.5A

Scale: 2.5A / V

DC-In AMON

ISL6259 Gain: 20x

GAIN: 500X


SCALE: 0.2A / V

MAX VOUT: 3.3V AT 0.66A

(500V/V)


HDD Current Sense / Filter

(For R and C)


SCALE: 0.667A / V

Max Vdiff: 31 mV


Read Address: 0x99


Max Vdiff: 31 mV

EDP Current: 15.5 A

DC-IN (AMON) Current Sense Filter

OTHER High Side Current Sense / Filter

Max Vdiff: 15 mV

AirPort Current Sense / Filter

DDR3 1V5R1V35 Current Sense / Filter


SCALE: 5A / V

GAIN: 200X


(200V/V)PLACEMENT_NOTEs:

MAX VOUT: 3.1V at 16.5A

SCALE: 5A/ V

GAIN: 100X

TBT/Inlet Temp Sensor

COMPUTING High Side Current Sense / Filter

(100V/V)

EDP Current: 15.5 A

(50V/V)

CHARGER BMON High Side (BATTERY DISCHAEGE) Current Sense, MUX & Filter

41

41 PLACE_NEAR=U4900.B3:5MM

0.22UF20%6.3V

X5R0201


4.53K

MF

1%

201

1/20W

52

41

41

41

41

PLACE_NEAR=U4900.B6:5mm

Place close to SMC

X5R

20%6.3V

0.22UF

0201


4.53K

1%

Place close to SMC

201MF

1/20W

10%0.1UF

6.3V

201X5R

55 71

55 71


Place close to SMC

0.22UF

X5R

20%6.3V

AIRPORTISNS_ENG

0201


Place close to SMC

1%1/20WMF201

4.53K

AIRPORTISNS_ENG


HDDISNS_ENG

Place close to SMC

6.3V20%0.22UF

X5R0201


1/20W

HDDISNS_ENG

201

Place close to SMC

1%

4.53K

MF

X5R201

10%0.1UF

6.3V

AIRPORTISNS_ENG

SC70INA210

AIRPORTISNS_ENG

INA211SC70

HDDISNS_ENG

PLACE_NEAR=U4900.G2:5mm

LCDBKLTISNS_ENG

6.3V

0.22UF20%

X5R0201

Place close to SMC

PLACE_NEAR=U4900.G2:5mm

4.53K

1%1/20WMF201

LCDBKLTISNS_ENG

LCDBKLTISNS_ENG

201

6.3VX5R

10%0.1UF

SC70INA211

LCDBKLTISNS_ENG

36 71

36 71

37 71

37 71

8 71

8 71


1/20W

MF

1%

201

300K


10V

201

10%

3300PF

X7R

41

Place close to SMC


0201

6.3V20%

X5R

0.22UF

1%


201MF

Place close to SMC

1/20W

4.53K

6.3VX5R201

10%0.1UF

8 71

8 71

INA214SC70

X5R

10%6.3V

HDDISNS_ENG

0.1UF

201

201

5%1/20WMF

10K10K

201

5%1/20W

MF

43

43

10%6.3V

201X5R

0.1UFMF201

5%1/20W

47

SIGNAL_MODEL=EMPTY

PLACE_NEAR=U5410.3:5mmPLACE_NEAR=U5410.2:5mm

0201

10%2200PF

10VX7R-CERM

46 71

46 71


SIGNAL_MODEL=EMPTY

10%

X7R-CERM0201

10V

2200PF

46

46

41

Place close to SMC


0.22UF

0201X5R

20%6.3V


201

1/20W1%

MF

4.53K

Place close to SMC

201

10%6.3VX5R

0.1UF

SC70INA213

CRITICAL

CRITICAL

MF

1%1W

0.005

0612

7

7

EMC1414-1-AIZL

CRITICAL

MSOP

52

SC70INA210

High Side Current Sensing



ISNS_HS_COMPUTING_P

ISNS_HS_COMPUTING_IOUT

=PP3V3_S0_HS_OTHER_ISNS

=TBTTHMSNS_D2_N

=TBTTHMSNS_D2_P

ISNS_1V5_S3_N ISNS_1V5S3_IOUT

=PP3V3_S3_1V5S3ISNS

ISNS_1V5_S3_P

SMC_1V5S3_ISENSE

INLET_THMSNS_D1_N

SMC_DCIN_ISENSE

TBT_INLET_THM_L


=PP3V3_S0_HDDISNS

GND_SMC_AVSS

TBT_INLET_ALERT_L

=I2C_TBT_INLET_THMSNS_SDA

ISNS_SSD_N

ISNS_SSD_P

GND_SMC_AVSS

ISNS_P5VHDD_IOUT

ISNS_AIRPORT_P

ISNS_P5VWLAN_IOUT

GND_SMC_AVSS

SMC_LCDBKLT_ISENSE

SMC_HDD_ISENSE

ISNS_LCDBKLT_P

ISNS_LCDBKLT_N

GND_SMC_AVSS

SMC_WLAN_ISENSE

ISNS_LCDBKLT_IOUT

=PP3V3_S0_BKLTISNS

CHGR_AMON

ISNS_AIRPORT_N

GND_SMC_AVSS

=PP3V3_S3_WLANISNS

GND_SMC_AVSS

SMC_HS_COMPUTING_ISENSE

SMC_OTHER_HI_ISENSE

=PPVIN_S5_HS_OTHER_ISNS_R

ISNS_HS_OTHER_P

ISNS_HS_OTHER_N

ISNS_HS_COMPUTING_N

=I2C_TBT_INLET_THMSNS_SCL

INLET_THMSNS_D1_P

GND_SMC_AVSS

SMC_BMON_ISENSECHGR_BMON

HS_OTHER_IOUT

=PPVIN_S5_HS_OTHER_ISNS

VOLTAGE=3.3VMIN_NECK_WIDTH=0.20 mmMIN_LINE_WIDTH=0.5 mmPP3V3_S0_HS_COMPUTING_ISNS_R

GND_SMC_AVSS

C54311

2

R5431

1 2

C54651

2

R54651 2

C54601

2

C54751

2

R54751 2

C54851

2

R54851 2

C54701

2U5470

2

5

4

6

1

3

U5480

2

5

4

6

1

3

C54951

2

R54951 2

C54901

2U5490

2

5

4

6

1

3

R5422

1 2

C54221

2

C54551

2

R54551 2

C54501

2U5450

2

5

4

6

1

3

C54801

2

R54121

2

R54111

2

C54101

2

R54101 2

C5411 1

2

C5412 1

2

C54331

2

R54331 2

C54301

2U5430

2

5

4

6

1

3

R5430

12

34

U5410

83

5

2

4

6

10

9

7

1

U5460

2

5

4

6

1

3

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54 OF 109

45 OF 72

7 45

7

7

7 45

7

40 41 44 45

40 41 44 45

40 41 44 45

40 41 44 45

7

40 41 44 45

7

40 41 44 45

71

71

40 41 44 45

40 41 44 45

BI

BI THRM_PADDN2/DP3

DP2/DN3

VDD

SMDATA

SMCLKGND

DN1

DP1 THERM*/ADDR

ALERT*

BI

BI

BI


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Place U5510 under CPU

Placement note:

Use GND pin B1 on U3600 for N leg

CPU Proximity Sensor

Read Address: 0x99Write Address: 0x98

Placement note:

To connect Die Sensor, Stuff R5550 & R5551, No stuff R5540 & R5541

To connect Proximity Sensor, Stuff R5540 & R5541, No Stuff R5550,R5551

Detect TBT Die Temperature

TBT Die

Placement note:Place Q5540 on MLB bottom side opposite U5400

Replacing caps with 100K PD on ISENSE SMC inputs

Placement note:Place Q5520 close to TBT on TOP side

Detect CPU Die Temperature

Detect DDR/5V/3.3V Proximity Temperature

Place Q5510 next to DDR/5V/3.3V supply on TOP side

Placement note:

Place Q5530 between near rear vent on bottom side

TBT,MLB Bottom & Inlet Proximity Sensors

10K

MF1/20W5%

201MF

1/20W5%

10K

201


SIGNAL_MODEL=EMPTY

10%10V

X7R-CERM

2200PF

0201

9 71

9 71

CRITICAL

DFNEMC1413

33

SM


201

1/20W5%

0

MF

201

1/20W5%

MF

0

NO STUFF

0

MF201

5%1/20W

0

MF201

5%1/20W

NO STUFF

BC846BLPDFN1006H4-3

BC846BLPDFN1006H4-3

BC846BLPDFN1006H4-3

BC846BLPDFN1006H4-3

43

43

201

6.3VX5R

0.1UF10%

47

5%

MF1/20W

201

2200PF

X7R-CERM

SIGNAL_MODEL=EMPTY


10%10V

0201

Thermal Sensors


RES,MF,1/20W,100K OHM,5,0201,SMD C5495 LCDBKLTISNS_PROD117S0008 1

117S0008 RES,MF,1/20W,100K OHM,5,0201,SMD C5485 HDDISNS_PROD1

117S0008 RES,MF,1/20W,100K OHM,5,0201,SMD1 VCCIOISNS_PRODC5361

117S0008 AIRPORTISNS_PRODRES,MF,1/20W,100K OHM,5,0201,SMD C54751

=MLBBOT_THMSNS_D3_N

=MLBBOT_THMSNS_D3_P

INLET_THMSNS_D1_P

INLET_THMSNS_D1_N

TBTTHMSNS_D2_R_P

TBTTHMSNS_D2_R_N

CPUTHMSNS_D2_P

CPUTHMSNS_D2_N

=TBTTHMSNS_D2_N

=I2C_CPUTHMSNS_SDA

TBT_THERMD_N

=TBTTHMSNS_D2_P

=TBTTHMSNS_D2_N

TBT_THERMD_PMAKE_BASE=TRUE

=TBTTHMSNS_D2_N

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.25 mmPP3V3_S0_CPUTHMSNS_R


CPUTHMSNS_THM_L

CPUTHMSNS_ALERT_L

=I2C_CPUTHMSNS_SCL

CPU_THERMD_P

CPU_THERMD_N

=PP3V3_S0_CPUTHMSNS

=TBTTHMSNS_D2_P

TP_TBT_THERM_DP

MAKE_BASE=TRUETBT_MLBBOT_THMSNS_P =MLBBOT_THMSNS_D3_P

=MLBBOT_THMSNS_D3_N

=TBTTHMSNS_D2_P

MAKE_BASE=TRUETBT_MLBBOT_THMSNS_N

C55101

2

R55101 2

C5512 1

2

R55121

2

R55111

2

C5511 1

2

U5510

83

5

2

4

6

10

9

7

11

1

XW55201 2

R55401 2

R55411 2

R55501 2

R55511 2

Q5510 1

3

2

Q5520 1

3

2

Q5530 1

3

2

Q5540 1

3

2

051-9276

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55 OF 109

46 OF 72

46

46

45 71

45 71

71

71

71

71

45 46

71

45 46

45 46

71

45 46

7

45 46 71

46

46

45 46

71

D

GS

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NC

GNDMOTOR CONTROL

TACH5V DC

NC

FAN CONNECTOR

518S0793

5%1/20WMF201

47KMF

5%1/20W

47K

201

201

5%1/20W

MF

100KSSM3K15FVSOD-VESM-HF

CRITICAL

F-RT-SMFF14A-4C-R11DL-B-3H

Fan


=PP5V_S0_FAN

=PP3V3_S0_FAN

SMC_FAN_0_TACH

SMC_FAN_0_CTL

FAN_RT_TACH

FAN_RT_PWM

R56651 2

R5660 1

2

R5661 1

2

Q5660

3

12

J5600

5

6

1

2

3

4

051-9276

2.7.0

56 OF 109

47 OF 72

6 7

7

40

40

6

6

IN

VIN

SW

OUTFB

EN

NC

THRMGNDPAD

NC

NC

NC

VCC

GND

SELOE*

D+

D-

Y+

Y-

M+

M-

BI

BI

OUT

IN

OUT

OUT

BI

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IPD Flex Connector

518S0793

518S0794

SEL=1 Choose USB

Keyboard Backlight Driver & Detection

J5815 pin 1 is grounded

Keyboard Backlight Connector

grounded when KB BL flex connected.

R5853 always stuffed, R5854 only

on keyboard backlight flex

If HIGH, keyboard backlight not present

If LOW, keyboard backlight present

To detect Keyboard backlight, SMC will

tristate and read SMC_SYS_KBDLED:

SEL=0 Choose pull up/down

X5R-CERM

10%0.1UF

16V

0201

PLACE_NEAR=J5700.10:1.5MM

17 26 36 40 61

0

MF5% 1/20W201

CRITICAL


NOSTUFF

X5R-CERM

10%16V

0.1UF

0201

CRITICAL

MLFMIC2292

10K1/16WMF-LF

5%

402

1/16WMF-LF

402

5%10K

10%50V

0.22UF

X5R-CERM0603-1

CRITICAL

TQFNPI3USB102ZLE

0.1UF


10%

201X5R

6.3V

6 43 48

CRITICAL


0.1UF

6.3VX5R

10%

201


6 43 48

6 40 41 48

6 40 41 48 51

6 41 48

25V

100PF

201

5%

CERM

PLACE_NEAR=J5700.8:1.5MM100PF

201PLACE_NEAR=J5700.9:1.5mm

CERM

5%25V

25V

201

5%


CERM

100PF

100PF

25V

201CERM

5%


25V

100PF

201CERM

5%


0402-LF

FERR-120-OHM-1.5A


0

MF5% 1/20W201

6 40 41

10%50VX5R-CERM

0.22UF

0603-1

MF-LF1/16W5%

402

4.7

CRITICAL

10UH-0.58A-0.35OHM

1098AS-SM

1UF

X5R

10%10V

402-1

BYPASS=U5750.1:2:2 MM

40

0.1UF

X5R-CERM

10%16V

0201

SYNC_MASTER=K21_MLB

IPD / KBD Backlight


=PP3V3_S4_TPAD

USB_TPAD_MUX_SEL

USB_TPAD_R_P

USB_TPAD_R_N

USB_TPAD_P

USB_TPAD_N

USB_TPAD_M_P

USB_TPAD_M_N

PM_SLP_S4_L

SMC_SYS_KBDLED

SMC_TPAD_RST_L

=PP5V_S0_KBDLED

SMC_ONOFF_L

SMC_LID

SMC_ONOFF_L

SMC_TPAD_RST_L

=I2C_TPAD_SCL

SMC_PME_S4_WAKE_L

SMC_LID

VOLTAGE=3.3V MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.20mm

PP3V3_TPAD_CONN

=I2C_TPAD_SDA

MIN_NECK_WIDTH=0.20mm MIN_LINE_WIDTH=0.5 mmVOLTAGE=5V

PP5V_TPAD_FILT


KBDLED_ANODE

KBDLED_SWMIN_LINE_WIDTH=0.3 MM

SWITCH_NODE=TRUEMIN_NECK_WIDTH=0.25 MM

=PP3V3_S4_TPAD

=I2C_TPAD_SDA

=PP5V_S5_TPAD

=PP3V42_G3H_TPAD


KBDLED_FB

=I2C_TPAD_SCL

C5710 1

2

C5700 1

2

C5720 1

2

J5700

15

16

1

10

11

12

13

14

2

3

4

5

6

7

8

9

C5732 1

2C5733 1

2 C5734 1

2 C5735 1

2 C5736 1

2

L5720

1 2

R57301 2

C57551

2

R57551

2

L5750

1 2

C5750 1

2

C5701 1

2

R57041 2

J5715

5

6

1

2

3

4

C5704 1

2

U5750

3

6

4 81

7

9

2

R57031

2

R57021

2

C57561

2

U5700

6

7

3

4

5

8 10

9

2

1

2.7.0

051-9276

48 OF 72

57 OF 109

5

7 48

24 67

24 67

6 67

6 67

67

67

7

6 40 41 48 51

6 40 41 48

6 41 48

6 43 48

6

6

6

7 48

6 43 48

7

6 7

6

OUTIN

IN IN

IN RST*/HOLD*

CE*

WP*

SCK

VSS THRM_PAD

SI/SIO0

SO/SOI1

VDD

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DUAL I/O MODE (MODE 0 & 3) SUPPORTED

NOTE: If HOLD* is asserted

ROM will ignore SPI cycles.

High Speed CLK Frequency - 50MHz for fast read dual I/O

3.3K5%

201

1/20WMF

41 42 68 41 42 68

41 42 68 41 42 68

6 19 42

CRITICAL

WSON

64MBIT

OMIT_TABLESST25VF064C

X5R-CERM

10%0.1UF

16V

0201

SPI ROM


SPI_MLB_CLK

SPI_MLB_CS_L

SPI_WP_L

SPIROM_USE_MLB

SPI_MLB_MOSI

SPI_MLB_MISO

=PP3V3_SUS_ROM

R61011

2

U6100

1

7

6 5

2

9

84

3

C6100 1

2

051-9276

2.7.0

61 OF 109

49 OF 72

7

IN

IN

IN

IN-

IN+ OUT+

OUT-

GAINSHDN*

PVDD

NC

PGND

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ALIAS OF PP5VLT_S3, MIN_LINE_WIDTH=0.50MM, MIN_NECK_WIDTH=0.25MM

6DB

SPEAKER LOWPASS

GAIN

APN:353S2888

80 HZ < FC < 132 HZ

SPEAKER AMPLIFIERS

10%

CRITICAL

16V

0.1UF

0201X5R-CERM

6 39 71

0.1UF

201

6.3V10%

X5R

2012-LLP

47UF

CRITICAL

6.3V20%

POLY-TANT

1/20W5%

201MF

06 39

6 39 71 CRITICAL

MAX98300WLP

1/20W5%

201MF

100K

10%

CRITICAL

16VX5R-CERM

0.1UF

0201

1/20W5%

201MF

100K

100K

NOSTUFF

MF

5%

201

1/20W

0

5%1/20WMF201


AUDI0: SPEAKER AMP

R_AMP_GAIN

SPKRAMP_INR_N

=PP5V_S3_AUDIO_AMP

R_SPKRAMP_SHDN

AUD_GPIO_3

MAX98300_R_NSPKRAMP_INR_P MAX98300_R_P


SPKRAMP_ROUT_P

MIN_LINE_WIDTH=0.30 mmMIN_NECK_WIDTH=0.20 mm

SPKRAMP_ROUT_N

PP5V_S3_U6210


VOLTAGE=5VMIN_LINE_WIDTH=0.5 mm

C6210

1 2

C6207 1

2

C62011

2

R62101 2

U6210

C3

B3

A3

C1

B1

A2

A1

C2

R62121

2

C6211

1 2

R62111

2

R62131

2

R62141 2

051-9276

2.7.0

62 OF 109

50 OF 72

B2

7

71

71

6 51 71

6 51 71

SW

BOOSTVIN

BIAS

SHDN*

GND

NC

FB

PADTHRM

NC

IN

BI

D

GS

IN

IN

IN

SHLD_PIN

SHLD_PIN

SHLD_PIN

SHLD_PIN

NEG

POS

POS

NEG

NEG

SYS_DETECT

SDA

SCL

POS

NC

NC

NC

NC

G

D

S


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6.8V Zener

Debug LEDs

3.425V "G3Hot" SupplySupply needs to guarantee 3.31V delivered to SMC VRef generator

(For development only)

518S0508

MLB to LIO Power Cable Connector

Right Speaker Connector

518S0519

Vout = 3.425V

518-0369

<Ra>

<Rb>

Vout = 1.25V * (1 + Ra / Rb)

(Switcher limit)

60MA MAX OUTPUT

518-0369

Battery Connector

K99-Specific

CRITICAL

20%10UF

X5R-CERM10V

0402-1

0.22UF10%10VCERM402

X5R-CERM

10%4.7UF

25V

0603

CRITICAL

DFNLT3470A

CRITICAL

SOT-323BAT30CWFILM

1/8W5%

805

10

MF-LF

6 43

6 43

CRITICAL

SC-75

NO STUFF

RCLAMP2402B201MF

1/20W5%

10K

10%25VX5R402

0.1UF1UF10%16V

402X5R

402

1K5%1/16WMF-LF

S3_S0_LED

1K1/20W

S3_S0_LED

201MF

5%


S3_S0_LED

S3_S0_LED

2.0X1.25MM-SMGREEN-3.6MCD

S3_S0_LED

GREEN-3.6MCD2.0X1.25MM-SM

23 25 40 61

M-RT-SM

78171-0002

CRITICAL

6 50 71

6 50 71

10%

0201

0.1UF

X5R-CERM16V

603-1X7R50V

0.1UF10%

WTB-PWR-M82M-RT-SM

CRITICAL

CRITICAL

F-RT-THBAT-K99

OMIT_TABLE

SMHALL-SENSOR-MLB-PADS-K99

NO STUFF

402CERM50V

0.001UF10%

4.7

MF-LF1/8W

805

5%

MF-LF1/16W

402

1%348K

200K1%

1/16WMF-LF

402

402

0

5%1/16WMF-LF

402

5%22PF50VCERM

MPM5:NO

1/20WMF201

1%40.2K

100K5%1/20W

201MF

CRITICAL

GDZ-0201GDZT2R6.8

CRITICAL

SI5419DU

POWERPAK

2520

10UH-30%-0.85A-460MOHM

CRITICAL

25V10%

X5R-CERM0603

4.7UF

X5R-CERM

4.7UF10%25V

0603

4.7UF10%

X5R-CERM25V

0603

25V10%

X5R-CERM

4.7UF

0603

X5R-CERM

10%25V

4.7UF

0603

CRITICAL

20%10UF

X5R-CERM10V

0402-1

603X5R35V

NO STUFFCRITICAL

1UF10%

NO STUFFCRITICAL

603

35VX5R

1UF10%

0.1UF10%

MPM5:YES

0402

50V

X5R-CERM

0

MPM5:NO

201

5%

MF1/20W

DC-In & Battery Connectors


118S0560 CRITICALR6912RES,MF,90.9KOHM,1,1/20W,02011 MPM5:YES

R6911RES,MF,100KOHM,1,1/20W,0201117S0008 MPM5:YES1 CRITICAL

PPVBAT_G3H_CONN

=SMBUS_BATT_SCL

SYS_DETECT_L

DBGLED_S0

DBGLED_S0_D

DBGLED_S3

=PP3V3_S3_DBGLEDS

ALL_SYS_PWRGD

=SMBUS_BATT_SDA

SMC_LID_R

SMC_LID

=PP3V42_G3H_HALL

SPKRAMP_ROUT_N

SPKRAMP_ROUT_P

SWITCH_NODE=TRUEDIDT=TRUE

P3V42G3H_SWMIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.2 mm

=PP3V42_G3H_REG

P3V42G3H_FB


P3V42G3H_BOOST

MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.5 mmDIDT=TRUEPPDCIN_G3H_OR_PBUS_R


VOLTAGE=18.5V

PPVIN_G3H_P3V42G3H


PPBUS_G3H_R


PPBUS_G3H

=PP5V_S3_LIO_CONN

=PP18V5_DCIN_CONN

=PP18V5_DCIN_ISOL

DCIN_ISOL_GATE

DCIN_ISOL_GATE_R

C69991

2

C6994 1

2

C6990 1

2

U6990

2

3

1

5

8 4

9

6

D6905

1

2

3R69051 2

D6950

3

1 2R69501

2

C69501

2

C6951 1

2

R69411

2

R69401

2

Q69403

12

D6920A

K

D6910A

K

J6903

3

4

1

2

C69061

2

C6905 1

2

J6900

1

2

3

4

5

6

J6950

10

11

12

13

1

2

3

4

5

6

7

8

9

J6955

1

2

3

45

6

7

8

C6955 1

2

R69201 2

R69951

2

R69961

2

R69611 2

C69951

2

R69121

2

R69101

2

D6912

A

K

Q6910

1

4

5

5A

L6995

1 2

C6991 1

2

C6992 1

2

C6993 1

2

C6996 1

2

C6997 1

2

C69981

2

C6907 1

2

C6908 1

2

C6912 1

2

R6911

1 2

051-9276

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69 OF 109

51 OF 72

7

6 52

6

7

6

6 40 41 48

6 7

7

6 7

6 7

6 7

7

OUT

OUT

IN

BI

OUT

AMON

BMON

ACOK

LGATE

PHASE

BOOT

SGATE

AGATE

CSIP

CSIN

DCIN

VNEG

CSOP

CSON

THRM_PAD

PGND

VDDPVDD

BGATE

UGATE

ICOMP

VCOMP

ACIN

SDA

VFRQ

CELL

VHST

SCL

SMB_RST_N

IN

S

G

D

IN

G

D

S

G

D

S

SW

BOOSTVIN

BIAS

SHDN*

GND

NC

FB

PADTHRM

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6 3



Input impedance of ~40K meets

Float CELL for 1S

Reverse-Current Protection

Vout = 1.25V * (1 + Ra / Rb)

Need to stuff R7092 if either PP5V5_DCIN:YES or PP5V5_VDDP are used!

5.5v "G3Hot" Supply

For Erp Lot6 spec

Q7055.

200MA MAX OUTPUTVout = 5.50V

f = 400 kHz

TO/FROM BATTERY

Max Current = 8A

(CHGR_AGATE)

DUE TO DIFFERENT CURRENT ON _P AND _N. (FROM INTERSIL)

ACIN pin threshold is 3.2V, +/- 50mV

DIVIDER SETS ACIN THRESHOLD AT 12.18V

Charger TOP FETs and

* PBUS through Q7085,

* DCIN through Q7080.

through body diodes:

This node is powered

(CHGR_SGATE)

<Rb>

<Ra>

sparkitecture requirements

(OD)

Inrush Limiter

(PPVBAT_G3H_CHGR_R)

(CHGR_BGATE)

(AGND)

20V/V

(PPVBAT_G3H_CHGR_R)

(CHGR_CSO_N)

(CHGR_CSO_P)

36V/V

.

(GND)

FROM ADAPTER

* R7051 HAS 2.2OHM TO COMPENSATE UNBALANCED VOLTAGE

(Switcher limit)

TO SYSTEM

(CHGR_DCIN)

30mA max load

1%1/20W

23.7K

201MF

201

10%

X5R

0.1UF

6.3V

470PF10%16VX5R-X7R201

470PF

X5R-X7R

10%16V

201

1UF10%

402X5R10V

10%10V

1UF

402-1X5R

402

5%

MF-LF

4.7

1/16W

MF1/20W1%66.5K

201


SM

10V

1UF

402

10%

X5R X5R

10%0.1UF

402

25V

0.1UF

25V10%

X5R402

10%0.047UF

402X7R16V

402

0.22UF

10VCERM

10%


1/20W

10

MF

5%

201

5%

10

201MF

1/20W

33UF-0.06OHM

POLY-TANTCASE-D3L

25V20%

CRITICAL CRITICAL

25V20%

CASE-D3L

33UF-0.06OHM

POLY-TANT

CRITICAL

1206

8AMP-24V

1/20WMF

332K1%

201

62K5%1/20WMF201

0.22UF

50VX5R-CERM

10%

0603-1

45

45

43

43

0.01UF10%10VX5R201

0.47UF10%10VX5R402

16V10%

X7R201

1000PF

41 44

0612-3

MF

1W

0.5%

0.01

10%50VX7R402

PLACE_NEAR=Q7030.5:1.5mm

0.001UF

PLACE_NEAR=L7030.2:1.5mm

1000PF10%

201X7R16V

TQFN

ISL6259HRTZ

CRITICAL

OMIT_TABLE

MF

100K5%

1/20W

201

NO STUFF

61

CRITICAL

SI7615DNPWRPK-1212-8

100

1/20W

201MF

1%

BAT30CWFILM

CRITICAL

SOT-323

10%25VX5R402

0.1UF

201

1/20WMF

5%100K

1/20W

201MF

1%470K

1UF10%25VX5R603-1

10%

X5R603-1

25V

1UF

0

1/20WMF

5%

201

6 40 41 42

POWERPAK

CRITICAL

SI5419DU SI5419DUPOWERPAK

CRITICAL

25VX5R603-1

1UF10%

25V

0.1UF10%

X5R402

0.01UF10%25VX7R402

10%25VX5R805

10UF

201 1/20W5% MF

2.2

MF 2015%

01/20W

1%

MF201

1/20W

255K

2201%

1/20WMF201

CASE-B

62UF

POLY11V20%

CRITICAL

62UF

CASE-B

CRITICAL

POLY11V20%

CASE-B

CRITICAL

62UF20%11VPOLY

WPAK

RJK03P0DPA

CRITICAL

PIMC104T4R7MN-SM

4.7UH-17A

CRITICAL

CRITICAL

0.5%

0612

0.020

1W

MF-LF

MF-LF

5%

603

PP5V5_DCIN:NO

20

1/10W

603

10VX5R

10UF

CRITICAL

20%

603

CRITICAL

10VX5R

10UF20%

1%

MF

1/20W

681K

201

MF

201

1%

1/20W

200K

0.22UF10%

10V

CERM

402

22PF

50V

5%

CERM

201

CRITICAL

DFN

LT3470A

MF-LF 5%

0

PP5V5_DCIN:YES

4021/16W

402MF-LF1/16W5%

0

PP5V5_VDDP4025%

1/16W

MF-LF

NO STUFF

0

25V

0603X5R-CERM

10%4.7UF CRITICAL

10UH-30%-0.85A-460MOHM

2520

0603X5R-CERM

4.7UF10%25V


PBus Supply & Battery Charger

VOLTAGE=18.5V


PPDCIN_G3H_OR_PBUS

CHGR_SGATE



CHGR_SGATE_DIV


PPVBAT_G3H_CHGR_REGMIN_LINE_WIDTH=0.6 mm




CHGR_CSO_R_NMIN_NECK_WIDTH=0.1 mm

CHGR_CSO_R_P


=PP3V42_G3H_CHGR

CHGR_VFRQ


PPCHGR_DCIN_D_RDIDT=TRUE

P5V1_BOOST



CHGR_CSI_R_P

CHGR_BMON

CHGR_VNEG_R

=CHGR_ACOK

CHGR_LGATE MIN_NECK_WIDTH=0.2 mm


GATE_NODE=TRUE

DIDT=TRUE


MIN_LINE_WIDTH=0.5 mm DIDT=TRUE

CHGR_BOOT

PPVBAT_G3H_CONNMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.15 mm

VOLTAGE=8.4V


CHGR_UGATE MIN_NECK_WIDTH=0.2 mm

DIDT=TRUE GATE_NODE=TRUE

MIN_LINE_WIDTH=0.2 mmCHGR_VNEGMIN_NECK_WIDTH=0.2 mm

=PPBUS_G3H

CHGR_RST_L

CHGR_CSI_R_N

=SMBUS_CHGR_SCL

=SMBUS_CHGR_SDA

CHGR_DCIN


CHGR_AGATE_DIV


PPCHGR_DCIN_D_R

VOLTAGE=18.5V

DIDT=TRUE

SWITCH_NODE=TRUE

CHGR_PHASE

VOLTAGE=8.4VMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mm

CHGR_CSI_P




CHGR_AGATE


VOLTAGE=5.1V

PP5V1_CHGR_VDDP

CHGR_CSI_N



PPDCIN_G3H_CHGR

VOLTAGE=18.5V




P5V1_SW

P5V1_FB

VOLTAGE=5.5V

PP5V5_CHGR_VDDPMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mm

PP5V1_CHGR_VDDP


PPDCIN_G3H_INRUSH

CHGR_DCIN


SMC_RESET_L

CHGR_VCOMPMIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

CHGR_DCIN_D


PP5V1_CHGR_VDDMIN_LINE_WIDTH=0.2 mm


=PPDCIN_S5_CHGR_ISOL

CHGR_VCOMP_R


VOLTAGE=0V

GND_CHGR_AGND

CHGR_ACIN

CHGR_CELL


CHGR_ICOMPMIN_LINE_WIDTH=0.2 mm

CHGR_CSO_N




CHGR_BGATE

MIN_NECK_WIDTH=0.25 MMMIN_LINE_WIDTH=0.6 mm

PPVBAT_G3H_CHGR_R

VOLTAGE=8.4V

CHGR_CSO_P



CHGR_AMON

=PPDCIN_S5_CHGR

R70111

2

C70421

2

C70161

2

C7015 1

2

C70021

2

C70001

2

R70011 2

R70101

2

XW7000

1 2

C7001 1

2

C70211

2

C7022 1

2

C70201

2

C70251

2

R70221 2

R70211 2

C7030 1

2

C7031 1

2

F7040

1 2

R70861

2

R70811

2

C7005 1

2

C7011 1

2

C70501

2

C7026 1

2

R7050

2 1

4 3

C70371

2

C70451

2

U7000

3

14

1

9

16

15

25

627

28

17

18

2

5

21

22

23

11

10

2613

29

24

7

19

20

4

12

8

R70021

2

Q7055

5

4

12

3

R70131

2

D7005

1

2

3

C7085 1

2

R70801

2

R70851

2

C70351

2

C70361

2

R70001 2

Q7080

1

4

5

5A

Q7085

1

4

5

5A

C70141

2

C70131

2

C70121

2

C7017 1

2

R7051 1 2

R7052 1 2

R70151

2

R70161

2

C7040 1

2

C7043 1

2

C7041 1

2

Q7030

2

1

6

7

3 4 5

L7030

1 2

R70201

2

3

4

R70051 2

C70991

2

C70981

2

R70951

2

R70961

2

C7094 1

2

C70951

2

U7090

2

3

1

5

8 4

9

6

R7090

1 2

R7091

1 2

R7092

1 2

C7090 1

2 L7095

1 2

C7084 1

2

051-9276

2.7.0

70 OF 109

52 OF 72

7

70

70

7

52

70

6 51

7

70

52

52

70

52

70

52

52

7

70

70

7

OUT

IN

IN

IN FB

EN

PVCCVCC

SREF

VO

OCSET

PGOOD

FSEL

RTN

PHASE

LGATE

UGATE

BOOT

PGNDGND

SET0

SET1

VID0

VID1

IN

Apple Inc.


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6 3



(VCCSAS0_OCSET)

(ENDIAN SWAP)

(VCCSAS0_VO)

1 0 0.8V

6A Max Output

f = 300 kHz

OCP = 8.5A

0 1 0.725V

1 1 0.675V

OCP = R7141 x 8.5uA / R7140

VID1 VID0 Voltage

0 0 0.9V

INTEL TABLE:

61

61

SM


5%

402

1/16WMF-LF

2.2

CRITICAL

10V20%10UF

X5R-CERM0402-1

MF-LF

05%

1/16W

402

10V

402

10%

CERM

0.22UF

25V5%

402NP0-C0G

1000PF201

1K1%

1/20WMF

201

1/20WMF

1K1%

25V

402

5%


1000PF

NP0-C0G

CRITICAL

1W

0612MF-1

1%0.001

0805

CRITICAL

10UF10%

X5R-CERM16V 16V

10%

402X7R-CERM

0.1UF

12

12

10%16V

10UF

0805

CRITICAL

X5R-CERM

402

0.022UF

CERM-X5R16V10%

PLACE_NEAR=C1763.2:3mm

SM

20%2VTANTCASE-B2-SM

270UF

11VPOLY

CRITICAL

CASE-B

20%

62UF

5%0

201MF

1/20W

UTQFN

CRITICAL

ISL95870AH

12

201

20K

MF

1%1/20W

201

1/20WMF

49.9K1%

201

511K1/20WMF

1%

201

1%1/20WMF

56K

1/20W1%

MF201

1.62K

201

1.62K

1/20W

VCCSAS0_RTN_R

1%

MF

5%50V

0201COG

10PF

X5R-CERM0402

20%10V

2.2UF

201

1/20WMF

3.24K1%

201

1%1/20W

3.24K

MF5%

COG0201

10PF50V

CRITICAL

POWERPAK-6X3.7SIZ710DT CRITICAL

1.0UH-7.7A

FDV0630H-SM


System Agent Supply



VCCSAS0_SET1_R

VCCSAS0_SET1


MIN_LINE_WIDTH=0.2 mmVCCSAS0_SET0


VCCSAS0_CS_N

VCCSAS0_CS_P


DIDT=TRUE

VCCSAS0_LL

SWITCH_NODE=TRUEMIN_NECK_WIDTH=0.2 mm

DIDT=TRUE

VCCSAS0_BOOT_RCMIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.2 mm

=PP5V_S0_VCCSA

=PPVCCSA_S0_REG

VOLTAGE=1.05V

PPVCCSA_S0_REG_RMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mm

CPU_VCCSA_VID<1>

CPU_VCCSA_VID<0>


DIDT=TRUE

MIN_NECK_WIDTH=0.2 mmGATE_NODE=TRUE

VCCSAS0_DRVH

DIDT=TRUE

VCCSAS0_VBSTMIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.2 mm

DIDT=TRUE


GATE_NODE=TRUE

VCCSAS0_DRVL

=PVCCSA_EN

VCCSAS0_FSELMIN_NECK_WIDTH=0.1 mmMIN_LINE_WIDTH=0.2 mm

=PPVIN_S0_VCCSAS0

CPU_VCCSASENSEMIN_LINE_WIDTH=0.2 mmMIN_NECK_WIDTH=0.1 mm

MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mmPP5V_S0_VCCSAS0_VCC

VOLTAGE=5V

VCCSAS0_SREFMIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm


CPU_VCCSASENSE_R


VCCSAS0_RTNMIN_LINE_WIDTH=0.2 mm

PVCCSA_PGOOD


VCCSAS0_AGNDMIN_LINE_WIDTH=0.6 mm

VOLTAGE=0V

VCCSAS0_OCSET


VCCSAS0_VO


C7103 1

2

R71031

2

C71021

2

XW7100

1 2

R7101 1

2

C71011

2

R71301

2

C71301

2

C7140

12

R71411

2

R71421

2

C7122 1

2

R7140

1 2

3 4

C7120 1

2

C7121 1

2

C7119 1

2

XW7101

1

2

C71411

2

C7123 1

2

U7100

1815

10

13

3

1

11

2

14

16

20

4

8

9

7

17

19

6

5

12

R71471

2

R71481

2

R71491

2

R71501 2

R71511 2

R71531 2

C71051

2

R71521

2

R71541

2

C71061

2

Q7100

1

6

4 5

2 3 7

8

L7100

1 2

051-9276

2.7.0

71 OF 109

53 OF 72

6

6

6

44 71

44 71

7

7

7

6

OUT

IN IN

EN

EN2EN1

DRVL2

SKIPSEL1

SKIPSEL2

DRVL1

V5SW

VBST2VBST1

VREG5

VREF2

VIN

THRM_PAD

SW2SW1

RF

PGOOD2PGOOD1

GND

DRVH2DRVH1

CSP2

CSN2CSN1

COMP2COMP1

VREG3

VFB1 VFB2

OCSEL

MODE

CSP1

OUT

IN

Apple Inc.


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6 3



F=400KHZ

F=400KHZ

Vout = 3.3V

6.5A MAX OUTPUT7.2A MAX OUTPUT

Vout = 5.0V

353S2678

152S1424

402

16V

X5R

10%1UF

CRITICAL

2.5UH-14A

PCMC063T-SM

10%

402

16VX5R

1UF

10%

25V

X5R

402

0.1UF0.1UF10%

402

25V

X5R

CASE-B2-SM

CRITICAL

6.3V

150UF

POLY-TANT

20%

402

16V

1UF10%

X5R

201

MF

1%

1/20W

249K

61

PLACE_NEAR=L7260.2:3mm

SM

0.22UF

CERM

10%

402

10V

23.2K

MF1/20W

201

1%

MF

1/20W

201

10K1%

1/20W

201MF

41.2K1%

1%1/20W

MF201

10K

SM


201

6.65K1%1/20WMF

1/20W

201MF

1.54K

1%


SM

X5R

10%

0.1UF

16V

402

1%

1.33K

MF1/20W

201

MF1/20W

4.22K

201

1%


SM


SM

7.5K

MF

1/20W

1%

201

NO STUFF

1/20W

1%

MF

20K

201


SM

SM


CASE-B2-SM

6.3V

CRITICAL

20%

TANT

150UF-0.018OHM-1.8A

NO STUFF

1/20W

20K

MF

201

1%

25VX7R-CERM

10%

201

220PF

201

MF

1%

7.5K

1/20W

10%10VX7R

4700PF

201

61 61

1/20W

MF

201

0

5%

NO STUFF

5%

MF

1/20W

201

0


1000PF

201

16V10%

X7R

16VX7R

10%1000PF

201


201X7R

10%1000PF

16V


1000PF

PLACE_NEAR=L7220.1.2:1.5mm

10%16V

201X7R

TPS51980

CRITICAL

QFNMF-LF402

1/16W5%0


201MF1/20W5%0

201

1/20WMF

0


5%

61

61

10%10V

4700PF

X7R

201

10%

X7R-CERM16V

270PF

0201

402

0.1UF

16VX5R

10%

1/16W

402MF-LF

5%0

CRITICAL

ELECCASE-B2S

6.3V

20%

62UF

150UF

CRITICAL

POLY-TANT

20%6.3V

CASE-B2-SM

CRITICAL

POWERPAK-6X3.7SIZ710DT

603X5R

10V20%10UF

603

X5R10V20%10UF

1.5UH-20%-18A-15MOHM

PCMC063T-SM

CRITICAL

10UF20%

10V

X5R

603

20%

62UF

11VPOLY

CRITICAL

CASE-B

11V

20%

CASE-BPOLY

62UF

CRITICAL

POLY

CRITICAL

20%

62UF

CASE-B

11V

62UF20%

CRITICAL

POLY11V

CASE-B

CRITICAL

SIZ710DTPOWERPAK-6X3.7

05%

1/20W

201MF

SKIP_5V3V3:AUDIBLE

MF1/20W

5%

0

201

SKIP_5V3V3:INAUDIBLE

2.2UF20%

10V

X5R-CERM

402


5V / 3.3V Power Supply

=PPVIN_S5_P5VP3V3

=PP5V_S5_LDO

P5VP3V3_VREF2

MIN_LINE_WIDTH=0.6 mmDIDT=TRUEGATE_NODE=TRUEMIN_NECK_WIDTH=0.2 mm

P3V3S5_DRVH


P5VS3_VBST_R

DIDT=TRUE

MIN_LINE_WIDTH=0.6 mmGND_P5VP3V3_SGND

VOLTAGE=0VMIN_NECK_WIDTH=0.2 mm

P5VS3_PGOOD


SWITCH_NODE=TRUEDIDT=TRUEP5VS3_LL

P3V3S5_CSN2



P3V3S5_CSP2_RMIN_LINE_WIDTH=0.2 mm


P3V3S5_VFB2

P3V3S5_COMP2MIN_LINE_WIDTH=0.2 mmMIN_NECK_WIDTH=0.1 mm

P5VS3_VFB1


P5VP3V3_VREF2


P5VS3_DRVHGATE_NODE=TRUEDIDT=TRUE

MIN_LINE_WIDTH=0.2 mmP5VP3V3_VREG3


GATE_NODE=TRUEP3V3S5_DRVL

MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mmDIDT=TRUE

MIN_NECK_WIDTH=0.2 mmDIDT=TRUE MIN_LINE_WIDTH=0.6 mm

P3V3S5_LLSWITCH_NODE=TRUE


DIDT=TRUEP3V3S5_VBST

DIDT=TRUEMIN_NECK_WIDTH=0.2 mm

P3V3S5_VBST_RMIN_LINE_WIDTH=0.6 mm

P5VP3V3_SKIPSEL

=PP5V_S3_REG

P3V3S5_PGOOD

P3V3S5_EN_R

MIN_NECK_WIDTH=0.1 mmMIN_LINE_WIDTH=0.2 mmP5VS3_CSP1_R

=PP5V_S3_REG

P5VS3_CSP1MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mm

P5VS3_DRVLDIDT=TRUE GATE_NODE=TRUE


DIDT=TRUEP5VS3_VBST

P3V3S5_RFP5VS3_FUNC

P5VS3_COMP1_R

P5VP3V3_VREF2

P3V3S5_COMP2_R


P5VS3_COMP1

=P5V3V3_REG_EN=PP3V3_S5_REG

MIN_LINE_WIDTH=0.2 mmP3V3S5_VFB2_R


P5VP3V3_VREG3


P5VS3_VFB1-R

=P5VS3_EN =P3V3S5_EN

P5VS3_EN_R

P5VS3_CSN1


P3V3S5_CSP2

C7200 1

2

L7260

1 2

C72411

2

C7264 1

2

C72241

2

C72521

2

C72811

2

R72061

2

XW7261

1

2

C7201 1

2

R72601

2

R72611

2

R72201

2

R72211

2

XW7200

1 2

R72161

2

R72461 2

XW7260

1

2

C7218

1 2

R72471 2

R72561

2

XW7220

1

2

XW7221

1

2

R72361

2

R72371

2

XW7262

1

2

XW7222

1

2

C72921

2

R72391

2

C7239 1

2

R72381

2

C7238 1

2

R72481 2

R72491

2

C72721

2

C72831

2

C72701

2

C72711

2

U7201

10 15

8 17

7 18

1 24

30 27

12

4 21

28

11

14

5 20

3

6

19

32 25

33

2

31 26

9 16

23

13

22

29

R72451

2

R72511

2

R72521

2

C7236 1

2

C7237 1

2

C7288

1 2

R72642

1

C72541

2

C72531

2

Q7260

1

6

4 5

2 3 7

8

C72901

2

C7250 1

2

L7220

1 2

C72051

2

C72421

2

C72401

2

C72841

2

C72821

2

Q7220

1

6

45

237

8

R72001

2

R72011

2

C7203 1

2

54 OF 72

72 OF 109

2.7.0

051-9276

7

7

54

54

54

7 54

7 54

54

7

54

D

G S

IN

IN

V5IN

REFIN

S5

VREF

S3

MODE

TRIP

SW

DRVL

PGOOD

VDDQSNS

VTT

VTTSNS

VTTREF

DRVH

VBST

VLDOIN

THRMVTTGNDPGND PADGND

OUT

IN

OUT

OUT

G

D

S

G

D

S


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DSIZEDRAWING NUMBER

REVISION

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6 3



10mA max load

(DDRREG_DRVL)

If LVDDR3_HW:NO is turned ON, switch R2821 & R7971 back to the original value for 1.5V DDR unless 1V5R1V35_SW is turned ON

C7360, C7361 close to memory

f = 400 kHz

Vout = 1.5V

VDDQ/VTTREF Enable

VTT Enable

(DDRREG_LL)

(DDRREG_DRVH)

(DDRREG_VDDQSNS)

(Q7335 limit)

14.1A max output

1V5R1V35_SW

VESM

CRITICAL

SSM3K15AMFVAPE

17

CRITICAL

20%

X5R

10UF


603

6.3V

10UF

X5R

20%

603

10V


1UF10%

603-1X5R

25V

0.1UF

10%25VX5R

402

10%50V

X7R

0.001UF

402

10UF

6.3V

20%

X5R603

402

0.001UF

50V10%

X7R


SM

61

CRITICAL

TPS51916

QFN

8

SM


SM


10%10V

402

0.22UF

CERM

10UF

X5R

20%6.3V

603


CRITICAL

8 26


10%16VX5R

0.1UF

402

CRITICAL

20%6.3V

X5R603

10UF


1%

200K


201

1/20W

MF

MF

1%

201


20K

1/20W

1/20W

MF

100K1%

201

LVDDR3_HW:NO


10%16VCERM

402

0.01UF


X5R

10UF

603

20%10V


5%

402

0 1/16W

MF-LF

0.88UH-20%-19A-2.3MOHM

MPCG1040LR88-SM

CRITICALCRITICAL

1206

0.0010.5WMF1%

45 71

45 71

PQFN3.3X3.3IRFHM831PBF

CRITICAL

IRFHM830DPBF

CRITICAL

PQFN3.3X3.3

MF

1%

201

1/20W

84.5K


CASE-B2-SM1

2.0V20%

330UF

CRITICAL

POLY-TANT

CASE-B2-SM1POLY-TANT

2.0V20%

330UF

CRITICAL

CASE-B

62UF20%11VPOLY

CRITICAL

CASE-B

20%

CRITICAL

POLY11V

62UF

CASE-B

62UF20%11VPOLY

CRITICAL

201

1/20W

MF

1%

150K


1V5R1V35_SW


1.5V DDR3 Supply

1118S0460 R7316 LVDDR3_HW:YESRES,MF,60.4KOHM,1,1/20W,0201

ISNS_1V5_S3_P



DDRREG_VDDQSNS

ISNS_1V5_S3_N

=PPDDR_S3_REG



VOLTAGE=1.5V

PPDDR_S3_REG_R

DDRREG_LL

DIDT=TRUESWITCH_NODE=TRUE



=DDRREG_EN

=PPVIN_S0_DDRREG_LDO

=DDRVTT_EN

MEM_VDD_SEL_1V5_L

DDRREG_P1V35_L

=PPVIN_S3_DDRREG

DDRREG_MODE



DDRREG_FB

DDRREG_1V8_VREF



=PP5V_S3_DDRREG

DDRREG_TRIP


GND_DDRREG_SGND


VOLTAGE=0V



DDRREG_VBST

DIDT=TRUE

DDRREG_PGOOD

=PPVTT_S3_DDR_BUF

DIDT=TRUE



DDRREG_VBST_RC



GATE_NODE=TRUE DIDT=TRUE

DDRREG_DRVH



DDRREG_DRVL

GATE_NODE=TRUE DIDT=TRUE

DDRREG_VTTSNS



=PPVTT_S0_DDR_LDO

C7300 1

2

C73321

2

C7325

1 2

C73331

2

C73451

2

C7346 1

2

XW7301

1

2

U730014

11

7

19

10

20

8

17

16

13

21

18

12 15

9

2

6

3

4

5

1

XW7360

1 2

XW7300

1

2 C7350 1

2

C7360 1

2

C7315 1

2

C73611

2

R73171

2

R73151

2

R73161

2

C73161

2

C7301 1

2

R7325

1 2

L7330

1 2

R7350

1 2

3 4

Q7330

5

4

1 2 3

Q7335

5

4

1 2 3R73181

2

C73401

2

C7341 1

2

C73301

2

C73311

2

C73341

2

R73141

2

Q73193

12

C73621

2

051-9276

2.7.0

73 OF 109

55 OF 72

7

7

7

31

7

7 31

7

IN

IN

IN

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

OUT

NC

OUT

NCNCNCNC

PAD

IMAXA

SR

IMAXB

ALERT*

THERMA

THERMB

VDIO

POKB

CLK

EN

POKA

CSPA3

DRVPWMA

GNDSB

GNDSA

THRM

CSPB1

DHB

LXB

BSTB

DLA2

DLB

CSNB

FBB

LXA1

DHA1

BSTA1

TON

DLA1

CSPA1

CSPAAVE

FBA

CSNA

BSTA2

CSPA2

DHA2

LXA2

VCC

VDDA

VDDB

VR_HOT*

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1/16WMF-LF

5%

10

402

2.2UF

X5R-CERM402

10V20%

402

10V20%2.2UF

X5R-CERM


12 65

12 65

12 65

100PF

201

25V5%

CERM

NO STUFF

MF

5%

201

1/20W

300

1

5%

MF1/20W

201

0402X5R-CERM

NO STUFF

10%10V

0.039UF25

61

61

10 40 41 65

57

57

57

57

57 71

57

57

57

57

57 71

SM

402

2.2UF20%10VX5R-CERM


1%200K

1/20W

NO STUFF

MF201

25V5%100PF

CERM

NO STUFF

201

201

1/20WMF

5%

10

201

10

1/20W5%

MF

12 65

12 65

16V

1000PF10%

X7R201

201

16VX7R

10%1000PF

1000PF

16V10%

X7R201

5%

MF

10

201

1/20W

12 65

12 65

201

10%

X7R16V

1000PF

201

1/20WMF

10

5%

44 57 71

201

5%25VCERM

100PF

NO STUFF

201

5%25VCERM

100PF

NO STUFF57 71

201

10V10%

NO STUFF

X5R

0.01UF


MF

1%54.9

201

1/20W


1/20W

201MF

1%130

57 71

MF1/20W

201

215K1%

137K

201

1%

MF1/20W

1%

MF-LF

90.9K

1/16W

402

5.76K1%1/20WMF201

5.76K1%

MF1/20W

201

10%0.0022UF

CERM50V

402

10%2200PF10VX7R-CERM0201

100KOHM-1%-100MW


CRITICAL

0603

CRITICAL


0603

100KOHM-1%-100MW

470PF

402

5%50V

NP0-C0G

10VX5R

10%

201

0.01UF

NO STUFF

1/20W

201

1%

MF

215K

1/20W

201

137K

MF

1%1/20W

201

10K1%

MF

1%1/20WMF201

6.34K

NP0-C0G

NO STUFF

201

25V5%47PF

2.2MF-LF4025% 1/16W

MF1/20W1%

8.25K

201

TQFN

CRITICAL

MAX15120

5%

100PF

CERM25V

201

NO STUFF

5%

100PF

CERM25V

201NO STUFF


CPU IMVP7 & AXG VCore Regulator

P5V_S0_CPUIMVP_VDD

VOLTAGE=5V


CPU_VIDALERT_L

CPUIMVP_NTC


CPUIMVP_ISUM_R


CPUIMVP_ISUM_NCPUIMVP_ISUM

CPUIMVP_UGATE1

CPU_AXG_SENSE_R


CPU_PROCHOT_L

CPUIMVP_NTCG


CPU_VIDSCLKCPU_VIDSOUT

GND_CPUIMVP_SGNDMIN_NECK_WIDTH=0.2 mmVOLTAGE=0V


CPUIMVP_IMAXA

CPUIMVP_ISUMG_N

CPUIMVP_ISUM_P

CPUIMVP_FBAMIN_LINE_WIDTH=0.2 mmMIN_NECK_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

CPUIMVP_FBA_RMIN_LINE_WIDTH=0.2 mm


CPUIMVP_FBB_R CPU_AXG_SENSE_P

CPUIMVP_VR_ON

CPUIMVP_PGOODCPUIMVP_AXG_PGOOD

CPU_VCCSENSE_N

CPU_AXG_SENSE_N

CPUIMVP_FBA

CPUIMVP_LGATE1

CPUIMVP_TON

CPUIMVP_BOOT1CPUIMVP_UGATE1_RCPUIMVP_PHASE1

CPUIMVP_FBB

CPUIMVP_LGATE1G

CPUIMVP_BOOT1G

CPUIMVP_PHASE1GCPUIMVP_UGATE1G


CPUIMVP_FBB

CPU_VCCSENSE_P

CPUIMVP_ISNS1_P

CPUIMVP_SLEW

CPUIMVP_IMAXB

=PPVCCIO_S0_CPUIMVP


CPU_VCCSENSE_R

CPUIMVP_ISUMG_P

=PP5V_S0_CPUIMVP

=PPVIN_S0_CPUIMVP

R74011 2

C7401 1

2

C74021

2

C74141

2

R74061 2

R74101 2

C7408

1 2

XW7400

12

C74031

2

R74641

2

C74151

2

R74401 2

R74411 2

C74401

2

C74411

2

C74121

2

R74131 2

C7422 1

2

R74231 2

C74191

2

C74181

2

C74421

2

R74791

2

R74801

2

R74601

2

R74611

2

R74021 2

R74681

2

R74661

2

C74071

2

C74041

2

R7469

1

2

R7467

1

2

C74091 2

C74431

2

R74621

2

R74631

2

R74651

2

R74121 2

C74441

2

R74031 2

R74221 2

U7400

17

20

28

11

18

37

9

36

38

39

35

8

22

26

13

23

25

14

31

1

4

6

3 7

29

30

21

27

12

19

10

32

33

34

41

2

40

24

15

16

5

C74521 2

C74621 2

051-9276

2.7.0

74 OF 109

56 OF 72

56

56

56

56

7

7

7 57

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

S

G

D

D

G

SNCNC

VSW

PGND

TGR

TG

BG

VIN

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6 3



152S1323

152S1323

PHASE 1

THESE TWO CAPS ARE FOR EMC

AXG PHASE

376S0985

376S0984

THESE TWO CAPS ARE FOR EMC

376S1005

CPU=IV Bridge ULV, AXG=GT2

PIMB104T-SM

CRITICAL

0.36UH-20%-30A-1.2MOHM

10UF20%25V

0603X5R-CERM

CRITICAL

16V

402

1UF10%

X5R50V

402

10%0.001UF

X7R

0.001UF10%50VX7R402

56

56

56

56

402

MF-LF

5%

0

1/16W

0.22UF

402

10VCERM

10%

0.001UF10%50VX7R402

X7R402

10%50V

0.001UF10%

402

16VX5R

1UF

2.2

NOSTUFF

1/10W5%

603

MF-LF

0.001UF

402

10%

CERM50V

NOSTUFF

0.22UF

10V

CERM

10%

402

56

56

56

56

MF

101%1/20W

201

MF

101%

201

1/20W

56 71

56 71

56 71

56 71

44 56 71

5%

1/16W

402

MF-LF

4.7

CRITICAL

1W1%

0612MF

0.00075

0.000751%1WMF0612

CRITICAL

46.41%

201MF

1/20W

1/20W1%

MF

46.4

201

10%10V

2200PF

0201

NO STUFF

X7R-CERM

NO STUFF

X7R

10%16V

1000PF

201

11V

20%

POLY

CRITICAL

62UF

CASE-B

62UF20%

11V

CRITICAL

POLY

CASE-B

CRITICAL

POLY11V

20%

62UF

CASE-B

CRITICAL

POLY11V

20%

62UF

CASE-B

POLY

CRITICAL

11V20%

62UF

CASE-B

20%11VPOLY

CRITICAL

62UF

CASE-B

20%

CRITICAL

62UF

11VPOLY

CASE-B

CRITICAL

PIMB104T-SM

0.36UH-20%-30A-1.2MOHM

CRITICAL

IRF6811STRPBFSQ

20%

62UF

CRITICAL

POLY11V

CASE-B

CRITICAL

11V

20%

62UF

POLY

CASE-B0603

CRITICAL

25V20%10UF

X5R-CERM

20%

CRITICAL

10UF

25VX5R-CERM0603

10UF20%

X5R-CERM0603

CRITICAL

25V

IRF6894MTRPBFDIRECTFET-MX

CRITICAL

105%

1/16W

MF-LF

402

CSD58872Q5DSON5X6

CRITICAL

CPU IMVP7 & AXG VCore Output


=PPVIN_S0_CPUAXG

PPVCORE_S0_AXG_R


VOLTAGE=1.05V

=PPVIN_S0_CPUIMVP

DIDT=TRUE

SWITCH_NODE=TRUE


CPUIMVP_VSWG

SWITCH_NODE=TRUE

CPUIMVP_PHASE1GDIDT=TRUE


GATE_NODE=TRUEDIDT=TRUE

CPUIMVP_UGATE1G_R





CPUIMVP_LGATE1G




CPUIMVP_UGATE1MIN_LINE_WIDTH=0.5 MM


DIDT=TRUE

SWITCH_NODE=TRUE

CPUIMVP_PHASE1MIN_LINE_WIDTH=0.5 MM

=PPVCORE_S0_AXG_REG

CPUIMVP_ISNS1G_P CPUIMVP_ISNS1G_N

CPUIMVP_ISUMG_P

=PPVCORE_S0_CPU_REG

CPUIMVP_AXG_SNUB

DIDT=TRUEMIN_LINE_WIDTH=0.4 MMMIN_NECK_WIDTH=0.2 MM

VOLTAGE=1.25V


CPUIMVP_UGATE1G



DIDT=TRUE

CPUIMVP_BOOT1G_RCMIN_LINE_WIDTH=0.5 MMMIN_NECK_WIDTH=0.2 MM

DIDT=TRUEMIN_NECK_WIDTH=0.2 MM

CPUIMVP_BOOT1GMIN_LINE_WIDTH=0.5 MM

DIDT=TRUEMIN_NECK_WIDTH=0.2 MM

CPUIMVP_BOOT1MIN_LINE_WIDTH=0.5 MM

CPUIMVP_ISNS1_N

DIDT=TRUEGATE_NODE=TRUE

CPUIMVP_LGATE1


CPUIMVP_ISUM_P

CPUIMVP_ISUM_N

CPUIMVP_BOOT1_RC

DIDT=TRUE


CPUIMVP_ISUMG_N

CPUIMVP_ISNS1_P

VOLTAGE=1.25V


PPVCORE_S0_CPU_PH1


L7510

1 2

C75151

2

C75171

2

C75181

2

C75191

2

R75111

2

C75111

2

C75591

2

C75581

2

C75571

2

R75521

2

C75521

2

C7551 1

2

R75141

2

R75541

2

R7555

1 2

R7510

1 2

3 4

R7550

1 2

3 4

R75531

2

R75131

2

C75711

2

C75741

2

C75131

2

C75141

2

C75401

2

C75411

2

C75601

2

C75531

2

C75541

2

L7550

1 2

Q7510

1

2

5

64

3

C75101

2

C75201

2

C75161

2

C75551

2

C75561

2

Q7520

1 2 6 7

5

3 4

R75511

2

Q7550

5

9

3

4

1

6

7

8

051-9276

2.7.0

75 OF 109

57 OF 72

7

7 56

7

44 71 44 71

7

44 71

OUT

IN BOOT

UGATE

LGATE

PHASE

RTN

FSEL

PGOOD

OCSET

VO

SREF

VCC PVCC

GND PGND

EN

FB VSW

PGND

TGR

TG

BG

VIN

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(CPUVCCIOS0_VO)

(CPUVCCIOS0_OCSET)

OCP = 25.6A

<Rb>

<Ra>

CPU VCCIO (1.05V S0) Regulator

21A Max Output

Vout = 1.05V

f = 300 kHz

OCP = R7641 x 8.5uA / R7640

Vout = 0.5V * (1 + Ra / Rb)

1/20WMF

1%3.01K

201

61

61

2.2UF10%

X5R16V

603

1/20W

0

MF

5%

201


SM

UTQFN

ISL95870

CRITICAL

CRITICAL

10UF20%

X5R10V

603

X5R402

16V10%1UF

3.01K1%1/20WMF201

3.01K1%

MF1/20W

201

402

5%

NP0-C0G25V

1000PF


1000PF5%

NP0-C0G402

25V

5%


25V

1000PF

402NP0-C0G

NP0-C0G

47PF5%

25V

201

05%

603

1/10W

MF-LF

5%

402

MF-LF1/16W

0

270UF20%

2VTANT

CRITICAL

CASE-B2-SM

47PF5%25V

201NP0-C0G

20%

CRITICAL

CASE-B2-SMTANT

2V

270UF

201

5%

MF

2.2

1/20W

CRITICAL

0.68UH-22A-2.7MOHM

PIMB104T-SM

0612MF1W1%

0.001

CRITICAL

POLY11V20%

62UF

CASE-B

CRITICAL

62UF20%11VPOLY

CRITICAL

CASE-B

62UF20%11VPOLY

CASE-B

CRITICAL

10%

402

16VX7R

0.047UF

SON5X6

CRITICAL

CSD58872Q5D

2.74K

MF1/20W

201

1%

201

1/20WMF

2.74K1%

1%3.01K

MF1/20W

201


CPU VCCIO (1.05V) Power Supply

CPUVCCIOS0_RTNMIN_LINE_WIDTH=0.2 mmMIN_NECK_WIDTH=0.2 mm


CPUVCCIOS0_VO

CPUVCCIOS0_OCSET


MIN_LINE_WIDTH=0.6 mmCPUVCCIOS0_AGND

MIN_NECK_WIDTH=0.15 mmVOLTAGE=0V


CPUVCCIOS0_FB

CPUVCCIOS0_SREF

=PPVIN_S0_CPUVCCIOS0

CPUVCCIOS0_BOOT_RCMIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.2 mmDIDT=TRUE

MIN_NECK_WIDTH=0.2 mmDIDT=TRUE

MIN_LINE_WIDTH=0.5 mmCPUVCCIOS0_VBST

=PP5V_S0_CPUVCCIOS0

PP5V_S0_CPUVCCIOS0_VCC

VOLTAGE=5V


=CPUVCCIOS0_EN


MIN_LINE_WIDTH=0.6 mmPPCPUVCCIO_S0_REG_R

CPUVCCIOS0_CS_N

CPUVCCIOS0_PGOOD

CPU_VCCIOSENSE_P

CPUVCCIOS0_FSEL

=PPCPUVCCIO_S0_REG

CPUVCCIOS0_DRVH

DIDT=TRUE


GATE_NODE=TRUEMIN_NECK_WIDTH=0.2 mm

CPU_VCCIOSENSE_N

CPUVCCIOS0_CS_P


GATE_NODE=TRUE

CPUVCCIOS0_DRVL

DIDT=TRUE

CPUVCCIOS0_R

DIDT=TRUE


CPUVCCIOS0_LLMIN_LINE_WIDTH=0.6 mm

SWITCH_NODE=TRUE VOLTAGE=1.05V

PPCPUVCCIO_S0_REG



C7604 1

2

C76051

2

C76031

2

R76451

2

R76051

2

R76041

2

R76441

2

C7602 1

2

R76031

2

XW7600

1 2

U7600

123

6

5

1

15

7

16

9

10

14

2

4

11

13

8

C76011

2 C76301

2

R76421

2

R76411

2C7640

12

C7623 1

2

C7622 1

2

R76301

2

R7631

1 2

C76481

2

C76491

2

R76011

2

L7630

1 2

R7640

12

34

C76191

2

C76201

2

C76211

2

Q7630

5

9

3

4

1

6

7

8

051-9276

2.7.0

76 OF 109

58 OF 72

7

7

44 71

12 65

7

12 65

44 71

IN

BIAS

NC

OUT

THRM

EN

PADGND

NC

NC

IN

BIAS

NC

OUT

THRM

EN

PADGND

NCNCNC

LXVDD

VIN

THRM_PAD

PGND

SGND

EN

PG

SYNCH

LX

VFB

NC

IN

OUT

NC

IN

BIAS

NC

OUT

THRM

EN

PADGND

IN

IN

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6 3



Cougar Point requires JTAG pull-ups to be powered at 1.05V when SUS suspend well is active.

1.05V SUS LDOPull-ups (3) must be 51 ohms to support XDP (not required in production).

70mA is required to support pull-ups. Alternative is strong voltage

Max Current = 0.020A

Vout = 1.05V

Freq = 1 MHz

1.5V S0 LDO

Max Current = 0.02A Max Current = 0.35A

Vout = 1.05V

<Ra>

152S1302

1.8V S0 Regulator

dividers (200/100) to 3.3V S5, which burns 100mW in all S-states.

1.05V S0 LDO

<Rb>

Vout = 0.8V * (1 + Ra / Rb)

Vout = 1.794V

Max Current = 1.8A

Vout = 1.5V

XDP_PCH

10%6.3VCERM402

1UF

XDP_PCH

TPS720105

CRITICAL

SON

10%6.3V

2.2UF

402X5R

XDP_PCH

X5R402

6.3V10%2.2UF

CRITICAL

TPS720105

SON

6.3VCERM402

1UF10%


1UF

402CERM6.3V10%


603X5R-CERM-16.3V20%

CRITICAL

22UF

603X5R-CERM-1

CRITICAL

20%6.3V

22UF

201NP0-C0G25V

47PF5%

1%113K

MF1/20W

201

PIMB042T-SM

1.0UH-20%-4.5A-24MOHM

CRITICAL

603X5R-CERM-1

20%22UF

CRITICAL

6.3V

CRITICAL

ISL8014AQFN

16VX7R

1000PF10%

201

61

61

1%90.9K

MF1/20W

201

402X5R6.3V10%2.2UF

CRITICAL

TPS72015

SON


402

6.3VCERM

1UF10%


402

1UF

CERM6.3V10%

7

61

Misc Power Supplies


=PP3V3_S0_P1V8S0

P1V8S0_PGOOD

=PP3V3_SUS_P1V05SUSLDO

=PP1V8_S0_REG

=P1V8S0_ENSWITCH_NODE=TRUEDIDT=TRUE

P1V8S0_SW

=1V05_S0_LDO_EN



=PP1V05_S0_LDO

=PP3V3_S0_P1V5S0

=PP1V8_S0_P1V5S0

=P1V5S0_EN

=PP1V5_S0_REG

P1V8S0_FB

=PP1V05_SUS_LDO

C7740 1

2

U7740

4

3

5

6 1

7

C77411

2

C77811

2

U7780

4

3

5

6 1

7

C7780 1

2

C7782 1

2

C77211

2

C7722 1

2

C77231

2R77201

2

L7720

1 2

C7720 1

2

U7720

5 14

15

6

16

13

7

11

129

10

4

17

3

8

1 2C7724 1

2

R77211

2

C77721

2

U7770

4

3

5

6 1

7C7771 1

2

C7770 1

2

051-9276

2.7.0

77 OF 109

59 OF 72

2

22

7

7

7

61

7

7

7

7 7

7

IN

IN

IN

D

SG

D

SG

IN

THRMGND

G

PG

SHDN*

D

VCC

S

ON

PAD

OUT

IN

IN

D

SG

D

SG

D

SG

DS

G

DS

G

DS

G

DS

G

S

D

G

G

S D

DS

G

IN

D

G S

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6 3



3.3V S4 FET

3.3V S4 FET

CHANNEL

3.3V S3 FET

31 mOhm @1.8V

MOSFET

0.7? A (EDP)

RDS(ON)

LOADING

SiA427

P-TYPE 8V/5V

P-TYPE 8V/5V

31 mOhm @1.8V

3.3V S3 FET

1.608 A (EDP)

SiA427MOSFET

LOADING

RDS(ON)

CHANNEL

11-16 mOHM @4.5V

DMP2018LFK

5.0V S0 FET

RDS(ON)

CHANNEL

MOSFET

5V_SUS FET

PQFN2X2

9.4 mOhm @4.5V

N-TYPE

1.5V S3/S0 FET

MOSFET

LOADING

CHANNEL

5 A (EDP)

P-TYPE

MOSFET

CHANNEL

LOADING 1.678 A (EDP)

RDS(ON)

RDS(ON)

100? mA (EDP)

MOSFET

26 mOhm @1.8V

P-TYPE 8V/5V

5.0V S0 FET

RDS(ON)

LOADING

P-TYPE 12V/8V

CHANNEL

3.3V SUS FET

3.2 A (EDP)

26 mOhm @1.8V

P-TYPE 8V/5VCHANNEL

LOADING

MOSFET

3.3V S0 FET

SiA427

APN 376S0981

SiA427

RDS(ON)

1.5V S3/S0 FET

3.3V S0 FET

3.3V_SUS FET

100? mA (EDP)LOADING

29 mOhm @4.5V

SiA427

5V SUS FET

26

0.01UF

10%10VX5R201

X5R

0.033UF

16V10%

402

5%

47K

1/20W

201MF

201

10%10VX5R

0.01UF

402

10%0.033UF

16VX5R

61

37 61

SOT563

SSM6N37FEAPE

SSM6N37FEAPESOT563

61

10K

MF

1/20W

5%

201

0.033UF10%

X5R

402

16V

0.01UF

16V

CERM

402

10%

SLG5AP020

CRITICALTDFN

402CERM10V

0.1UF20%

MF-LF

5%

0

402

1/16W

603

6.3VX5R-CERM

10%4.7UF

NO STUFF

8

60 61

60 61

SSM6N37FEAPESOT563

0.033UF

X5R16V10%

402

0.033UF

X5R402

16V10%

402CERM16V10%

0.01UF

201

10V10%

X5R

0.01UF

SSM6N37FEAPESOT563

SSM6N37FEAPESOT563

100K

2011/20WMF5%

1/20W

12K

MF5%

201

201

5%1/20WMF

3.3K

MF

220K5%1/20W201

CRITICAL

SIA427DJSC70-6L

SIA427DJ

CRITICAL

SC70-6L

SIA427DJ

CRITICAL

SC70-6L

1/20WMF

91K

201

5%

1/20W

201

5%

MF

10K

1/20W

201

5%

MF

220K

100KMF1/20W5%

201

SIA413DJ

CRITICAL

SC70-6L

PQFN2X2IRLHS6242TRPBF

CRITICAL

1/10W

603MF-LF

0

5%

CRITICAL

CRITICAL

1/16W

0

5%

402MF-LF

CRITICAL

402

5%1/16WMF-LF

0

0.001

1W1%

0612MF-1

CRITICAL

1206

1/4W5%

MF-LF

0

CRITICAL

DMP2018LFK

CRITICAL

DFN2563-6

SC70-6L

SIA427DJ

CRITICAL

0.01UF

10%16VCERM402

16VX5R402

0.033UF10%

402

5%1/16WMF-LF

47K

402MF-LF

220K5%1/16W

61

0

1/16WMF-LF

5%

402

NO STUFF

0

1/16WMF-LF

5%

402

CRITICAL

SSM3K15AMFVAPE

VESM

Power FETsSYNC_MASTER=K21_MLB SYNC_DATE=12/13/2010

=P3V3S4_EN

P3V3S4_EN_L

=PP3V3_S4_P3V3S4FET

=PP1V5_S3_P1V5S3RS0_FET

=PP3V3_SUS_FET

ISNS_3V3S0_P

PP1V5_S3RS0_FET_RVOLTAGE=1.5V


=PP1V5_S3RS0_FET

P3V3S0_SS

=PP3V3_S5_P3V3SUSFET

ISNS_3V3S0_N

=PP3V3_S0_FET

MIN_LINE_WIDTH=0.5 MMMIN_NECK_WIDTH=0.20MM

VOLTAGE=3.3VPP3V3_S0_FET_R

P5V0S0_EN_L

=PP5V_SUS_FET

MIN_NECK_WIDTH=0.20MMMIN_LINE_WIDTH=0.50MMVOLTAGE=3.3VPP3V3_SUS_FET_R

=PP5V_S0_FET=PP5V_S5_P1V5DDRFET

P5VSUS_SS

P3V3SUS_SS

=P5VS0_EN

=P3V3S0_EN

=P5V_3V3_SUS_ENP3V3SUS_EN_L

P5VSUS_EN_L

P1V5CPU_EN

P1V5S0FET_GATE P1V5S0FET_GATE_R

P1V5S3RS0_RAMP_DONE

=PP3V3_S0_P3V3S0FET

P3V3S0_EN_L

=PP5V_S5_P5VSUSFET

MIN_LINE_WIDTH=0.4 MMMIN_NECK_WIDTH=0.2 MMVOLTAGE=5VPP5V_S0_FET_R

P5V0S0_SS

=PP5V_S3_P5VS0FET

=P3V3S3_EN

P3V3S3_EN_L P3V3S3_SS

PP3V3_S3_FET_RVOLTAGE=3.3VMIN_LINE_WIDTH=0.50MMMIN_NECK_WIDTH=0.20MM

=PP3V3_S3_FET

=P5V_3V3_SUS_EN

=PP3V3_S3_P3V3S3FET

P3V3S4_SS

PP3V3_S4_FET_RVOLTAGE=3.3VMIN_LINE_WIDTH=0.50MMMIN_NECK_WIDTH=0.20MM

=PP3V3_S4_FET

C7810

1 2

C7811 1

2

R78101 2

C7830

1 2

C7831 1

2

Q7812 6

2 1

Q7812 3

5 4

R78601 2

C7861 1

2

C7860

1 2

U78015

7

4

2

8

6

3

9

1

C7801 1

2

R78011 2

C7802 1

2

Q7822 6

2 1

C7841 1

2

C7821 1

2

C78401 2

C78201 2

Q7822 3

5 4

Q7802 3

5 4

R78121

2

R78201 2

R78401 2

R78621

2

Q7830

1

3

47

Q7820

1

3

47

Q7810

1

3

47

R78301 2

R78321

2

R78421

2

R78221

2

Q7840

1

3

47

Q7801

1 2 5 6 8

3

4 7

R78111 2

R78211 2

R78411 2

R7831

1 2

3 4

R78501 2

Q7860

4

3

1

2

Q7800

1

3

47

C7800

1 2

C7809 1

2

R78001 2

R78021

2

R78031 2

R78041 2

Q78093

12

051-9276

2.7.0

78 OF 109

60 OF 72

7

7

7

44 71

7

7

44 71

7

7

7 7

7

7

7

7

7

7

G

D

SIN

IN

G

D

S

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

D

G S

IN

OUT

IN

IN

IN

INNC

NC

NC

Q3

Q2

Q4

Q1

SENSE

CT

VDD

GND

RESET*

MR*

IN

G

D

S

OUT

OUT

VDD

MR*

RST*V4MON

V3MON

V2MON

GND THRM_PAD

OUT

OUT

OUT

IN

VDD

OUT_A*

OUT_A

THRMGND

IN_A

DLY_1C

IN_B

OUT_BDLY (OD,IPU)

(OD,IPU)

(OD,IPU)(IPD)

1.3V

PAD

2:1

-

+

OUT

OUT

VCC

A

Y

GND

B

CIN

IN

OUT

IN

IN

G

D

SNC

NC

NC

NC

OUT

NC

NC

IN

IN

OUT

OUT

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6 3



DP S4 Power Enable

(PM_SLP_S3_R_L)

U7930 Sense input

Mobile System Power State Table

1

VFRQ High: Variable Frequency

CHGR VFRQ Generation

S0 ENABLE

threhold is 3.07V

Could stuff R7930 to satisfy PCH power down timing t235

PM_RSMRST_L goes to U1800.C21

3.3V SUS Detect

Min delay timeNo stuff C7931, 12ms

3.3V/5.0V Sus ENABLE

PP1V5_S3RS0

Q2: 0.XXXV

3.3V w/Divider: 2.345V

SMC_BATLOW_L:100K pull up on SMC page

NOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal.

CPUVCORE ENABLE

0

353S2310

toggle 3Hz

SMC_ADAPTER_ENInternal pull-ups 100K +/- 20%

Deep Sleep (S5AC)

Deep Sleep (S4)

Deep Sleep (S5)

Deep Sleep (S4AC)

State

Sleep (S3)

Sleep (S3AC)

Run (S0)

Battery Off (G3Hot)

Battery Off (G3HotAC)

1

0

0

1

1

0

0

0

1

01

0

0

1

0

00

0

0

0

00

0

0

0

0

0

0

0

0

0

0

0

00 01 011

1

1

SMC_S4_WAKESRC_EN

1

1

1

1

SMC_PM_G2_ENABLE

X

1

0

PM_SUS_EN

1

1

1

PM_SLP_S5_L

1

1

PM_SLP_S4_L

1

1

1 0

0

1

PM_SLP_S3_L

(ISL Version in development)

V4MON: 0.572V-0.630V

V2MON: 2.815V-3.099VV3MON: 0.572V-0.630V

S0 Rail PGOOD Circuitry

Worst-Case Thresholds:

SMC-->PM_DSW_PWRGD

S5_PWRGD (old name RSMRST_PWRGD)-->SMC

Unused fet

WLAN Enable Generation"WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0"))

(PM_SLP_S3_L)

VDD: 2.734V-3.010VThresholds:

353S2809

Q4: 0.660V

P1V5S0_PGOOD from U7710

(IPU)

(AC_EN_L)

(90K IPU)

3.3V,5V S3 ENABLE

343S0497

DLY > 10 msThreshold: ??

S5 Rail Enables & PGOOD

S0 Rail PGOOD (BJT Version)

Q3: 0.640V

PM_SLP_S5_L:100K pull down on PCH page

VFRQ Low: Fix Frequency

2N7002DW-X-GSOT-363

17 40 41

17 26 40 61

SOT-3632N7002DW-X-G

36

54

55

60


CERM-X5R

10%

402

0.47UF

6.3V

56

PLACE_NEAR=U7400.1:5mm1/20WMF

5%

201

0

60

37 60

44

58

59

53

201MF1/20W5%5.1K



0.47UF

402CERM-X5R6.3V10%

17 26 36 40

48


0.47UF10%

CERM-X5R402

6.3V

1/20W


201MF

5.1K5%


402CERM-X5R

0.47UF10%6.3V


CERM-X5R

0.47UF

6.3V10%

402


33K

201MF1/20W5%

201

1/20WMF

10K5%

52

SOD-VESM-HFSSM3K15FV

17 26 40 61

NO STUFF

5%0

MF1/20W

201

5%10K

MF201

1/20W

23 25 40 51 61

201

5%1001/20W

MF

5%

MF1/20W

100

201

5%1/20W

100

201MF

100

MF1/20W5%

201

59

54

5%

100

MF1/20W

201

5%

MF1/20W

330

201

S0PGOOD_ISL

58

53

201MF

1%150K1/20W

201

S0PGOOD_ISL

6.3VX5R

10%0.1UF

201

1/20WMF

15K1%

201

7.15K1/20WMF

1%DFN2015H4-8

CRITICAL

ASMCC0179

5%

1K

1/20WMF201

201

1/20W

1K

MF

5%

CRITICAL

TPS3808G33DBVRG4SOT23-6

NO STUFF

16VX7R

1000PF10%

201

201

1/20WMF

100K5%

6.3VX5R

0.1UF10%


201

5%

MF1/20W

NO STUFF

100

201

56

SOT-3632N7002DW-X-G

5%

100

MF1/20W

201

59

CERM-X5R


0.47UF

6.3V10%

402

17

ISL88042IRTEZ

CRITICALTDFN

S0PGOOD_ISL

1/20WMF

201

1%

S0PGOOD_ISL

15K

S0PGOOD_ISL

201

12.4K

MF1/20W

1%

15K

S0PGOOD_ISL

1%

MF1/20W

201

1%

MF

10K

1/20W

S0PGOOD_ISL

201 1/20W1%

MF

S0PGOOD_ISL

6.04K

201

201MF

1%

S0PGOOD_ISL

6.04K

1/20W

54

X5R402NO STUFF

10%0.033UF16V

1/20W

100

MF201

5%

40

201

10%6.3VX5R

0.1UF

40

TDFNSLG4AP012

CRITICAL

220PF

X7R-CERM201

10%25V

6 38 39

201

5%1/20WMF

0

NO STUFF

10V

402

10%0.068UF

CERM

59

20K


201

1/20WMF

5%

201

1/20WMF

NO STUFF

5%

0

SOT89174AUP1G3208

10%


X5R201

0.1UF6.3V

17

40 41

60

39K1/20W

201


MF

5%


201MF1/20W5%9.1K

MF

5%

100

1/20W

201

54

18 23 36

SOT-3632N7002DW-X-G

5%

1K

1/20WMF201

63

MF-LF

0

NOSTUFF

5%

1/16W

402

SOT89174LVC1G32

17 40 20%


0.1uF

402

CERM

10V

40 41

63

201MF1/20W5%0

NO STUFF

60


Power Control 1/ENABLE

=PP3V3_S5_PWRCTL

=PP3V3_S0_PWRCTL

PM_SLP_S5_L

PM_SLP_S3_L

PVCCSA_ENMAKE_BASE=TRUE

=PVCCSA_EN

=1V05_S0_LDO_EN

=CPUVCCIOS0_EN

P1V5S0_ENMAKE_BASE=TRUE

=P1V5S0_EN

MAKE_BASE=TRUEP1V8S0_EN =P1V8S0_EN

=TBT_S0_EN

=P3V3S0_EN

=PBUSVSENS_EN

=P5VS0_EN

CHGR_VFRQ

=PP3V42_G3H_PWRCTL

MAKE_BASE=TRUE

SMC_S4_WAKESRC_EN

P1V8S0_PGOOD

DDRREG_ENMAKE_BASE=TRUE

=PP3V3_SUS_PWRCTL

MAKE_BASE=TRUEPM_SLP_S4_L

ALL_SYS_PWRGD

=P3V3S5_EN


P5VS3_ENMAKE_BASE=TRUE

=P5VS3_EN

AP_PWR_EN

CPUVCCIOS0_PGOOD

=PP5V_S0_VMON

=PP1V05_S0_VMON

VMON_3V3_DIV VMON_Q2_BASE

=PP3V3_S5_VMON

S0PGD_C

VMON_Q4_BASE

S0PGD_BJT_GND_R

S4_PGOOD_CT

=PP3V3_SUS_PWRCTL

=P3V3S3_EN

=USB_PWR_EN

=DDRREG_EN

=PP1V5_S3RS0_VMON

SMC_ADAPTER_EN

=PP3V3_S0_VMON

=PP1V5_S3RS0_VMON

=PP1V05_S0_VMON

P3V3S5_PGOOD

PVCCSA_PGOOD

AC_EN_L

PM_WLAN_EN_L

S5PGOOD_DLY

MAKE_BASE=TRUEP5V3V3_REG_EN

PM_SLP_S3_L

CPUIMVP_AXG_PGOOD

SMC_PM_G2_ENMAKE_BASE=TRUE

=PP3V42_G3H_PWRCTL

=PP3V3_S5_PWRCTL

ALL_SYS_PWRGD_RP1V05_DIV_VMON

P1V5_DIV_VMON

P5V_DIV_VMON

=PP3V3_S0_VMON

ALL_SYS_PWRGD

P5VS3_PGOOD


=P5V3V3_REG_EN

MAKE_BASE=TRUES5_PWRGD

=PP3V3_S5_PWRCTL

=P5V_3V3_SUS_ENPM_SUS_ENMAKE_BASE=TRUE

=PP3V3_S5_PWRCTL

SMC_BATLOW_L

ALL_SYS_PWRGD

PM_SLP_SUS_L

VMON_Q3_BASE

CPUIMVP_VR_ON

PM_SLP_S3_R_LMAKE_BASE=TRUE

PM_RSMRST_L

SUS_PGOOD_MR_L

CPUVCCIOS0_ENMAKE_BASE=TRUE

P5V3V3_S4_EN

MAKE_BASE=TRUE

=TBTAPWRSW_EN

=P3V3S4_EN

Q79206

2

1

Q79256

2

1

C79121

2

R79741 2

R7911

1

2

C79101

2

C79861

2

R7986

1

2

C79811

2

C79871

2

R7987

1

2

R7931

12

Q79313

1 2

R79291

2

R79671

2

R79571

2

R79661 2

R79641 2

R79011 2

R79631 2

R79621 2

R79561

2

C7960 1

2

R79511

2

R79521

2

Q79505

7

1

6 4

8

2

3

R79541 2

R79551 2

U7930

4

2

3

15

6C79311

2

R79331

2

C7930 1

2

R79681 2

Q79203

5

4

R79781 2

C79881

2

U7960

4

1

8

9

356

2 7

R79731

2

R79711

2

R79611

2

R79701

2

R79721

2

R79601

2

C79421

2

R79411 2

C7940 1

2 U7941

7

5

2

63

4

8

9

1

C79411

2

R79131 2

C79131

2

R7981

1

2

R79171 2

U7940

1

3

6

2

5

4

C7943 1

2

R7988

1

2

R7912

1

2

R79651 2

Q79253

5

4

R79531 2

R7915

1 2

U7970

2

1

3

6

4

C7970 1

2

R79301

2

051-9276

2.7.0

79 OF 109

61 OF 72

5

7 61

7

7 61

7 61

23 25 40 51 61

7

7 61

7

7 61

7 61

7 61

7 61

7 61

7 61

7 61

7 61

7 61

44

7 61

23 25 40 51 61

GND THRM

ON

VIN_1

VIN_2

VOUT_1

VOUT_2

PAD

NC

NC

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

BI

BI

BI

IN

NC

NCNC

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6 3



Internal DP Connector: 518S0829

LCD Connector

LED Backlight I/F

DisplayPort I/F

(DP_INT_AUX_CH_C_P)

Pull-ups on panel side,

4.7 kOhm to 3.3V

CHECK IF LVDS_IG_PANEL_PWR GLITCHES ON POWER UP

(DP_INT_AUX_CH_C_N)10UF

603X5R6.3V20%10%

6.3VX5R201

0.1UF1K5%

1/20WMF

201

0.1UF

201X5R6.3V10%

MFET-2X2-8IN

CRITICAL

FPF1009

5%50V

C0G-CERM603

1000PF


10%16VX7R201

1000PF

0.1UF

10%16V

0201X5R-CERM

16V10%

X5R-CERM0201

0.1UF

16V10%

X5R-CERM0201

0.1UF

10%16V

X5R-CERM0201

0.1UF

CRITICAL

20525-130E-01F-RT-SM

201MF

1/20W5%

100K


5%

0

1/20WMF201

100K5%1/20WMF201

MF1/20W5%100K

201

9

6 64

6 64

6 64

6 64

6 64

6 64

9 65

9 65

8

9 65

9 65

43

43

201

5%

0

MF1/20W

201

5%

0

MF1/20W

5%1/20W

MF

1M

201


1M

201

5%


MF1/20W

0402-LF

FERR-120-OHM-1.5A


Internal DisplayPort Connector

DP_INT_ML_F_N<0>

DP_INT_AUX_CH_P


PP3V3_SW_LCD_UFMIN_LINE_WIDTH=0.30 MM

VOLTAGE=3.3V

LCD_IG_PWR_EN

DP_INT_AUX_CH_N

DP_INT_ML_P<0>

DP_INT_HPD_CONN

DP_INT_ML_N<0>

=PP3V3_S5_LCD

LED_RETURN_6


PP3V3_SW_LCD

VOLTAGE=3.3V

LED_RETURN_5

LED_RETURN_4

LED_RETURN_3

I2C_TCON_SCL_R

=I2C_TCON_SDA

=I2C_TCON_SCL

DP_INT_ML_F_P<0>

DP_INT_HPD

DP_INT_AUX_CH_C_P

DP_INT_AUX_CH_C_N

LED_RETURN_1

LED_RETURN_2

I2C_TCON_SDA_R

PPVOUT_SW_LCDBKLT

L9004

1 2

C90121

2

C9011 1

2

R90141

2

C90091

2

U9000

6

1

7

2

3

4

5

C9017 1

2

C9015 1

2

C9024

1 2

C9025

1 2

C9020

1 2

C9021

1 2

J9000

1

10

11

12

13

14

15

16

17

18

19

2

20

21

22

23

24

25

26

27

28

29

3

30

31

32

33

34

35

36

37

38

39

4

40

41

5

6

7

8

9

R90501

2

R90601 2

R90801

2

R90701

2

R90611 2

R90621 2

R90181

2

R90171

2

051-9276

2.7.0

90 OF 109

62 OF 72

6 65

6

7

6

6

6 65

6 65

6 65

6

6 64

IN

IN

OUT

IN

IN

ISET_S3

V3P3OUT

ISET_S0

EN

S0

HV_EN

RSVD

GND THRM

OUT

VHV

ISET_V3P3

RSVD

V3P3

PAD

IN

IN

IN

DPMLO+

DPMLO-

VDD

DP-

DP+

DDC_CLK

AUX+

AUX-

AUXIO_EN

AUXIO-

AUXIO+

THMPADGND

BIASIN BIASOUT

DDC_DAT

CA_DETOUT CA_DET

DP_PD

LSTX

LSRX

HPDOUT HPDOUT

BI

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

IN

IN

BI

BI

IN

IN

DP_PWR

AUX_CHP

ML_LANE3P

ML_LANE3N

CONFIG1

AUX_CHN

RETURN

GND GND

ML_LANE0N

ML_LANE0P

CONFIG2

HOT_PLUG_DETECT

GND

GND

GND

ML_LANE1P

ML_LANE1N

ML_LANE2P

ML_LANE2N

SHIELD PINS

Y A

B

C

VCC

GND

OUT


Apple Inc.


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6 3



Nominal Min Max

Single R on ISET_V3P3 OK.

Y = B

Thunderbolt Connector A

TBT: LSX_A_R2P/P2R (P/N)

TBT: RX_1 Bias Sink

470k R’s for ESD protection

on AC-coupled signals.

TBT: TX_0

TBT Dir

(Both D’s)

514-0818

TBT: LSX_R2P/P2R (P/N)TBT: Unused

greater than or equal

(Both C’s)

TBT: TX_1

DP Source must pull

down HPD input with

Sink HPD range:

below

For J9400 TBT SMT pads

Nominal Min Max

IHVS0/S3 1120mA 1090mA 1170mA (12W minimum)

TBT DirDP Dir

ILIM = 40000 / RISET

(Both C’s)

(Both C’s)

For 12V systems:

12V: See

18.9V Max

V3P3 must be S4 to support

wake from Thunderbolt devices.

IV3P3 1100mA 1030mA 1200mA

IHVS3 890mA 830mA 930mA (assumes 3S, 9-12.6V, 7.5-11.7W)

(3, 5, 17 & 19):

Low: 0 - 0.8V

High: 2.0 - 5.0V

(0-18.9V)

DP Dir

(0-18.9V)

(Both C’s)

to 100K (DPv1.1a).

IHVS0 890mA 830mA 930mA (assumes 15V, 12W minimum)

ISET_Sx with CD3210.

requires two R’s per HV

Single-fault protection

3.3V/HV Power MUX

X7R

0.01UF

50V10%

402

33 69

33 69

1/20W

125%

MF201

402

0.01UF

X7R

10%50V

SIGNAL_MODEL=EMPTY

1K

GND_VOID=TRUE

MF1/20W

201

5%1K

GND_VOID=TRUE

SIGNAL_MODEL=EMPTY

MF1/20W

201

5%

30PF

CERM402

5%50V

CERM50V

402

30PF5%

100K

MF1/20W

201

5%

CRITICAL

GND_VOID=TRUE

SIGNAL_MODEL=EMPTY

650NH-5%-0.430MA-0.52OHM

0603

GND_VOID=TRUE

650NH-5%-0.430MA-0.52OHM

CRITICAL

SIGNAL_MODEL=EMPTY

0603

0402CERM-X5R

20%10UF

6.3V16V10%

0201

0.1UF

X5R-CERM

0.1UF

16V

0201

10%

X5R-CERMX5R-CERM-1

22UF

CRITICAL

603

20%6.3V

20%6.3V

POLY-TANT

CRITICAL

CASE-B2-SM

100UF

1/20W

1M

MF201

5%

201

1M

MF1/20W5% 330PF

10%16VX7R201

16V

330PF10%

X7R201

201GND_VOID=TRUE

2.2K

MF1/20W

5%2.2K

GND_VOID=TRUE

MF1/20W

201

5%

FERR-120-OHM-3A

0603

33

X5R402

0.1UF

25V10%

TSLP-2-7

CRITICAL

BAR90-02LRH

SIGNAL_MODEL=TBTPINGND_VOID=TRUE

CRITICAL

TSLP-2-7

GND_VOID=TRUESIGNAL_MODEL=TBTPIN

BAR90-02LRH

470K

MF1/20W

201

GND_VOID=TRUE

5%

MF

470K

1/20W

GND_VOID=TRUE

201

5%

33 69

33 69

GND_VOID=TRUE

470K

201

1/20WMF

5%470K

201

1/20WMF

GND_VOID=TRUE

5%

CD3210A0RGPQFN

CRITICAL

33 35

61

61

MF

36.5K1%

201

1/20W

402

25V10%0.1UF

X5R

HVQFNCBTL05023

CRITICAL

SIGNAL_MODEL=TBT_MUX

5%

201

1/20WMF

100K

100K

201

1/20WMF

5%

X5R-CERM

10%0.1UF

0201

16V

0.1UF

0201X5R-CERM

16V10%

33

8

8

25

33

33

33

5%

201

1/20WMF

1M

10K

MF1/20W

201

5%

10%

0201X5R-CERM16V

0.1UF

33

33 69

33 69

33 69

33 69

33 69

33 69

0.1UF10%X5R-CERM 0201

16V

10%X5R-CERM0.1UF 0201

16V

33 69

33 69

33 69

33 69

470K5%

2011/20W

MF

5%201

1/20WMF

470K

F-RT-THMDP-J11

CRITICAL

GND_VOID=TRUEGND_VOID=TRUEGND_VOID=TRUEGND_VOID=TRUE

201

1%

MF

22.6K1/20W

TBTHV:P15V

201MF1/20W1%22.6K

TBTHV:P15V

4.7UF

0603X5R-CERM

25V10%

CERM-X5R-1

GND_VOID=TRUE

2014V20%0.47UF

GND_VOID=TRUE

CERM-X5R-12014V20%0.47UF

2010.47UF 20% 4VCERM-X5R-1

GND_VOID=TRUE

0.47UF 201

GND_VOID=TRUE

20% 4V

CERM-X5R-1

TBTHV:P15V

1/20W

22.6K

201MF

1%

TBTHV:P15V

1/20W

22.6K

201MF

1%

0.22UF 20%X5R

6.3V0201

6.3VX5R20%0.22UF 0201

GND_VOID=TRUE

0.22UF02016.3V20%

X5R

GND_VOID=TRUE

02010.22UF 6.3V20%

X5R

GND_VOID=TRUE

02016.3V

X5R20%0.22UF

GND_VOID=TRUE

02010.22UF 6.3V20%

X5R

02010.22UF 6.3V20%

X5R

0201X5R

20% 6.3V0.22UF

X5R-CERM0201

0.01UF

10%25V

10%25V

X5R-CERM

0.01UF

0201

0201

0.01UF

X5R-CERM25V10%

CRITICAL

74AUP1T97SOT891

CERM10V20%0.1UF

402

33


Thunderbolt Connector A

RES,MF,1/20W,17.8K,1,0201118S0145 R9411,R94142 TBTHV:P12V

TBTHV:P12VRES,MF,1/20W,17.8K,1,0201118S0145 R9410,R94132

=PPHV_SW_TBTAPWRSW

TBTAPWRSW_ISET_S3_R

TBTAPWRSW_ISET_S0

=PP3V3_S4_TBTAPWRSW

TBTAPWRSW_ISET_S3

DP_TBTSNK0_DDC_DATADP_A_AUXCH_DDC_P

TBT_A_CONFIG1_RC

TBT_A_LSRX_UNBUF

TBT_A_R2D_N<0>

TBT_A_R2D_P<1>

TBTACONN_1_CMIN_LINE_WIDTH=0.38 MM


TBT_A_R2D_P<0>

TBT_A_R2D_C_P<0>

TBTAPWRSW_ISET_S0_R

=TBT_S0_EN

TBT_A_HV_EN

DP_A_AUXCH_DDC_N

TBT_A_D2R_P<0>

TBT_A_D2R_N<0>

TBT_A_D2R_C_P<1>

TBT_A_D2R_C_N<1>

VOLTAGE=18.9VMIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.38 MMTBTACONN_20_RC


MIN_LINE_WIDTH=0.38 MMPP3V3_SW_TBTAPWR

=TBTAPWRSW_EN


PP3V3RHV_SW_TBTAPWR

VOLTAGE=15V


TBT_A_D2R_C_P<0>

TBT_A_D2R_C_N<0>

MIN_NECK_WIDTH=0.20 MMVOLTAGE=15V

MIN_LINE_WIDTH=0.38 MMPPHV_SW_TBTAPWR

TBT_A_R2D_C_N<0>

TBT_A_R2D_C_P<1>

DP_TBTPA_ML_C_P<3>

DP_TBTPA_ML_N<3>DP_TBTPA_ML_C_N<3>

TBT_A_BIAS

TBT_A_R2D_N<1>

TBT_A_R2D_C_N<1>

DP_A_AUXCH_DDC_P

TBT_A_CONFIG1_RC

TBT_A_D2R_P<1>

TBT_A_D2R1_AUXDDC_N

DP_A_LSX_ML_P<1>

TBTACONN_7_C

VOLTAGE=18.9V


DP_TBTPA_ML_P<3>

TBT_A_HPD

TBT_A_D2R_N<1>

TBT_A_CONFIG2_RC

TBT_A_D2R1_AUXDDC_P

DP_A_LSX_ML_N<1>

DP_TBTPA_AUXCH_N

DP_TBTPA_AUXCH_P

DP_TBTPA_ML_P<1>

DP_TBTPA_AUXCH_C_P

DP_TBTPA_ML_C_P<1>

DP_TBTPA_AUXCH_C_N

DP_TBTPA_ML_N<1>DP_TBTPA_ML_C_N<1>

VOLTAGE=3.3VTBT_A_BIAS

DP_A_AUXCH_DDC_N

PP3V3_SW_TBTAPWR

DP_A_LSX_ML_P<1>

DP_A_LSX_ML_N<1>

DP_TBTSNK0_DDC_CLK

DP_AUXIO_EN

TBT_A_CIO_SEL

TBT_A_CONFIG1_BUF

TBT_A_HPD

TBT_A_DP_PWRDN

DP_TBTPA_HPD

TBT_A_LSTX

PP3V3_SW_TBTAPWR

TBT_A_LSRX

TBTAPWRSW_ISET_V3P3

L9400

1 2

C9400 1

2

R94011

2

C9401 1

2

R94941

2

R94951

2

C9498 1

2

C94991

2

R94411

2

L9498

12

L9499

12

C94861

2

C9485 1

2

C94811

2

C9480 1

2

C9487 1

2

R94521

2

R94511

2

C9494 1

2

C94951

2

R94981

2

R94991

2

C9410 1

2

D9499 A K

D9498 A K

R94701

2

R94711

2

R94731

2

R94721

2

U9410

5

1 2 3 4

13

11 10

9

8

12

14

1516

17

21

19

20

18

6

7

R94121

2

C94111

2

U9420

7

8

2

23

22

1 24

1816

5

4

10

11

6

20

19

9

21

1712

13

14

25

3 15

R94291

2

R94281

2

C9420 1

2

C9421 1

2

R94261

2

R94271

2

C94251

2

C9430 1 2

C9431 1 2

R9479 1 2

R9478 1 2

J9400

18

16

4

6

20

1

713

814

2

21

22

23

24

25

26

27

28

5

3

11

9

17

15

12

10

19

R94101

2

R94111

2

C9415 1

2

C9474 1 2

C9475 1 2

C9476 1 2

C9477 1 2

R94131

2

R94141

2

C9433 1 2

C9432 1 2

C9470 1 2

C9471 1 2

C9472 1 2

C9473 1 2

C9479 1 2

C9478 1 2

C94051 2

C940612

C9402 1

2

U9460

2

3

1

6

5

4

C94601

2

051-9276

2.7.0

94 OF 109

63 OF 72

7

7

63 69

63

69

69

69

63 69

69

69

7 63

69

69

69

63

69

63 69

63

69

63 69 69

63

69

63 69

69

69

69

69

63

63 69

7 63

63 69

63 69

63

7 63

VDDIO VINVLDO

SW_0

SW_1

FB

OUT3

OUT2

OUT1

OUT4

OUT5

OUT6

GND_SW

GND_S

GND_L

GND_SW

VSYNC

ISET

FILTER

FSET

SCLK

PWM

SDA

FAULT

EN

IN

IN

D

SG

D

SG

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

BI


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6 3



PPBUS_SW_LCDBKLT_PWR

*LCD_BKLT_PWM SHOULD BE AWAY FROM BOOST CIRCUITON THE SENSOR PAGE

I_LED=20.3mA

*PPBUS_SW_LCDBKLT_PWR_SW SHOULD BE KEPT AS SHORT AS POSSIBLE.

*C9797 AND C9799 SHOULD BE PLACED IN T-BONE FOR ACOUSTICS

RDS(ON) 43 mOhm @4.5V

FDC638APZ

CHANNEL

MOSFET

P-TYPE

0.65 A (EDP)LOADING

THERE IS A SENSE RESISTOR BETWEEN

AND PPBUS_SW_BKL

10.2 ohm resistors for current

measurement on LED strings.

I_LED=369/Riset

(EEPROM should set EN_I_RES=1)

Addr: 0x58(Wr)/0x59(Rd)

PPBUS S0 LCDBkLT FET

Fpwm=9.62kHz

see spec for others

PLACE_NEAR=D9701.2:5mm

1210-1

50VX5R

CRITICAL

10%10UF

PLACE_NEAR=D9701.2:3mm

1210-1

10UF10%50V

CRITICAL

X5R

15UH-2.8A

PIMB053T-SM

CRITICAL

LP8550

25-BUMP-MICRO

CRITICAL

25

8

SOT563

SSM6N15FEAPE

1%

147K

MF

1/20W

201

SOT563

SSM6N15FEAPE

603-HF

3AMP-32V-467

BOTTOM

1%

301K

MF

1/20W

201

10%

16V

0.1UF

402

X5R

CRITICAL

FDC638APZ_SBMS001

SSOT6-HF

SM


201MF1/20W1%18.2K

200K

1/20W1%

201MF 1%

1/20W

201

100K

MF

201

5%

MF

10K

1/20W

5%

201

1/20WMF

0

0

MF1/20W5%

201

5%1/20WMF201

33

33PF

201

5%25VNP0-C0G

1/20W

90.9K

201MF

1%

201MF

1/20W5%

10K

PLACE_NEAR=U9701.C4:4mm

10%

X5R201

6.3V

0.1UF

PLACE_NEAR=U9701.D1:3mm

201X5R

0.01UF

10V10%

CRITICAL

10UF

805X5R

10%25V

PLACE_NEAR=L9701.1:3mm PLACE_NEAR=L9701.1:3mm

10%

402

0.1UF

X5R25V 10%

50V

402


X7R-CERM

220PF

RB160M-60G


SOD-123

CRITICAL

0

1/16WMF-LF

5%

402

BKLT:PROD

PLACE_NEAR=U9701.E1:10mm

BOTTOM

0

1/16WMF-LF

5%

402

BKLT:PROD


BOTTOM

402

5%

MF-LF1/16W

BKLT:PROD

0

BOTTOM


6 62

6 62

6 62

6 62

6 62

6 62

0

5%

MF-LF402

1/16W

BKLT:PROD


BOTTOM

BKLT:PROD

1/16WMF-LF402

5%

0PLACE_NEAR=U9701.C5:10mm

BOTTOM

0

1/16W5%

402MF-LF

BKLT:PROD


BOTTOM

603-1

10%25VX5R


1UF

SM

PLACEMENT_NOTE=Keep away from noise nodes(E4, A1, A2, B1, B2 pins)

8

43

43


LCD Backlight DriverBKLT:ENGRES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM3 R9720,R9721,R9722103S0198

RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM103S0198 R9717,R9718,R97193 BKLT:ENG

=PP3V3_S0_BKL_VDDIO

BKL_VSYNC_R


BKL_ISEN4


BKL_ISEN3


BKL_ISEN2


BKL_ISEN1

BKL_FLTR


BKL_ISEN5


BKL_ISEN6



PPBUS_SW_LCDBKLT_PWR_SWMIN_LINE_WIDTH=0.5 MM

VOLTAGE=50V



PPBUS_S0_LCDBKLT_FUSED

GND_BKL_SGND

VOLTAGE=0VMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.4 MM


PPVOUT_SW_LCDBKLT_FBVOLTAGE=50V


TP_BKL_FAULTPLACE_SIDE=BOTTOM

VOLTAGE=50VMIN_NECK_WIDTH=0.375 MM

PPVOUT_SW_LCDBKLTMIN_LINE_WIDTH=0.5 MM

VOLTAGE=12.6V

PPBUS_SW_LCDBKLT_PWRMIN_LINE_WIDTH=0.4 mmMIN_NECK_WIDTH=0.25 mm


LED_RETURN_6

LED_RETURN_3MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.20 mm

LED_RETURN_2


LED_RETURN_1


LED_RETURN_4MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mmLED_RETURN_5


LCDBKLT_DISABLELCD_BKLT_EN

BKLT_PLT_RST_L

LCDBKLT_EN_L

BKL_ISET

PPBUS_SW_LCDBKLT_PWR

BKL_EN

BKL_SCL

=I2C_BKL_1_SCL

BKL_SDA=I2C_BKL_1_SDA

LCD_BKLT_PWM

BKL_FSET

BKL_PWM

=PPBUS_S0_LCDBKLT

LCDBKLT_EN_DIV=PPBUS_SW_BKL

=PP5V_S0_BKL

C9712 1

2

C97131

2

C97961

2

D9701

A K

R97221 2

R97211 2

R97201 2

R97181 2

R97191 2

R97171 2

C9710 1

2

XW9710

1 2

C97991

2

C97971

2

L9701

1 2

U9701

A3

C3

A5

C2

B4

E4

B5

A1

A2

B3

E5

D5

C5

E3

E2

E1

A4

D3

D4

B1

B2

C4

C1

D1

D2

Q9707 3

54

R97891

2

Q9707 6

21

F9700

1 2

R97881

2

C9782 1

2

Q9706

12

56

3

4

XW9720

1 2

R97141

2

R9731

1 2

R97151

2

R97411 2R9753

1 2

R97571 2

R97041 2

C97041

2R97161

2

R97551

2

C9711 1

2

C97141

2

051-9276

2.7.0

97 OF 109

64 OF 72

7

6 62

8 64

8 64

7

8

7

TABLE_SPACING_ASSIGNMENT_ITEM



AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD




















TABLE_SPACING_RULE_ITEM















LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD





TABLE_PHYSICAL_RULE_ITEM


MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD






























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CPU Net PropertiesNET_TYPE

PHYSICAL SPACING

(XDP_BPM_L_R_CFG)

(XDP_BPM_L_R_CFG)

(FSB_CPURST_L)

DP

PCIe SSD

DMI/FDI

SOURCE: 471984_Chief_River_MS_PDG_1.0 and the spacing rule is adjusted per SI team feedback.

PCH PCIE Spacing

PCIE Clock Spacing

CPU Signal Constraints

ELECTRICAL_CONSTRAINT_SET

once rdar://10308147 is resolved

back to TABLE_SPACING_RULE

Note: CPU_8MIL and CPU_ITP can be converted

CPU PCIE Spacing

Note: DisplayPort tables are on Page 103

PCI-Express Interface Constraints

=10x_DIELECTRIC ?CPU_COMP_2OTHER TOP,BOTTOM

=6x_DIELECTRICTOP,BOTTOM ?CPU_COMP_2SELF

CPU_ITP_2ANY ?* =4x_DIELECTRIC

?* =4x_DIELECTRICCPU_VCCSENSE_2SELF

?* =6x_DIELECTRICCPU_VCCSENSE_2OTHER

=80_OHM_DIFF =80_OHM_DIFFPCIE_80D * =80_OHM_DIFF=80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF

TOP,BOTTOM ?=6x_DIELECTRICCLK_PCIE_2SELF

=80_OHM_DIFF*CLK_PCIE_80D =80_OHM_DIFF =80_OHM_DIFF=80_OHM_DIFF =80_OHM_DIFF=80_OHM_DIFF


CPU Constraints

SYNC_MASTER=CONSTRAINTS

=STANDARDCPU_AGTL * ?

* * CPU_8MIL_2ANYCPU_8MIL

CPU_ITP CPU_ITP_2ANY**

CPU_COMP_2SELF ?* =4x_DIELECTRIC

CPU_COMP_2OTHER ?* =6x_DIELECTRIC

CPU_VCCSENSE_2SELF =6x_DIELECTRICTOP,BOTTOM ?

CLK_PCIE_2OTHER ?* =6x_DIELECTRIC

PCIE_TX2TX =5x_DIELECTRICTOP,BOTTOM ?

PCIE_2OTHERHS =4x_DIELECTRIC* ?

PCIE_RX2RX TOP,BOTTOM ?=5x_DIELECTRIC

?TOP,BOTTOM =10x_DIELECTRICCLK_PCIE_2OTHER

CPU_VCCSENSE ** CPU_VCCSENSE_2OTHER

=4x_DIELECTRIC ?*CLK_PCIE_2SELF

PCIE_CPU_TX *_CPU_RX * PCIE_TX2RX

*_CPU_TXPCIE_CPU_RX PCIE_RX2TX*

PCIE_2OTHERHS**_TXPCIE_CPU_TX

=7x_DIELECTRICPCIE_RX2TX ?TOP,BOTTOM

CPU_VCCSENSE * CPU_VCCSENSE_2SELFCPU_VCCSENSE

=27P4_OHM_SE 0.100 MM=27P4_OHM_SE=27P4_OHM_SECPU_27P4S * 0.100 MM=27P4_OHM_SE

8 MIL ?*CPU_8MIL_2ANY

=STANDARD=45_OHM_SE=45_OHM_SE =45_OHM_SECPU_45S =STANDARD* =45_OHM_SE

=10x_DIELECTRICTOP,BOTTOM ?CPU_VCCSENSE_2OTHER

CLK_PCIE_2SELFCLK_PCIECLK_PCIE *

CLK_PCIE_2OTHER*CLK_PCIE *

=6x_DIELECTRIC ?PCIE_RX2TX *

PCIE_2OTHER ?=3x_DIELECTRIC*

=6x_DIELECTRICPCIE_TX2RX * ?

=4x_DIELECTRICPCIE_RX2OTHERRX ?*

* ?PCIE_RX2RX =2.5x_DIELECTRIC

* =2.5x_DIELECTRICPCIE_TX2TX ?

?* =4x_DIELECTRICPCIE_TX2OTHERTX

TOP,BOTTOM ?=5x_DIELECTRICPCIE_2OTHER

PCIE_2OTHERHS =6x_DIELECTRIC ?TOP,BOTTOM

PCIE_TX2RX TOP,BOTTOM =7x_DIELECTRIC ?

=5x_DIELECTRICPCIE_RX2OTHERRX TOP,BOTTOM ?

PCIE_TX2OTHERTX =5x_DIELECTRICTOP,BOTTOM ?

CPU_COMP CPU_COMP * CPU_COMP_2SELF

CPU_COMP_2OTHERCPU_COMP **

TOP,BOTTOMCPU_AGTL =2x_DIELECTRIC ?

PCIE_CPU_TX PCIE_TX2TX*PCIE_CPU_TX

PCIE_CPU_RX PCIE_RX2RX*PCIE_CPU_RX

PCIE_CPU_RX * PCIE_RX2OTHERRX*_CPU_RX

PCIE_TX2OTHERTX*PCIE_CPU_TX *_CPU_TX

**_TXPCIE_CPU_RX PCIE_2OTHERHS

PCIE_2OTHERHS*_RXPCIE_CPU_TX *

*_RX PCIE_2OTHERHS*PCIE_CPU_RX

PCIE_2OTHER* *PCIE_CPU_TX

* PCIE_2OTHER*PCIE_CPU_RX

PCIE_2OTHER**PCIE_PCH_RX

* PCIE_2OTHER*PCIE_PCH_TX

PCIE_PCH_RX PCIE_2OTHERHS**_RX

PCIE_PCH_RX PCIE_RX2TX**_PCH_TX

PCIE_PCH_TX PCIE_TX2RX**_PCH_RX

*_TX * PCIE_2OTHERHSPCIE_PCH_TX

*_TX PCIE_2OTHERHS*PCIE_PCH_RX

PCIE_PCH_TX **_RX PCIE_2OTHERHS

*_PCH_RX PCIE_RX2OTHERRX*PCIE_PCH_RX

PCIE_TX2OTHERTX*_PCH_TXPCIE_PCH_TX *

PCIE_PCH_RXPCIE_PCH_RX * PCIE_RX2RX

PCIE_TX2TX*PCIE_PCH_TX PCIE_PCH_TX

PCIE_CPU_TXPCIE_CPU_MUX_R2D PCIE_SSD_R2D_C_N<0>PCIE_80D

PCIE_CPU_TXPCIE_80D PCIE_SSD_R2D_MUX_IN_PPCIE_SSD_R2D_MUX_IN_NPCIE_CPU_TXPCIE_80D

PCIE_CPU_MUX_D2R PCIE_CPU_RX PCIE_SSD_D2R_P<0>PCIE_80D

PCIE_CPU_TXPCIE_CPU_MUX_R2D PCIE_80D PCIE_SSD_R2D_C_P<0>

CPU_45S CPU_ITP XDP_CPU_PRDY_L

CPU_AGTL PM_MEM_PWRGDPM_MEM_PWRGD CPU_45S

PCIE_PCH_RXFDI_DATA FDI_DATA_P<7:0>PCIE_80D

PCIE_PCH_RX DMI_N2S_N<3:0>DMI_N2S PCIE_80D

CPU_45S CPU_AGTL FDI_LSYNC<1..0>CPU_AGTL FDI_FSYNC<1..0>CPU_45S

CPU_45S CPU_ITPXDP_TMS XDP_CPU_TMS

XDP_TRST_L CPU_45S CPU_ITP XDP_CPU_TRST_LCPU_45SXDP_BPM_L XDP_BPM_L<3..0>CPU_ITP

CPU_ITPCPU_45S XDP_CPURST_L

CPU_45S XDP_OBSDATA_B<3..0>CPU_ITP

DP_INT_ML_P<3..0>DP_TXDP_80DDP_INT_ML

PCIE_CLK100M_SSD_NCLK_PCIE_80D CLK_PCIEPCIE_CLK100M_SSD

PCIE_CPU_TX PCIE_SSD_R2D_P<1>PCIE_80D

CPU_VCCSENSESENSE_1TO1_P2MMCPU_AXG_SENSE CPU_AXG_SENSE_P

XDP_TCK CPU_45S CPU_ITP XDP_CPU_TCK

CPU_45S CPU_ITP XDP_CPU_TDIXDP_TDI

CLK_PCIE XDP_CPU_CLK100M_PITPCPU_CLK100M CLK_PCIE_80D

DP_AUX DP_INT_AUX_CH_NDP_80D

DP_AUX DP_INT_AUX_CH_C_NDP_INT_AUXCH DP_80DDP_INT_AUX_CH_PDP_AUXDP_80D

DP_AUX DP_INT_AUX_CH_C_PDP_80DDP_INT_AUXCH

DP_TX DP_INT_ML_F_N<3..0>DP_80D

DP_TX DP_INT_ML_N<3..0>DP_80DDP_INT_MLDP_INT_ML_F_P<3..0>DP_TXDP_80D

CLK_PCIE_80D CLK_PCIE PCIE_CLK100M_SSD_PPCIE_CLK100M_SSD

PCIE_CPU_RXPCIE_80D PCIE_SSD_D2R_C_P<1>

PCIE_CPU_RXPCIE_80D PCIE_SSD_D2R_MUX_OUT_N

PCIE_CPU_SSD_R2D PCIE_CPU_RXPCIE_80D PCIE_SSD_R2D_C_P<1>

PCIE_CPU_SSD_D2R PCIE_CPU_RXPCIE_80D PCIE_SSD_D2R_P<1>

PCIE_CPU_RXPCIE_80D PCIE_SSD_D2R_C_N<1>

PCIE_CPU_SSD_D2R PCIE_CPU_RXPCIE_80D PCIE_SSD_D2R_N<1>

PCIE_CPU_TXPCIE_80D PCIE_SSD_R2D_N<1>

PCIE_CPU_SSD_R2D PCIE_CPU_RXPCIE_80D PCIE_SSD_R2D_C_N<1>

PCIE_CPU_RXPCIE_80D PCIE_SSD_D2R_MUX_OUT_PPCIE_SSD_D2R_N<0>PCIE_CPU_MUX_D2R PCIE_CPU_RXPCIE_80D

CPU_COMPCPU_SVIDSOUT CPU_45S CPU_VIDSOUTCPU_COMP CPU_VIDSCLKCPU_SVIDSCLK CPU_45S

CPU_COMPCPU_45SCPU_SVIDALERT_L CPU_VIDALERT_L

CPU_VCC_VALSENSE_NCPU_VCCSENSECPU_27P4SCPU_VALSENSE

CPU_VCC_VALSENSE_PCPU_VCCSENSECPU_VALSENSE CPU_27P4S

CPU_AXG_VALSENSE_NCPU_VCCSENSECPU_27P4SCPU_VALSENSE

CPU_VCCSENSE CPU_AXG_VALSENSE_PCPU_27P4SCPU_VALSENSE

CPU_VCCSENSE CPU_VDDQ_SENSE_NCPU_VALSENSE CPU_27P4S

CPU_AXG_SENSE CPU_VCCSENSESENSE_1TO1_P2MM CPU_AXG_SENSE_NCPU_VCCSENSECPU_27P4S CPU_VDDQ_SENSE_PCPU_VALSENSE

CPU_VCCSENSESENSE_1TO1_P2MM CPU_VCCIOSENSE_NCPU_VCCIOSENSE

CPU_VCCSENSESENSE_1TO1_P2MM CPU_VCCIOSENSE_PCPU_VCCIOSENSE

CPU_VCCSENSE SENSE_1TO1_P2MM CPU_VCCSENSE CPU_VCCSENSE_NCPU_VCCSENSE SENSE_1TO1_P2MM CPU_VCCSENSE CPU_VCCSENSE_P

CPU_45S CPU_ITP CPU_CFG<15..12>

CPU_45SXDP_BPM_L_R_CFG XDP_BPM_L<7..4>CPU_ITP

CPU_45S CPU_ITPXDP_TDO XDP_CPU_TDO

CPU_27P4S EDP_COMPCPU_COMP

CPU_27P4S CPU_PEG_COMPCPU_COMP

CLK_PCIE_80D CLK_PCIE XDP_CPU_CLK100M_NITPCPU_CLK100M

CLK_PCIE ITPXDP_CLK100M_NCLK_PCIE_80DITPCPU_CLK100M

CLK_PCIECLK_PCIE_80D ITPXDP_CLK100M_PITPCPU_CLK100M

CLK_PCIE ITPCPU_CLK100M_NCLK_PCIE_80DITPCPU_CLK100M

CLK_PCIE ITPCPU_CLK100M_PITPCPU_CLK100M CLK_PCIE_80D

CLK_PCIE_80D CLK_PCIEDPLL_REF_CLK120M DPLL_REF_CLKNCLK_PCIE_80D CLK_PCIE DPLL_REF_CLKPDPLL_REF_CLK120M

CLK_PCIECLK_PCIE_80D DMI_CLK100M_CPU_NDMI_CLK100M

CPU_8MILPM_THRMTRIP_L PM_THRMTRIP_LCPU_45S

CLK_PCIECLK_PCIE_80D DMI_CLK100M_CPU_PDMI_CLK100M

CPU_AGTLCPU_PWRGD CPU_PWRGDCPU_45S

CPU_AGTL CPU_VCCIO_SELCPU_45S

CPU_AGTLCPU_PROCHOT_L CPU_PROCHOT_LCPU_45S

CPU_AGTL CPU_CATERR_LCPU_CATERR_L CPU_45S

CPU_ITP CPU_CFG<11..0>CPU_45S

CPU_COMP CPU_SM_RCOMP<2>CPU_SM_RCOMP CPU_27P4S

CPU_COMPCPU_SM_RCOMP CPU_27P4S CPU_SM_RCOMP<0>CPU_COMP CPU_SM_RCOMP<1>CPU_27P4SCPU_SM_RCOMP

CPU_45S XDP_CPU_PREQ_LCPU_ITP

PCIE_PCH_TXPCIE_80D DMI_S2N_P<3:0>DMI_S2N

PCIE_PCH_TX DMI_S2N_N<3:0>PCIE_80DDMI_S2N

PCIE_PCH_RXPCIE_80D DMI_N2S_P<3:0>DMI_N2S

PCIE_PCH_RX FDI_DATA_N<7:0>FDI_DATA PCIE_80D

CPU_AGTL FDI_INTCPU_45S

CPU_45S CPU_COMPCPU_PECI CPU_PECICPU_AGTLPM_SYNC PM_SYNCCPU_45S

CPU_ITP XDP_DBRESET_LCPU_45S

051-9276

2.7.0

100 OF 109

65 OF 72

8 37

37

37

8 37

8 37

10 23

10 17 26

9 17

9 17

9 17

9 17

10 23

10 23

10 23

23

23

9 62

6 16 37

6 37

12 56

10 23

10 23

23

9 62

6 62

9 62

6 62

6 62

9 62

6 62

6 16 37

37

8 37

6 8 37

6 8 37

6 37

8 37

37

8 37

12 56

12 56

12 56

9

9

9

9

12

12 56

12

12 58

12 58

12 56

12 56

9 23

10 23

10 23

9

9

23

16 23

16 23

10 16

10 16

8 10

8 10

10 16

10 19 41

10 16

10 19 23

12

10 40 41 56

10 40

9 23

10

10

10

10 23

9 17

9 17

9 17

9 17

9 17

10 19 41

10 17

10 23 25







































































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=8.6x_DIELECTRIC

=5.7x_DIELECTRIC

=6x_DIELECTRIC

=6x_DIELECTRIC

=PWR_P2MM

=GND_P2MM

=2x_DIELECTRIC

"Real" Spacing

=3x_DIELECTRIC

=3x_DIELECTRIC

=3x_DIELECTRIC

=3x_DIELECTRIC

=4x_DIELECTRIC

PalPilot Spacing

=4x_DIELECTRIC

=4x_DIELECTRIC

=4x_DIELECTRIC

=PWR_P2MM

=GND_P2MM

=2x_DIELECTRIC

=5.7x_DIELECTRIC

=8.6x_DIELECTRIC

Memory Bus Constraints

Spacing Rule Sets

Memory Bus Spacing Group Assignments

Memory to GND Spacing

Memory to Power Spacing

Memory Net Properties

PHYSICALELECTRICAL_CONSTRAINT_SET

NET_TYPE

SPACING

MEM_CMD2CTRL * ?=3x_DIELECTRIC

?*MEM_CMD2CMD =3x_DIELECTRIC

*MEM_DQS2OWNDATA ?=3x_DIELECTRIC

*MEM_DATA2SELF ?=2x_DIELECTRIC

MEM_CTRL2CTRL * ?=3x_DIELECTRIC

MEM_CLK2CLK * ?=6x_DIELECTRIC

MEM_2OTHERMEM * ?=4x_DIELECTRIC

MEM_2PWR * ?=PWR_P2MM

MEM_2GND * ?=GND_P2MM

MEM_2OTHER* *MEM_CLK

MEM_2OTHER* *MEM_CMD

MEM_2OTHER* *MEM_CTRL

*MEM_B_DATA_6 * MEM_2OTHER

*MEM_B_DATA_7 MEM_2OTHER*


Memory Constraints


MEM_B_DATA_1MEM_B_DQS_1 * MEM_DQS2OWNDATA

*MEM_B_DQS_0 * MEM_2OTHER

*MEM_A_DQS_7 * MEM_2OTHER






MEM_*MEM_PWR * MEM_2PWR

=SAMEMEM_*_DATA_* MEM_DATA2SELF*

MEM_* MEM_* * MEM_2OTHERMEM

MEM_B_DATA_7MEM_B_DQS_7 MEM_DQS2OWNDATA*






MEM_B_DQS_0 MEM_B_DATA_0 MEM_DQS2OWNDATA*

MEM_A_DATA_2MEM_A_DQS_2 MEM_DQS2OWNDATA*







MEM_DQS2OWNDATAMEM_A_DATA_0MEM_A_DQS_0 *

MEM_CTRL2CTRL*MEM_CTRLMEM_CTRL

MEM_CMD2CTRL*MEM_CTRLMEM_CMD

MEM_CMD2CMD*MEM_CMDMEM_CMD

MEM_CLK2CLK*MEM_CLKMEM_CLK




*MEM_A_DATA_2 * MEM_2OTHER















** MEM_2OTHERMEM_B_DQS_1

** MEM_2OTHERMEM_B_DATA_5


**MEM_B_DATA_3 MEM_2OTHER


MEM_PWR * * DEFAULT

* ?MEM_2OTHER =6x_DIELECTRIC

MEM_80D =80_OHM_DIFF=80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF* =80_OHM_DIFF

=72_OHM_DIFF=72_OHM_DIFF=72_OHM_DIFF =72_OHM_DIFF=72_OHM_DIFF*MEM_72D =72_OHM_DIFF

=45_OHM_SE=45_OHM_SE=45_OHM_SE=45_OHM_SEMEM_45S * =45_OHM_SE=45_OHM_SE

MEM_2GND*GND MEM_*

MEM_B_DQS7 MEM_B_DQS_7 MEM_B_DQS_N<7>MEM_80D

PP1V5_S3MEM_PWR

PP0V75_S3_MEM_VREFDQ_AMEM_PWR

MEM_B_ODT<3..0>MEM_B_CTRL MEM_CTRLMEM_45S

MEM_B_CMD MEM_CMDMEM_45S MEM_B_RAS_L

MEM_B_WE_LMEM_B_CMD MEM_CMDMEM_45S

MEM_A_CAS_LMEM_A_CMD MEM_CMDMEM_45S

MEM_A_DQS_0 MEM_A_DQS_N<0>MEM_A_DQS0 MEM_80D

MEM_A_WE_LMEM_A_CMD MEM_45S MEM_CMD

MEM_A_RAS_LMEM_A_CMD MEM_CMDMEM_45S

MEM_A_DQ_BYTE3 MEM_A_DATA_3 MEM_A_DQ<31..24>MEM_45S

MEM_A_DATA_0 MEM_A_DQ<7..0>MEM_A_DQ_BYTE0 MEM_45S

MEM_A_DATA_1MEM_A_DQ_BYTE1 MEM_45S MEM_A_DQ<15..8>

MEM_B_DATA_3 MEM_B_DQ<31..24>MEM_B_DQ_BYTE3 MEM_45S

PP0V75_S3_MEM_VREFCA_AMEM_PWR


MEM_B_A<15..0>MEM_B_CMD MEM_CMDMEM_45S

MEM_B_CS_L<3..0>MEM_B_CTRL MEM_CTRLMEM_45S

MEM_CTRLMEM_B_CTRL MEM_45S MEM_B_CKE<3..0>

MEM_A_DQS_6MEM_A_DQS6 MEM_80D MEM_A_DQS_P<6>MEM_A_DQS_5MEM_80DMEM_A_DQS5 MEM_A_DQS_N<5>

MEM_B_DQS6 MEM_B_DQS_6 MEM_B_DQS_P<6>MEM_80D



MEM_B_CAS_LMEM_B_CMD MEM_CMDMEM_45S

MEM_B_BA<2..0>MEM_B_CMD MEM_CMDMEM_45S

MEM_B_CLK MEM_CLKMEM_72D MEM_B_CLK_P<5..0>

MEM_A_BA<2..0>MEM_A_CMD MEM_CMDMEM_45S

MEM_A_CLK_N<5..0>MEM_A_CLK MEM_CLKMEM_72D

MEM_A_CS_L<3..0>MEM_A_CTRL MEM_CTRLMEM_45SMEM_A_ODT<3..0>MEM_A_CTRL MEM_CTRLMEM_45S

MEM_B_DQS_4 MEM_B_DQS_N<4>MEM_80DMEM_B_DQS4

MEM_A_DQS_5 MEM_A_DQS_P<5>MEM_A_DQS5 MEM_80D

MEM_80D MEM_A_DQS_N<4>MEM_A_DQS4 MEM_A_DQS_4

MEM_A_DQS_4MEM_80D MEM_A_DQS_P<4>MEM_A_DQS4


MEM_A_A<15..0>MEM_A_CMD MEM_CMDMEM_45S

MEM_A_CKE<3..0>MEM_A_CTRL MEM_CTRLMEM_45S

MEM_A_CLK_P<5..0>MEM_A_CLK MEM_CLKMEM_72D


MEM_A_DQS_2MEM_A_DQS2 MEM_80D MEM_A_DQS_P<2>MEM_A_DQS_1 MEM_A_DQS_N<1>MEM_A_DQS1 MEM_80D

MEM_B_DQS_7 MEM_B_DQS_P<7>MEM_80DMEM_B_DQS7

MEM_B_DQS_P<0>MEM_B_DQS_0MEM_B_DQS0 MEM_80D

MEM_B_DQ<55..48>MEM_B_DATA_6MEM_B_DQ_BYTE6 MEM_45S

MEM_B_DQS_6MEM_B_DQS6 MEM_B_DQS_N<6>MEM_80D

MEM_B_DQS_P<5>MEM_B_DQS_5MEM_B_DQS5 MEM_80D

MEM_A_DQS_7 MEM_A_DQS_P<7>MEM_A_DQS7 MEM_80D


MEM_A_DQS_2MEM_A_DQS2 MEM_80D MEM_A_DQS_N<2>

MEM_A_DQS_1MEM_A_DQS1 MEM_80D MEM_A_DQS_P<1>



MEM_80D MEM_B_DQS_5 MEM_B_DQS_N<5>MEM_B_DQS5

MEM_B_DQ<39..32>MEM_B_DATA_4MEM_B_DQ_BYTE4 MEM_45SMEM_B_DQ<47..40>MEM_B_DATA_5MEM_B_DQ_BYTE5 MEM_45S

MEM_B_DQ<63..56>MEM_B_DATA_7MEM_B_DQ_BYTE7 MEM_45S

MEM_B_DQS_0MEM_B_DQS0 MEM_80D MEM_B_DQS_N<0>MEM_B_DQS_1MEM_B_DQS1 MEM_80D MEM_B_DQS_P<1>

MEM_B_DQS_N<1>MEM_B_DQS_1MEM_B_DQS1 MEM_80DMEM_B_DQS_P<2>MEM_B_DQS_2MEM_B_DQS2 MEM_80D

MEM_B_DQS_N<3>MEM_B_DQS_3MEM_80DMEM_B_DQS3

MEM_B_DQS_2MEM_B_DQS2 MEM_B_DQS_N<2>MEM_80DMEM_B_DQS_P<3>MEM_B_DQS_3MEM_B_DQS3 MEM_80D

MEM_B_DQS_P<4>MEM_B_DQS4 MEM_80D MEM_B_DQS_4

MEM_A_DATA_5MEM_A_DQ_BYTE5 MEM_45S MEM_A_DQ<47..40>MEM_A_DATA_4 MEM_A_DQ<39..32>MEM_A_DQ_BYTE4 MEM_45S

PP1V5_S3RS0MEM_PWR

MEM_B_CLK_N<5..0>MEM_B_CLK MEM_CLKMEM_72D




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Unused USB nets(USB_TPAD_HUB)

(USB_TPAD_HUB)

USB EXTB nets (Left USB port)

USB Camera nets

USB EXTA nets (Right USB port)

USB Hub nets

SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.8

USB 3.0 Interface Constraints

PCH Net Properties

PHYSICAL

NET_TYPE

SPACINGELECTRICAL_CONSTRAINT_SET

SATA Interface Constraints

SATA SSD

SOURCE: 471984_Chief_River_MS_PDG_1.0 and the spacing rule is adjusted per SI team feedback.

UART Interface Constraints

USB 2.0 Interface Constraints

SOURCE: 471984_Cheif_River_MS_PDG_1.0 and the spacing rule is adjusted per SI team feedback.

=80_OHM_DIFF =80_OHM_DIFF=80_OHM_DIFF=80_OHM_DIFF=80_OHM_DIFF* =80_OHM_DIFFUSB_80D

* ?USB3_TX2TX =2.5x_DIELECTRICUSB3_2OTHERUSB3_PCH_TX **

USB3_PCH_RX **_RX USB3_2OTHERHS

USB3_2OTHERUSB3_PCH_RX **

USB3_PCH_TX **_RX USB3_2OTHERHS

USB3_PCH_TX **_TX USB3_2OTHERHS

USB3_PCH_RX **_TX USB3_2OTHERHS

USB3_TX2RXUSB3_PCH_TX **_PCH_RX

USB3_RX2OTHERRXUSB3_PCH_RX **_PCH_RX

USB3_PCH_TX USB3_TX2OTHERTX**_PCH_TX

USB3_RX2TXUSB3_PCH_RX **_PCH_TX

USB3_TX2TXUSB3_PCH_TXUSB3_PCH_TX *

* ?USB3_2OTHERHS =4x_DIELECTRIC

* =3x_DIELECTRICUSB3_2OTHER ?

* =6x_DIELECTRIC ?USB3_RX2TX

* =4x_DIELECTRIC ?USB3_RX2OTHERRX

* =4x_DIELECTRIC ?USB3_TX2OTHERTX

* =6x_DIELECTRIC ?USB3_TX2RX

* =2.5x_DIELECTRIC ?USB3_RX2RX

TOP,BOTTOMUSB3_2OTHER ?=5x_DIELECTRIC

USB3_2OTHERHS =6x_DIELECTRIC ?TOP,BOTTOM

=7x_DIELECTRICUSB3_RX2TX ?TOP,BOTTOM

USB3_TX2RX TOP,BOTTOM ?=7x_DIELECTRIC

USB3_RX2OTHERRX ?=5x_DIELECTRICTOP,BOTTOM

TOP,BOTTOMUSB3_TX2OTHERTX ?=5x_DIELECTRIC

=5x_DIELECTRICUSB3_RX2RX ?TOP,BOTTOM

USB3_TX2TX ?=5x_DIELECTRICTOP,BOTTOM

?USB =4x_DIELECTRICTOP,BOTTOM

=45_OHM_SE=45_OHM_SE =45_OHM_SE=45_OHM_SE=45_OHM_SE=45_OHM_SE*UART_45S

=2x_DIELECTRICUART ?*

?* =3x_DIELECTRICSATA3_2OTHER

=4x_DIELECTRICSATA3_2OTHERHS * ?

?* =6x_DIELECTRICSATA3_TX2RX

* ?SATA3_RX2OTHERRX =4x_DIELECTRIC

?* =2.5x_DIELECTRICSATA3_RX2RX

?* =2.5x_DIELECTRICSATA3_TX2TX

* ?=6x_DIELECTRICSATA3_RX2TX

?TOP,BOTTOMSATA3_2OTHERHS =6x_DIELECTRIC

?TOP,BOTTOMSATA3_RX2TX =7x_DIELECTRIC

SATA3_TX2RX TOP,BOTTOM ?=7x_DIELECTRIC

?SATA3_RX2OTHERRX TOP,BOTTOM =5x_DIELECTRIC

SATA3_2OTHER TOP,BOTTOM ?=5x_DIELECTRIC

SATA3_TX2OTHERTX TOP,BOTTOM ?=5x_DIELECTRIC

SATA3_RX2RX ?=5x_DIELECTRICTOP,BOTTOM

TOP,BOTTOMSATA3_TX2TX ?=5x_DIELECTRIC

SATA3_2OTHER**SATA3_PCH_RX

**SATA3_PCH_TX SATA3_2OTHER

*_RX SATA3_2OTHERHS*SATA3_PCH_RX

*SATA3_PCH_TX *_TX SATA3_2OTHERHS

* SATA3_RX2RXSATA3_PCH_RXSATA3_PCH_RX

**_PCH_RX SATA3_TX2RXSATA3_PCH_TX

**_PCH_RX SATA3_RX2OTHERRXSATA3_PCH_RX

* SATA3_TX2TXSATA3_PCH_TXSATA3_PCH_TX

*_PCH_TX * SATA3_TX2OTHERTXSATA3_PCH_TX

*_PCH_TX SATA3_RX2TX*SATA3_PCH_RX

=4x_DIELECTRICSATA_ICOMP * ?

=80_OHM_DIFFSATA_80D =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF* =80_OHM_DIFF =80_OHM_DIFF

SATA3_TX2OTHERTX ?* =4x_DIELECTRIC

SATA3_2OTHERHSSATA3_PCH_TX *_RX *

* SATA3_2OTHERHSSATA3_PCH_RX *_TX

USB3_RX2RXUSB3_PCH_RXUSB3_PCH_RX *

?USB * =2x_DIELECTRIC

=STANDARD=STANDARD* =STANDARD 8 MIL =STANDARD8 MILPCH_USB_RBIAS

SYNC_DATE=01/11/2012SYNC_MASTER=CONSTRAINTS

PCH Constraints 1

SATA_SSD_R2D_MUX_IN_NSATA3_PCH_TXSATA_80D

SATA_PCH_MUX_R2D SATA_HDD_R2D_C_NSATA3_PCH_TXSATA_80DSATA_SSD_R2D_MUX_IN_PSATA3_PCH_TXSATA_80D

SATA_MUX_SSD_R2D SATA_SSD_R2D_PSATA_80D SATA3_PCH_TX

SATA_MUX_SSD_R2D SATA_80D SATA_SSD_R2D_NSATA3_PCH_TX

SATA_PCH_MUX_R2D SATA3_PCH_TX SATA_HDD_R2D_C_PSATA_80D

SATA3_PCH_RX SATA_SSD_D2R_MUX_OUT_PSATA_80D

SATA_80D SATA3_PCH_RX SATA_HDD_D2R_PSATA_PCH_MUX_D2R

SATA_80D SATA_HDD_D2R_NSATA3_PCH_RXSATA_PCH_MUX_D2R

SATA3_PCH_RX SATA_SSD_D2R_MUX_OUT_NSATA_80D

SATA_MUX_SSD_D2R SATA_SSD_D2R_PSATA_80D SATA3_PCH_RX

SATA_MUX_SSD_D2R SATA_80D SATA_SSD_D2R_NSATA3_PCH_RX

SATA_ICOMPPCH_SATA_ICOMP PCH_SATAICOMP

USBUSB_HUB1_UP USB_HUB_UP_NUSB_80D

USBUSB_HUB1_UP USB_80D USB_HUB_UP_P

USB_BT_NUSB_80D USBUSB_BT

USB_BT_PUSB_80D USBUSB_BT

USB_BT_WAKE_PUSBUSB_80D

USB_BT_CONN_PUSBUSB_80DUSB_BT_CONN_NUSBUSB_80D

USB_TPAD_PUSBUSB_80DUSB_TPAD

USB_BT_WAKE_NUSBUSB_80D

USB_TPAD_NUSBUSB_80DUSB_TPADUSB_TPAD_CONN_PUSB_80D USBUSB_TPAD_CONN_NUSB_80D USB

USB_80D USB_TPAD_HUB_PUSBUSB_TPAD_HUBUSB_TPAD_HUB_NUSB_80D USBUSB_TPAD_HUB

USBUSB_80D USB_TPAD_R_P

USB_TPAD_M_PUSB_80D USBUSB_TPAD_M

USBUSB_80D USB_TPAD_R_N

USB_SDCARD_NUSBUSB_80DUSB_SDCARD

USB_TPAD_M_NUSB_80D USBUSB_TPAD_MUSB_SDCARD_PUSBUSB_80DUSB_SDCARD

USB_SMC_PUSB_80D USBUSB_SMCUSB_SMC_NUSB_80D USBUSB_SMC

USB_CAMERA_NUSB_80D USBUSB_CAMERA

USB_CAMERA_PUSB_80D USBUSB_CAMERA

USB_EXTA_PUSBUSB_80DUSB_EXTA

SMC_DEBUGPRT_RX_LUART_45S UART

USB3_EXTA_RX_F_NUSB3_PCH_RXUSB_80D

USB3_EXTA_TX_F_NUSB_80D USB3_PCH_TX

USB3_EXTA_TX_F_PUSB_80D USB3_PCH_TX

USB3_EXTA_TX_C_NUSB_80D USB3_PCH_TX

USB_80D USB2_EXTA_MUXED_PUSBUSB2_EXTA_MUXED_NUSB_80D USB

USB_80D USB2_EXTA_MUXED_F_PUSBUSB2_EXTA_MUXED_F_NUSB_80D USB

USB3_PCH_RXUSB3_EXTA_RX USB3_EXTA_RX_PUSB_80D

USB3_PCH_RX USB3_EXTA_RX_NUSB3_EXTA_RX USB_80D

USB3_EXTA_TX USB3_EXTA_TX_PUSB_80D USB3_PCH_TXUSB3_EXTA_TX_NUSB3_EXTA_TX USB3_PCH_TXUSB_80D

USB3_EXTA_TX_C_PUSB_80D USB3_PCH_TX

USB3_PCH_RXUSB_80D USB3_EXTA_RX_F_P

USB_EXTD_XHCI_PUSBUSB_80D

USBUSB_80D USB_EXTD_XHCI_N

PCH_USB_RBIASPCH_USB_RBIASPCH_USB_RBIASPCIE_CLK100M_PCH_PCLK_PCIE_80D CLK_PCIEPCH_DIFFCLK_UNUSED_PCIE_CLK100M_PCH_NCLK_PCIE_80DPCH_DIFFCLK_UNUSED_ CLK_PCIE

CLK_PCIE_80D PCH_CLK96M_DOT_PCLK_PCIEPCH_DIFFCLK_UNUSED_

CLK_PCIE_80D PCH_CLK100M_SATA_PCLK_PCIEPCH_DIFFCLK_UNUSED_

PCH_CLK96M_DOT_NCLK_PCIE_80D CLK_PCIEPCH_DIFFCLK_UNUSED_

CPU_45S PCH_CLK14P3M_REFCLKCLK_PCIE

PCH_CLK100M_SATA_NPCH_DIFFCLK_UNUSED_ CLK_PCIECLK_PCIE_80D

USB_80D USB3_PCH_RX USB3_EXTB_RX_CONN_P

USB3_PCH_TXUSB_80DUSB3_EXTB_TX USB3_EXTB_TX_N

USB3_PCH_RXUSB_80D USB3_EXTB_RX_CONN_NUSB3_PCH_TXUSB_80DUSB3_EXTB_TX USB3_EXTB_TX_P

USB3_PCH_TXUSB_80D USB3_EXTB_TX_C_NUSB3_PCH_TXUSB_80D USB3_EXTB_TX_C_P

USB_80D USB USB_EXTB_XHCI_P

USB3_EXTB_RX USB3_PCH_RXUSB_80D USB3_EXTB_RX_PUSBUSB_80D USB_EXTB_XHCI_N

USBUSB_80D USB_EXTB_EHCI_PUSB_EXTB USBUSB_80D USB_EXTB_N

USBUSB_80D USB_EXTB_EHCI_N

USB_80DUSB_EXTB USB USB_EXTB_P

USB_80D USB3_PCH_RXUSB3_EXTB_RX USB3_EXTB_RX_N

USB_80D USB3_PCH_RX USB3_EXTB_RX_RC_NUSB_80D USB3_PCH_RX USB3_EXTB_RX_RC_P

USB_EXTA_NUSBUSB_80DUSB_EXTASMC_DEBUGPRT_TX_LUARTUART_45S

051-9276

2.7.0

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SIO Signal Constraints


SMBus Interface Constraints

SPI Interface Constraints

XDP Constraints

LPC Bus Constraints

SPACING

NOTE: 25MHz system clocks very sensitive to noise.

HD Audio Interface Constraints

PHYSICAL

PCH Net PropertiesNET_TYPE

ELECTRICAL_CONSTRAINT_SET PHYSICAL

NET_TYPE

SPACING

System Clock Signal Constraints


Chipset Net Properties


Clock Net Properties

PHYSICAL

NET_TYPE

SPACING

DisplayPort

=45_OHM_SECLK_SLOW_45S =STANDARD=STANDARD* =45_OHM_SE =45_OHM_SE =45_OHM_SE

CLK_25M_45S =STANDARD=STANDARD* =45_OHM_SE =45_OHM_SE =45_OHM_SE =45_OHM_SE


PCH Constraints 2


DP_2OTHER*DP_TX *

*_RX *DP_TX DP_2OTHERHS

DP_2DPDP_TXDP_TX *

*DP_TX *_TX DP_2OTHERHS

=3x_DIELECTRIC* ?DP_2OTHER

DP_AUX * ?=3x_DIELECTRIC

* ?DP_2OTHERHS =4x_DIELECTRIC

?* =3x_DIELECTRICDP_2DP

=80_OHM_DIFF =80_OHM_DIFF* =80_OHM_DIFF =80_OHM_DIFFDP_80D =80_OHM_DIFF =80_OHM_DIFF

TOP,BOTTOM =4x_DIELECTRIC ?DP_2OTHER

?=4x_DIELECTRICTOP,BOTTOMDP_AUX

TOP,BOTTOM ?DP_2OTHERHS =6x_DIELECTRIC

DP_2DP ?=4x_DIELECTRICTOP,BOTTOM

=STANDARD=45_OHM_SE =STANDARDCLK_SLOW_45S * =45_OHM_SE =45_OHM_SE =45_OHM_SE

CLK_LPC_45S =45_OHM_SE =45_OHM_SE =STANDARD=STANDARD* =45_OHM_SE=45_OHM_SE

LPC =3x_DIELECTRIC ?*

=4x_DIELECTRIC*CLK_LPC ?

=45_OHM_SE =STANDARD*HDA_45S =45_OHM_SE =45_OHM_SE =45_OHM_SE =STANDARD

CLK_25M ?=5x_DIELECTRIC*

=STANDARD=STANDARD* =45_OHM_SE=45_OHM_SE=45_OHM_SE =45_OHM_SELPC_45S

=50_OHM_SE =50_OHM_SE=50_OHM_SE=50_OHM_SETOP,BOTTOMSMB_45S_R_50S

?=2x_DIELECTRIC*SMB

HDA ?=2x_DIELECTRIC*

=2x_DIELECTRICCLK_SLOW ?*

CLK_SLOW =4x_DIELECTRIC ?*

=2:1_SPACING ?PCH_ITP *

=4x_DIELECTRIC ?SPI *

=45_OHM_SE =45_OHM_SE=45_OHM_SE =STANDARD =STANDARD*SPI_45S =45_OHM_SE

=STANDARD=45_OHM_SEPCH_45S =45_OHM_SE* =STANDARD=45_OHM_SE=45_OHM_SE

=45_OHM_SE =STANDARD =STANDARD* =45_OHM_SE=45_OHM_SE=45_OHM_SESMB_45S_R_50S

CLK_SLOW SYSCLK_CLK32K_RTCCLK_SLOW_45SSYSCLK_CLK32K_RTC

SYSCLK_CLK25M_SBCLK_25M_45S CLK_25MSYSCLK_CLK25M_SB

CLK_25M_45S SYSCLK_CLK25M_SB_RCLK_25M

SYSCLK_CLK25M_TBT CLK_25M_45S CLK_25M SYSCLK_CLK25M_TBTSYSCLK_CLK25M_TBT_RCLK_25MCLK_25M_45S

SYSCLK_CLK25M_X1SYSCLK_CLK25M_XTAL CLK_25MCLK_25M_45SSYSCLK_CLK25M_X2CLK_25MCLK_25M_45SSYSCLK_CLK25M_X2_RCLK_25M_45S CLK_25M

DP_TBTSNK1_AUXCH_C_NDP_80D DP_AUX

DP_TBTSNK1_AUXCH_C_PDP_80D DP_AUX

DP_TBT_AUXCH DP_TBTSNK1_AUXCH_NDP_80D DP_AUX

DP_TBT_AUXCH DP_TBTSNK1_AUXCH_PDP_80D DP_AUX

DP_80D DP_TX DP_TBTSNK1_ML_C_N<3..0>DP_80D DP_TX DP_TBTSNK1_ML_C_P<3..0>

DP_TBT_ML DP_80D DP_TX DP_TBTSNK1_ML_N<3..0>DP_TBT_ML DP_TXDP_80D DP_TBTSNK1_ML_P<3..0>

DP_AUX DP_TBTSNK0_AUXCH_C_NDP_80D

DP_TBTSNK0_AUXCH_C_PDP_AUXDP_80D

DP_AUXDP_TBT_AUXCH DP_TBTSNK0_AUXCH_NDP_80D

DP_TBT_AUXCH DP_TBTSNK0_AUXCH_PDP_AUXDP_80D

DP_TBTSNK0_ML_C_N<3..0>DP_TXDP_80D

DP_TBTSNK0_ML_C_P<3..0>DP_TXDP_80D

DP_TBTSNK0_ML_N<3..0>DP_TBT_ML DP_TXDP_80D

DP_TBTSNK0_ML_P<3..0>DP_TBT_ML DP_TXDP_80DLPC_AD<3..0>LPCLPC_45SLPC_AD

SML_PCH_0_DATASMBSMBUS_PCH_0_DATA SMB_45S_R_50S

SPI_MLB_CS_LSPI_45S SPI

PCIE_TBT_R2D_P<3..0>PCIE_80D PCIE_PCH_TXPCIE_TBT_R2D

PCIE_TBT_R2D_C_P<3..0>PCIE_PCH_TXPCIE_80D

PEG_CLK100M_NCLK_PCIE_80D CLK_PCIE

PCIE_CLK100M_AP CLK_PCIE_80D CLK_PCIE PCIE_CLK100M_AP_P

PCIE_AP_D2R_PPCIE_PCH_RXPCIE_80DPCIE_AP_D2R

SPI_SMC_CS_LSPISPI_45S

LPC LPC_FRAME_LLPC_45SLPC_FRAME_LLPCPLUS_RESET_LLPCLPC_45S

LPC_CLK33M PCH_CLK33M_PCIINCLK_LPCCLK_LPC_45S

SMBUS_PCH_DATASMBUS_PCH_DATA SMBSMB_45S_R_50S

SMB_45S_R_50S SML_PCH_0_CLKSMBSMBUS_PCH_0_CLK

SML_PCH_1_CLKSMB_45S_R_50S SMBSMBUS_SMC_1_S0_SCLSML_PCH_1_DATASMB_45S_R_50S SMBSMBUS_SMC_1_S0_SDA

LPC_CLK33M CLK_LPC_45S LPC_CLK33M_LPCPLUSCLK_LPC

LPC_CLK33M_SMC_RCLK_LPCCLK_LPC_45S

CLK_LPC LPC_CLK33M_SMCCLK_LPC_45SLPC_CLK33M

CLK_SLOW_45S CLK_SLOW SMC_CLK32K

HDA_SDOUT_RHDAHDA_45S

HDA_SDOUT HDA_SDOUTHDA_45S HDA

HDA_SDIN0 HDA_SDIN0HDAHDA_45S

CLK_SLOWCLK_SLOW_45SPM_SUS_CLK PM_CLK32K_SUSCLK_R

SPI_MOSISPISPI_45S

SPI_MOSI_RSPI_MOSI SPI_45S SPI

CLK_LPC LPC_CLK33M_LPCPLUS_RCLK_LPC_45S

PCH_CLK33M_PCIOUTCLK_LPCCLK_LPC_45S

HDA_SYNCHDA_45S HDAHDA_SYNC

HDA_45S HDA HDA_RST_L

SPI_CLKSPI_45S SPI

SPISPI_45S SPI_SMC_CLK

SPI_45S SPI SPI_MLB_MOSISPI_MLB_MISOSPI_45S SPI

HDA_BIT_CLKHDAHDA_BIT_CLK HDA_45S

SMBUS_PCH_CLKSMBUS_PCH_CLK SMBSMB_45S_R_50S

PCIE_AP_R2D_C_PPCIE_PCH_TXPCIE_80D

PCIE_AP_R2D_NPCIE_AP_R2D PCIE_80D PCIE_PCH_TX

PCIE_AP_R2D_PPCIE_AP_R2D PCIE_80D PCIE_PCH_TX

SPI SPI_CS0_LSPI_45S

SPI_CLK_RSPI_CLK SPISPI_45S

HDAHDA_RST_L HDA_RST_R_LHDA_45S

HDA_45S HDA_SYNC_RHDA

HDA_BIT_CLK_RHDA_45S HDA

PCIE_TBT_R2D_C_N<3..0>PCIE_80D PCIE_PCH_TX

PCH_45S PCH_ITPXDP_TMS XDP_PCH_TMS

SPI_SMC_MOSISPISPI_45SSPI_SMC_MISOSPISPI_45S

PCIE_AP_R2D_C_NPCIE_PCH_TXPCIE_80D

CLK_PCIE_80D CLK_PCIEPCIE_CLK100M_AP PCIE_CLK100M_AP_N

PEG_CLK100M_PCLK_PCIE_80D CLK_PCIE

PCH_ITPPCH_45S XDP_PCH_TDOXDP_TDO

PCH_ITPPCH_45S XDP_PCH_TCKXDP_TCK

SPI_MISOSPISPI_45SSPI_MISO

SPI_45S SPI_CS0_R_LSPISPI_CS0

SPI_MLB_CLKSPISPI_45S

PCIE_PCH_RXPCIE_AP_D2R PCIE_80D PCIE_AP_D2R_N

PCIE_TBT_D2R_N<3..0>PCIE_PCH_RXPCIE_TBT_D2R PCIE_80D

CLK_PCIECLK_PCIE_80DPCIE_CLK100M_TBT PCIE_CLK100M_TBT_NCLK_PCIEPCIE_CLK100M_TBT CLK_PCIE_80D PCIE_CLK100M_TBT_PPCIE_PCH_RXPCIE_80D PCIE_TBT_D2R_C_N<3..0>PCIE_PCH_RXPCIE_80D PCIE_TBT_D2R_C_P<3..0>

PCIE_TBT_R2D PCIE_TBT_R2D_N<3..0>PCIE_80D PCIE_PCH_TX

PCIE_TBT_D2R PCIE_PCH_RXPCIE_80D PCIE_TBT_D2R_P<3..0>

XDP_TDI PCH_ITP XDP_PCH_TDIPCH_45S

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Thunderbolt/DP Connector Signal Constraints

SPACINGPHYSICAL

NET_TYPE


NOTE: DisplayPort Physical/Spacing Constraints provided by Chipset or GPU page.

Thunderbolt SPI Signal Constraints

DisplayPort Signal Constraints Thunderbolt/DP Net Properties

Only used on hosts supporting Thunderbolt video-in

SPACING

Thunderbolt IC Net PropertiesNET_TYPE

PHYSICALELECTRICAL_CONSTRAINT_SET

Only used on dual-port hosts.

=STANDARD=STANDARD=45_OHM_SE=45_OHM_SE=45_OHM_SE=45_OHM_SE*TBT_SPI_45S

TOP,BOTTOM ?TBTDP_TX2TX =6x_DIELECTRIC

*TBTDP_RX TBTDP_TX2RXTBTDP_TX

TBTDP_RX2RX*TBTDP_RXTBTDP_RX

=80_OHM_DIFF=80_OHM_DIFF=80_OHM_DIFF=80_OHM_DIFF=80_OHM_DIFF*TBTDP_80D =80_OHM_DIFF

?=2x_DIELECTRIC*TBT_SPI

TBTDP_TX **_RX TBTDP_2OTHERHS

TBTDP_RX * TBTDP_2OTHERHS*_TX

?*TBTDP_2OTHERHS =6x_DIELECTRIC

* ?TBTDP_2OTHER =4x_DIELECTRIC

=4x_DIELECTRIC* ?TBTDP_RX2RX

=6x_DIELECTRIC* ?TBTDP_TX2RX

=4x_DIELECTRIC*TBTDP_TX2TX ?

*TBTDP_RXTBTDP_TX TBTDP_TX2RX

TOP,BOTTOM ?=6x_DIELECTRICTBTDP_2OTHER

TBTDP_RX * TBTDP_2OTHERHS*_RX

*TBTDP_TX * TBTDP_2OTHER

* *TBTDP_RX TBTDP_2OTHER

* TBTDP_2OTHERHS*_TXTBTDP_TX

TOP,BOTTOM ?TBTDP_RX2RX =6x_DIELECTRIC

?TOP,BOTTOM =10x_DIELECTRICTBTDP_2OTHERHS

TOP,BOTTOM ?TBTDP_TX2RX =10x_DIELECTRIC

SYNC_MASTER=CONSTRAINTS SYNC_DATE=01/11/2012

Thunderbolt Constraints

*TBTDP_TXTBTDP_TX TBTDP_TX2TX

DP_80D DP_TBTPA_ML_P<3..1:2>DP_TX

DP_80D DP_TBTPA_ML_N<3..1:2>DP_TX

DP_80D DP_TBTPA_ML_C_N<3>DP_TBTPA_ML3 DP_TX

DP_TX DP_A_LSX_ML_N<1>DP_80D

DP_TBTPA_ML_C_P<3>DP_TBTPA_ML3 DP_TXDP_80D

DP_TBTPA_ML_C_P<1>DP_TBTPA_ML1 DP_80D DP_TXDP_TBTPA_ML_C_N<1>DP_TBTPA_ML1 DP_80D DP_TX

DP_A_LSX_ML_P<1>DP_80D DP_TX

DP_A_AUXCH_DDC_NDP_80D DP_AUX

TBTDP_80D TBT_B_D2R1_AUXDDC_NTBTDP_RX

TBTDP_80D TBT_B_D2R1_AUXDDC_PTBTDP_RX

DP_80D DP_B_AUXCH_DDC_NDP_AUX

DP_80D DP_TBTPB_AUXCH_NDP_AUX

DP_80D DP_TBTPB_AUXCH_PDP_AUX

DP_80D DP_B_AUXCH_DDC_PDP_AUX

DP_80DTBT_B_AUXCH DP_TBTPB_AUXCH_C_NDP_AUX

DP_80DTBT_B_AUXCH DP_TBTPB_AUXCH_C_PDP_AUX

TBTDP_80DTBT_B_D2R TBT_B_D2R_N<1..0>TBTDP_RX

TBT_B_D2R TBTDP_80D TBT_B_D2R_P<1..0>TBTDP_RX

TBTDP_80D TBT_B_D2R_C_N<1..0>TBTDP_RX

TBT_B_D2R_C_P<1..0>TBTDP_80D TBTDP_RX

DP_B_LSX_ML_P<1>DP_TXDP_80DDP_B_LSX_ML_N<1>DP_TXDP_80D

DP_TXDP_80D DP_TBTPB_ML_N<3..1:2>

DP_TXDP_80DDP_TBTPB_ML DP_TBTPB_ML_C_N<3..1:2>DP_TXDP_80D DP_TBTPB_ML_P<3..1:2>

DP_TXDP_80D DP_TBTPB_ML_C_P<3..1:2>DP_TBTPB_ML

TBTDP_80D TBT_B_R2D_P<1..0>TBTDP_TX

TBTDP_80D TBT_B_R2D_C_P<1..0>TBT_B_R2D TBTDP_TX

TBT_SPI_CS_L TBT_SPITBT_SPI_45S TBT_SPI_CS_LTBT_SPITBT_SPI_45STBT_SPI_MISO TBT_SPI_MISOTBT_SPITBT_SPI_45STBT_SPI_MOSI TBT_SPI_MOSITBT_SPITBT_SPI_45STBT_SPI_CLK TBT_SPI_CLK

DP_AUXDP_80D DP_TBTSRC_AUXCH_C_NDP_AUXDP_80D DP_TBTSRC_AUXCH_C_PDP_TXDP_80D DP_TBTSRC_ML_C_N<3..0>DP_TXDP_80D DP_TBTSRC_ML_C_P<3..0>

TBTDP_80D TBT_A_R2D_P<1..0>TBTDP_TX

TBTDP_80D TBT_A_R2D_N<1..0>TBTDP_TX

TBTDP_80DTBT_A_R2D TBT_A_R2D_C_N<1..0>TBTDP_TX

TBTDP_80DTBT_A_R2D TBT_A_R2D_C_P<1..0>TBTDP_TX

TBTDP_80D TBT_B_R2D_N<1..0>TBTDP_TX

TBTDP_80DTBT_B_R2D TBT_B_R2D_C_N<1..0>TBTDP_TX

TBT_A_D2R1_AUXDDC_NTBTDP_80D TBTDP_RX

TBT_A_D2R1_AUXDDC_PTBTDP_80D TBTDP_RX

TBT_A_D2R_C_N<1..0>TBTDP_80D TBTDP_RX

DP_A_AUXCH_DDC_PDP_80D DP_AUX

DP_80D DP_TBTPA_AUXCH_NDP_AUX

DP_80D DP_TBTPA_AUXCH_PDP_AUX

DP_TBTPA_AUXCH_C_NTBT_A_AUXCH DP_80D DP_AUX

DP_TBTPA_AUXCH_C_PDP_80DTBT_A_AUXCH DP_AUX

TBTDP_80D TBT_A_D2R_N<0>TBT_A_D2R0 TBTDP_RX

TBTDP_80D TBT_A_D2R_P<0>TBT_A_D2R0 TBTDP_RX

TBTDP_80D TBT_A_D2R_N<1>TBT_A_D2R1 TBTDP_RX

TBT_A_D2R_P<1>TBT_A_D2R1 TBTDP_80D TBTDP_RX

TBT_A_D2R_C_P<1..0>TBTDP_80D TBTDP_RX

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SMBus Charger Net Properties


NET_TYPE


SPACING

SPACINGPHYSICAL

NET_TYPE

PHYSICAL

SMC SMBus Net Properties

0.1 MM=STANDARD =STANDARD=STANDARD* =STANDARD 0.1 MM1:1_DIFFPAIR


SMC Constraints

SMB_45S_R_50S SMBUS_SMC_3_SDASMBSMBUS_SMC_3_SDA

SMB_45S_R_50S SMB SMBUS_SMC_3_SCLSMBUS_SMC_3_SCL

SMBUS_SMC_5_G3_SDA SMB SMBUS_SMC_5_G3_SDASMB_45S_R_50S

SMBUS_SMC_5_G3_SCL SMB SMBUS_SMC_5_G3_SCLSMB_45S_R_50S

SMB_45S_R_50S SMB SMBUS_SMC_2_S3_SDASMBUS_SMC_2_S3_SDA

SMB_45S_R_50S SMB SMBUS_SMC_2_S3_SCLSMBUS_SMC_2_S3_SCL

SMBSMBUS_SMC_0_S0_SDA SMBUS_SMC_0_S0_SDASMB_45S_R_50S

SMBSMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SCLSMB_45S_R_50S

1:1_DIFFPAIR CHGR_CSI_PSENSE_DIFFPAIR

CHGR_CSO_P1:1_DIFFPAIRSENSE_DIFFPAIRCHGR_CSO_N1:1_DIFFPAIRSENSE_DIFFPAIR

1:1_DIFFPAIR CHGR_CSI_R_N1:1_DIFFPAIR CHGR_CSI_R_P1:1_DIFFPAIR CHGR_CSI_NSENSE_DIFFPAIR

1:1_DIFFPAIR CHGR_CSO_R_P1:1_DIFFPAIR CHGR_CSO_R_N

SMB_45S_R_50S SMBUS_SMC_1_S0_SDASMBSMBUS_SMC_1_S0_SDA

SMB_45S_R_50S SMBUS_SMC_1_S0_SCLSMBSMBUS_SMC_1_S0_SCL

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J11/J13 Specific Net Properties

PHYSICAL SPACING

NET_TYPE



Project Specific Constraints

GND_P2MM*LVDS*GND0.20 MM*GND_P2MM 1000

PWR_P2MM*SATA*SB_POWER

PWR_P2MM 10000.20 MM*

PWR_P2MMSATA* *SB_POWER

THERM =2:1_SPACING ?*

GND * =STANDARD ?

*AUDIO =2:1_SPACING ?

*SENSE =2:1_SPACING ?

=1:1_DIFFPAIRSPKR_DIFFPAIR * =1:1_DIFFPAIR =1:1_DIFFPAIR0.100 MM =1:1_DIFFPAIR0.300 MM

* =1:1_DIFFPAIRTHERM_1TO1_45S =1:1_DIFFPAIR =1:1_DIFFPAIR=45_OHM_SE=45_OHM_SE =45_OHM_SE

=1:1_DIFFPAIR =1:1_DIFFPAIR* =1:1_DIFFPAIRSENSE_1TO1_P2MM 0.100 MM =1:1_DIFFPAIR0.200 MM

SENSE_1TO1_45S =1:1_DIFFPAIR=45_OHM_SE=45_OHM_SE* =1:1_DIFFPAIR=1:1_DIFFPAIR =45_OHM_SE

GND *CPU_COMP GND_P2MM

CPU_VCCSENSE GND_P2MMGND *

CLK_PCIE *GND GND_P2MM

* GND_P2MMPCIE*GND

GND_P2MM*GND SATA*

USB* GND_P2MM*GND

PWR_P2MM*CLK_PCIESB_POWER

SPKRAMP_ROUT_PSPKR_OUT AUDIOSPKR_DIFFPAIR

MAX98300_R_N1:1_DIFFPAIR AUDIO

MAX98300_R_P1:1_DIFFPAIR AUDIO

AUD_DIFF 1:1_DIFFPAIR AUDIO SPKRAMP_INR_NAUD_DIFF 1:1_DIFFPAIR AUDIO SPKRAMP_INR_P

PP3V3_S0SB_POWER

PP3V3_S5SB_POWER

SPKR_OUT AUDIOSPKR_DIFFPAIR SPKRAMP_ROUT_N

SENSE_1TO1_45S ISNS_LCDBKLT_PSENSESENSE_DIFFPAIR

SENSE_1TO1_45S SENSESENSE_DIFFPAIR ISNS_LCDBKLT_N

SENSE_DIFFPAIR ISNS_SSD_PSENSE_1TO1_45S SENSE

SENSE_DIFFPAIR SENSESENSE_1TO1_45S ISNS_HS_COMPUTING_P

ISNS_SSD_NSENSESENSE_1TO1_45SSENSE_DIFFPAIR

SENSE ISNS_AIRPORT_PSENSE_DIFFPAIR SENSE_1TO1_45S

SENSE_1TO1_45SSENSE_DIFFPAIR ISNS_HS_COMPUTING_NSENSE

SENSE_1TO1_P2MMSENSE_DIFFPAIR SENSE CPUIMVP_ISUM_N

SENSE_DIFFPAIR SENSESENSE_1TO1_45S ISNS_AIRPORT_N

SENSE_1TO1_45S ISNS_1V5_S3_PSENSESENSE_DIFFPAIR

SENSE_DIFFPAIR ISNS_HS_OTHER_NSENSE_1TO1_45S SENSE

SENSE_DIFFPAIR SENSE CPUIMVP_ISUM_PSENSE_1TO1_P2MM

SENSE_1TO1_P2MMSENSE_DIFFPAIR SENSE VCCSAS0_CS_NSENSE_1TO1_45S SENSE VCCSAISNS_R_P

SENSE_DIFFPAIR SENSE ISNS_3V3S0_PSENSE_1TO1_45S

SENSESENSE_1TO1_45S ISNS_3V3S0_R_N

SENSE_DIFFPAIR SENSESENSE_1TO1_P2MM CPUIMVP_ISUMG_N

THERM_1TO1_45S TBT_MLBBOT_THMSNS_NTHERM

TBT_THERMD_PTHERMTHERM_1TO1_45SSENSE_DIFFPAIR

SENSE_DIFFPAIR THERMTHERM_1TO1_45S TBT_THERMD_NTHERMTHERM_1TO1_45S TBT_MLBBOT_THMSNS_P

SENSE_1TO1_P2MMSENSE_DIFFPAIR SENSE VCCSAS0_CS_P

SENSE_1TO1_45S CPUIMVP_ISUMG_R_NSENSE

SENSE_DIFFPAIR SENSE_1TO1_45S ISNS_HS_OTHER_PSENSE

SENSE_1TO1_45S CPUIMVP_ISUMG_R_PSENSE

CPUIMVP_ISUM_R_NSENSESENSE_1TO1_45S

CPUIMVP_ISNS1_PSENSE_1TO1_P2MM SENSESENSE_DIFFPAIR

SENSE_DIFFPAIR SENSESENSE_1TO1_P2MM CPUVCCIOS0_CS_N

CPU_THERMD_NSENSESENSE_1TO1_45SSENSE_DIFFPAIR

SENSE_DIFFPAIR SENSE_1TO1_P2MM SENSE CPUIMVP_ISUMG_P

SENSE_DIFFPAIR SENSESENSE_1TO1_45S ISNS_3V3S0_N

SENSE_1TO1_45S SENSE VCCSAISNS_R_N

CPUIMVP_ISUM_R_PSENSESENSE_1TO1_45S

CPUIMVP_ISNS1_NSENSE_DIFFPAIR SENSESENSE_1TO1_P2MM

SENSE_DIFFPAIR CPUIMVP_ISNS1G_NSENSESENSE_1TO1_P2MM

SENSE_DIFFPAIR CPUIMVP_ISNS1G_PSENSESENSE_1TO1_P2MM

ISNS_1V5_S3_NSENSE_DIFFPAIR SENSE_1TO1_45S SENSE

SENSE_DIFFPAIR CPU_THERMD_PSENSESENSE_1TO1_45S

THERM TBTTHMSNS_D2_R_NTHERM_1TO1_45S

SENSESENSE_1TO1_45SSENSE_DIFFPAIR CPUTHMSNS_D2_PSENSESENSE_1TO1_45SSENSE_DIFFPAIR CPUTHMSNS_D2_N

CPUVCCIOS0_CS_PSENSE_DIFFPAIR SENSE_1TO1_P2MM SENSE

THERM TBTTHMSNS_D2_R_PTHERM_1TO1_45S

SENSE_DIFFPAIR INLET_THMSNS_D1_NTHERMTHERM_1TO1_45S

INLET_THMSNS_D1_PTHERMTHERM_1TO1_45SSENSE_DIFFPAIR

SENSESENSE_1TO1_45S ISNS_3V3S0_R_P

GND GND

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TABLE_BOARD_INFO

VERSIONALLEGRO

(MIL or MM)BOARD UNITSBOARD LAYERS BOARD AREAS

























































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J11/J13 Board-Specific Spacing & Physical Constraints

Spacing Constraints

Differential Pair Physical Constraints

Single-ended Physical Constraints

27P4_OHM_SE N* 100 MM 100 MM =STANDARD=STANDARD=STANDARD

ISL4,ISL9 Y27P4_OHM_SE 0.182 MM0.182 MM

0.182 MMYISL3,ISL10 0.182 MM27P4_OHM_SE

Y27P4_OHM_SE 0.182 MM 0.182 MMISL2,ISL11

Y27P4_OHM_SE 0.310 MM0.310 MMTOP,BOTTOM

=DEFAULT =DEFAULTSTANDARD * =DEFAULT =DEFAULT =DEFAULT=DEFAULT

PCB Rule Definitions


DEFAULT TOP,BOTTOM =50_OHM_SE=50_OHM_SEY

1x_DIELECTRIC ISL4,ISL9 0.050 MM ?

* 0.090 MM ?1x_DIELECTRIC

STANDARD =DEFAULT ?*

*BGA_P2MM ?=DEFAULT

BGA_P1MM ?=DEFAULT*

TOP,BOTTOM Y 0.195 MM0.195 MM35_OHM_SE

YISL3,ISL10 0.125 MM 0.125 MM35_OHM_SE

0.125 MM35_OHM_SE Y 0.125 MMISL2,ISL11

YISL4,ISL935_OHM_SE 0.125 MM 0.125 MM

0.110 MM0.110 MM50_OHM_SE YTOP,BOTTOM

0.110 MM0.110 MM0.088 MM0.088 MMYISL4,ISL980_OHM_DIFF

100 MMN* =STANDARD =STANDARD =STANDARD80_OHM_DIFF 100 MM

=STANDARD=STANDARD=STANDARD* N72_OHM_DIFF 100 MM100 MM

Y 0.115 MM0.115 MM0.081 MM0.081 MM80_OHM_DIFF ISL2,ISL11

0.150 MM0.150 MM0.114 MM0.114 MMISL4,ISL9 Y72_OHM_DIFF



YTOP,BOTTOM72_OHM_DIFF 0.165 MM 0.130 MM 0.130 MM0.165 MM

100 MM100 MMN* =STANDARD =STANDARD50_OHM_SE =STANDARD



=STANDARD100 MM100 MMN* =STANDARD45_OHM_SE =STANDARD

ISL2,ISL11 Y45_OHM_SE 0.075 MM 0.075 MM

TOP,BOTTOM Y45_OHM_SE 0.135 MM 0.135 MM

0.099 MM0.099 MM40_OHM_SE YISL4,ISL9

100 MM100 MMN* =STANDARD =STANDARD40_OHM_SE =STANDARD

ISL2,ISL11 Y40_OHM_SE 0.096 MM 0.096 MM

TOP,BOTTOM Y40_OHM_SE 0.170 MM 0.170 MM

100 MMN*35_OHM_SE =STANDARD =STANDARD =STANDARD100 MM

DEFAULT ISL3,ISL10 Y =45_OHM_SE =45_OHM_SE

ISL2,ISL11DEFAULT Y =45_OHM_SE =45_OHM_SE

ISL4,ISL9DEFAULT Y =45_OHM_SE =45_OHM_SE

DEFAULT ?0.1 MM*

1x_DIELECTRIC ISL3,ISL10 0.053 MM ?

1x_DIELECTRIC TOP,BOTTOM 0.071 MM ?

100 MM 100 MMN* 10 MM 0 MM 0 MMDEFAULT

BGA_P2MMBGA*CLK_PCIE

BGA_P2MMBGA*CLK_SLOW

BGA_P2MMBGA*MEM_CLK

BGA_P1MMBGA**

1:1_SPACING * 0.100 MM ?

TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM NO_TYPE,BGA MM 16.2

Y 0.096 MM40_OHM_SE ISL3,ISL10 0.096 MM

55_OHM_SE TOP,BOTTOM 0.090 MMY 0.090 MM

0.115 MM0.115 MM0.081 MM0.081 MMYISL3,ISL1080_OHM_DIFF

TOP,BOTTOM 0.130 MM0.130 MM0.132 MM0.132 MMY80_OHM_DIFF

=STANDARD=STANDARD=STANDARD* N 100 MM55_OHM_SE 100 MM

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