ITRS Winter Public Conference, December3, Makuhari Messe, Japan 1ITRS Summer Conference, July 12, 2012, San Francisco, CA, USA

Modeling and Simulation ITWGLothar Pfitzner on behalf of

Jürgen Lorenz – Fraunhofer IISB, Germany – Chairperson M&S ITWG

ITWG/TWG MembersH. Jaouen, STM-FR. Minixhofer, austriamicrosystemsW. Molzer, Intel Mobile CommunicationsA. Benvenuti, MicronB. Huizing, NXPW. Lerch, centrothermW. Demmerle, Synopsys GermanyR. Gull, Synopsys SwitzerlandJ. Lorenz, Fraunhofer IISB (chairperson)A. De Keersgieter, IMECJ.-C. Barbe, LETIW. Grabinski, EPFL LausanneM. Ciappa, ETH ZurichT. Grasser, TU Vienna

S. Satoh, FujitsuN. Aoki, ToshibaN. Kotani, Hiroshima Int.Univ.

J. H. Choi, HynixJ.-K. Park, SamsungY. Kwon, SamsungY.S. Pang, MagnaChipH. Park, Synopsys KoreaK.R. Kim, UNISTS. Han, SNU

F. Benistant, Globalfoundries

Y.M. Sheu, TSMCC.S. Yeh, UMCI.C. Yang, MacronixM. Chang, Tsing-Hua Univ.

V. Singh, INTELC. Mouli, MicronD. Dunn, IBMS. Kincal, A. Nainani, Applied MaterialsR. Gafiteanu, MENTORV. Moroz, SynopsysG. Klimeck, Purdue

ITRS Winter Public Conference, December3, Makuhari Messe, Japan 2ITRS Summer Conference, July 12, 2012, San Francisco, CA, USA

Modeling & Simulation SCOPE & SCALES

Modeling Overall Goal• Support technology development and optimization• Reduce development times and costs

Equipment related• Equipment/Feature scale Modeling• Lithography Modeling

IC-scale• Circuit Elements Modeling• Package Simulation

• Interconnects and Integrated Passives Modeling

Feature scale• Front End Process

Modeling• Device Modeling

• Numerical Methods• Materials Modeling• Reliability Modeling• Modeling for Design Robustness,

Manufacturing and Yield

ITRS Winter Public Conference, December3, Makuhari Messe, Japan 3ITRS Summer Conference, July 12, 2012, San Francisco, CA, USA

Some Key Messages Mission of Modeling and Simulation as cross-cut topic: Support areas covered by other ITWGs Continued in-depth analysis of M&S needs of other ITWGs, based on documents + inter-ITWG discussions Strong links with ALL ITWGs – see also crosscut texts in 2011 ITRS

Modeling and simulation based on quantitative physical understanding of equipments/materials/processes/devices/circuits/systems tool for technology/device development & optimization and for training/education

One of the few methods which can reduce development times and costs

Delineation between M&S and ERD / ERM: Architectures to be addressed by M&S ITWG as soon as transferred from ERD/ERM to PIDS

2012 work: Update of M&S tables Prepare for new development time & cost reduction survey in 2013 Extended support to PIDS specs via new partner Purdue & others Continued trend to delay items observed: Necessary research could not be

done due to lack of resources (research funding)

ITRS Winter Public Conference, December3, Makuhari Messe, Japan 4ITRS Summer Conference, July 12, 2012, San Francisco, CA, USA

Development Time and Cost Reduction Estimate Answers on question for average reduction of development time and costs in

success case of simulation which occurred in environment of TCAD users.

Definition different from estimate before 2008 which referred to cost reduction potential and was based on earlier survey

New survey planned for 2013

ITRS Winter Public Conference, December3, Makuhari Messe, Japan 5ITRS Summer Conference, July 12, 2012, San Francisco, CA, USA

2012 Short-Term Difficult Challenges – no changes from 2011

Lithography Simulation including EUV

Example (Fraunhofer IISB): Large-area rigorous simulation of optical lithography

Mask layout(dark-blue = Cr absorber)

Mask scale = 4 times wafer scale

High resolution aerial image computed with Dr.LiTHO (Waveguide + new Imaging: 5.4 h on one CPU with 2.8 GHz. Additionally, efficient parallelization

possible ).

500 1000 1500 2000 2500

500

1000

1500

2000

2500

(nm)

(nm)

• Complementary lithography• Simulation of defect inspection and characterization, influences/defect printing. Mask

optimization including defect repair or compensation based on defect signature available from characterization. Multilayer defect propagation

• Simulation of resolution enhancement techniques including combined mask/source optimization (OPC, PSM) and including EMF and resist effects, and extensions for inverse lithography

• Models that bridge requirements of OPC (speed) and process development (predictive) including EMF effects, including high NA effects for EUV

• Predictive and separable resist models (e.g., mesoscale models) including line-edge roughness, accurate profiles, topcoat and substrate (underlayer) interactions, etch resistance, adhesion, mechanical stability, leaching, swelling or slimming, and time-dependent effects in in single and multiple exposure• Resist model parameter calibration methodology (including kinetic transport and

stochastic parameters)• Fast, predictive simulation of ebeam mask making (single-beam and multibeam)

including short and long range proximity corrections• Simulation of directed self-assembly of sublithography patterns, esp. guiding pattern

optimization and defect formation• Modeling lifetime effects of equipment and masks, including lens and mirror heating

effects• Predictive coupled deposition-lithography-etch simulation (incl. double patterning,

self-aligned patterning)• Modeling metrology equipment and data extraction for enhancing model calibration

accuracy• Modeling of pellicle effects and pellicle defects simulation (incl. double patterning,

self-aligned patterning)

ITRS Winter Public Conference, December3, Makuhari Messe, Japan 6ITRS Summer Conference, July 12, 2012, San Francisco, CA, USA

Use of lattice KMC in Sentaurus Process for simulation of epitaxy (source: Synopsys)

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2012 Short-Term Difficult ChallengesIntegrated modeling of equipment, materials, feature scale processes and

influences on device and circuit performance and reliability, including random and systematic variability – no changes from 2011

Linked Equipment-feature scale simulation (source: Fraunhofer IISB and IMS):

Top: Simulated density of Cl+ ions in the ICP reactor, simulated with ESI-CFD commercial package

Middle: Example for discretized geometry after partial etch of the polysilicon during the gate patterning process

Bottom: Experimental profiles for isolated lines

Etch bias

ITRS Winter Public Conference, December3, Makuhari Messe, Japan 8ITRS Summer Conference, July 12, 2012, San Francisco, CA, USA

2012 Short-Term Difficult Challenges Nanoscale /advanced MtM Device Simulation Capability: Methods, models and

algorithms – changes from 2011 in blue / red

courtesy Infineon / TU Munich

drain

source

courtesy Infineon / TU Munich

Handling of strain- and orientation-dependent hole mobility in SENTAURUS device (source: Synopsys)

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2012 Short-Term Difficult Challenges

Electrical-Thermal-Mechanical Modeling for Interconnects and Packaging – changes from 2011 in blue

Needs• Model thermal-mechanical, thermodynamic and electrical properties of low-k, high-k and conductors for efficient on-chip and off-chip incl. SIP and wafer level packages, including power management, and the impact of processing on these properties especially for interfaces and films under 1 micron dimension• Thermal modeling for 3D ICs and assessment of modeling and CAD tools capable of supporting 3D designs. Thermo-mechanical modeling of Through Silicon Vias and thin stacked dies (incl. adhesive/interposers), and their impact on active device properties (stress, expansion, keepout regions, …). Size effects (microstructure, surfaces, ...) and variability of thinned wafers.• Combined EM and drift diffusion simulation to include inductance effects in substrate caused by interconnects and bond wires• Signal integrity modeling for 3D ICs• Identify effects and apply/extend models which influence reliability of packages and interconnects incl. 3D integration (e.g. stress voiding, electromigration, fracture initiation, dielectric breakdown, piezoelectric effects)• Physical models and simulation tools to predict adhesion and fracture toughness on interconnect-relavant interfaces (homogeneous and heterogeneous), packages and die interfaces • Dynamic simulation of mechanical problems of flexible substrates and packages• Models for electron transport in ultra fine patterned interconnects• Simulation tools for die, package and board that allow for coherent co-design

Source: Synopsys

Temperature distribution in an interconnect structure.

Source: TU Vienna / IST project MULSIC

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2012 Short-term Difficult ChallengesCircuit Element and System Modeling for High Frequency (up to 300 Ghz)

Applications - changes from 2011 in blue / red

gate

g2

bulk

drain sources1 d1s2 s3 s4 s10 s9s8

No series resistanceNo DIBL,No static feedbackNo overlap capacitance

g1

R gate

R bulk, central

R bulk, drain R bulk, source

C jun,s C jun,d

b1

C gso C gdo

R source R drain

+

_ V

T1

(From NXP)

ITRS Winter Public Conference, December3, Makuhari Messe, Japan 11ITRS Summer Conference, July 12, 2012, San Francisco, CA, USA

2012 Difficult Challenges Changes from 2011 in blue

Nano-scale modeling for Emerging Research Devices and

interconnects including Emerging Research Materials

Optoelectronics Modeling

NGL Simulation

Modeling of chemical, thermomechanical and electrical

properties of new materials

ITRS Winter Public Conference, December3, Makuhari Messe, Japan 12ITRS Summer Conference, July 12, 2012, San Francisco, CA, USA

More details given in ITRS M&S tables

For questions, please contact Juergen.Lorenz@iisb.fraunhofer.de

Thank you