ipc designers council how can we help you and your local chapter be successful?

IPCDESIGNERS COUNCIL

How can we help you and your local Chapter

be successful?

2

Agenda

IPC History Overview Designers Council History Designer Training and Certification Chapter Activities Summit, Symposiums and

Conferences Future Plans

3

IPC HISTORY

1957 - FOUNDED BY SIX INDEPENDENT

BOARD FABRICATORS

1958 - USERS/SUPPLIERS MADE MEMBERS

1966 - MEMBERSHIP OFFERED TO

COMPANIES OUTSIDE THE AMERICAS

1977 - IPC NAME CHANGED TO REFLECT

ELECTRONIC PACKAGING AND

PROGRAMMING

1986 - COOPERATIVE LIAISON WITH ANSI

1988 - COMMITTEE RESTRUCTURING

1991 - IPC DESIGNERS COUNCIL FOUNDED

4

IPC Present Status

REGULAR MEMBERS TECHNICAL LIAISON MEMBERS GOVERNMENT MEMBERS

TOTAL IPC Members 2,500 +

TOTAL Designers Council Members 956 +

5

Beginning of Designers Council

Proposed and validated during

IPC-D-275 workshops in 1991 Over 900 individuals exposed to ideas

during 14 workshops Part of IPC’s Long Range Mission

statement - 1990 Formation meeting held in Atlanta -

January, 1992

6

Designers Council Structure

DESIGNERS COUNCIL

DESIGNERS COUNCILEXECUTIVE BOARD

IPCBOD

GENERAL MEMBERS

INDIVIDUAL CHAPTERS

INTERNATIONALAFFILIATIONS

DESIGNERS COUNCIL EDUCATION COMMITTEE

7

DESIGNERS COUNCIL CHARTER SCOPE

“TO ENCOURAGE, FACILITATE, COORDINATE AND PROMOTE THE ORDERLY INTERCHANGE AND INTEGRATION OF DESIGN CONCEPTS CONCERNING PRINTED BOARD, PRINTED BOARD ASSEMBLY, AND RELATED TECHNOLOGIES THROUGH COMMUNICATION, SEMINARS, WORKSHOPS, LOCAL, NATIONAL AND INTERNATIONAL CHAPTER PROGRAMMING AND OTHER MEANS.”

8

OBJECTIVES

PROMOTE AND DISSEMINATE INFORMATION REGARDING CURRENT ACTIVITIES AND NEW DEVELOPMENTS IN DESIGN TECHNOLOGY.

ENCOURAGE AND DEVELOP

COORDINATED INPUT AND RESPONSE TO EXISTING AND PROPOSED DESIGN-RELATED STANDARDS AND PUBLICATIONS.

9

OBJECTIVES - CONT’D

ACHIEVE MAXIMUM INDUSTRY AWARENESS OF DESIGN STANDARDIZATION ISSUES IN PRINTED BOARD, PRINTED BOARD ASSEMBLY AND RELATED DESIGN TECHNOLOGIES.

ENCOURAGE AND COORDINATE THE COMPILATION OF DESIGN INFORMATION INCLUDING EQUIPMENT, EQUIPMENT CAPABILITY (TOOLS AND TECHNOLOGIES) AND RELATED INFORMATION.

10


INCREASE INDUSTRY AWARENESS OF THE ROLE THAT THE PRINTED BOARD DESIGNERS PLAY IN THE PRODUCT DEVELOPMENT CYCLE.

ESTABLISH A FORMAL EDUCATION STRUCTURE AND CERTIFICATION PROGRAM TO ENSURE DESIGNER COMPETENCY AND CONSISTENT DESIGN STANDARDS.

11


STIMULATE COMMUNICATION AMONG AND BETWEEN PRINTED CIRCUIT BOARD DESIGNERS AND OTHERS IN RELATED ENGINEERING DISCIPLINES.

12

Designers Council Networking

Local Programming – Chapter Based National Conferences – Summit and

the Designer Learning Symposiums Designer Education Programs IPC Standards and Services Designer Email Forum Interchange

13

Internal Support Functions

Database Management Invoicing Website Conferences and Symposiums Designer Education Development

and Implementation Web Forum Monitoring Membership Promotion

IPC Designers Council IPC Designers Council Training and CertificationTraining and Certification

A program that uses industry design A program that uses industry design standards to develop a training syllabus standards to develop a training syllabus

that informs designers on the that informs designers on the manufacturing issues of Printed Boards manufacturing issues of Printed Boards and electronic assemblies. (DFM and and electronic assemblies. (DFM and

DFA).DFA).

Program DevelopmentProgram Development

• Developed by the IPC Designers Council Educational CommitteeDeveloped by the IPC Designers Council Educational Committee• Achieve maximum awareness of the DFM and DFA issuesAchieve maximum awareness of the DFM and DFA issues• Encourage the coordination of design standardization issuesEncourage the coordination of design standardization issues• Increase designer profile elevation processIncrease designer profile elevation process• Stimulate communication between and among designers Stimulate communication between and among designers • Initiate a set of training modules to cover basic and focused Initiate a set of training modules to cover basic and focused

subjectssubjects• Core Module, Advanced Module, Hi-Speed, HDI, etc.Core Module, Advanced Module, Hi-Speed, HDI, etc.• Training materials - Study Guide, Industry Standards, CD-ROMTraining materials - Study Guide, Industry Standards, CD-ROM• Certification requires passing exam (104 multiple choice Certification requires passing exam (104 multiple choice

questions)questions)

Program StatusProgram Status

• Two day training review followed by the two hour Two day training review followed by the two hour exam.exam.

• Almost 3000 Designers have been certified (CID)Almost 3000 Designers have been certified (CID)• Over 500 Designers have achieved their CID+Over 500 Designers have achieved their CID+• Trainings centers located in the US, Europe, Trainings centers located in the US, Europe,

(Scotland Netherlands, Germany) and Australia (Scotland Netherlands, Germany) and Australia (Melbourne, Sydney)(Melbourne, Sydney)

• Over ten officially approved trainersOver ten officially approved trainers• Data base continuously evaluates scores and Data base continuously evaluates scores and

answersanswers• Focus modules being developed for 2007Focus modules being developed for 2007

17

The Designers Certification Program has been devised and The Designers Certification Program has been devised and produced by the Education Committee of the IPC Designers Council.produced by the Education Committee of the IPC Designers Council.

Its purpose is Its purpose is to give to give

designers, and designers, and other PCB other PCB

professionals, professionals, the opportunity the opportunity to gain a world to gain a world

wide wide recognised recognised qualification qualification

based on good based on good practice that is practice that is

required to required to design, design,

manufacture manufacture and test PCB’s.and test PCB’s.

Designer Certification – CIDDesigner Certification – CID

Description & format – click here Description & format – click here ----

Advanced Designer Advanced Designer CertificationCertificationPart 1 CID+Part 1 CID+

Description & format Description & format ----click here ----click here ----

Advanced Designer Advanced Designer CertificationCertificationPart 2 CID++Part 2 CID++


High Speed & High Speed & Impedance Control Impedance Control

Focus ModuleFocus Module


EMI DesignEMI DesignFocus ModuleFocus Module


RF Design PrinciplesRF Design PrinciplesFocus ModuleFocus Module


18

Description & format

Based on the leading IPC standards for PCB design, IPC Designer Certification reinforces the knowledge gained by professionals over their many years of experience and good working practices.

Designers purchase the Designer Certification Kit that includes self-study materials and enrolment in a two-day IPC Designer Certification Preparation workshop. All Designer Certification testing is done at the workshop location shortly after it concludes. Individuals who do not feel prepared to take the test immediately after the training may choose to keep their exam voucher and take the test at a later date. The workshop training provides an in-depth view of the principles contained in the examination and is strongly recommended for anyone interested in obtaining the certification.

Study Guide contents - click here ---- ----

19

Status of Training Modules

Basic Module Live in 1999, minor changes 2005

Advanced One Module Live in 2002, minor changes 2005

High Speed, High Frequency Objectives complete, live in 2005

Electro Magnetic Interference (EMI) Objectives complete, live in 2005

20

Electronic Module Objectives

Module Concept Comparison

• Original Segmentation– Layout– Electrical– Materials– Components– Assembly Requirements– Board Fabrication– Board Physical– Documentation– Inspection/Testing– Reliability

• Proposed Segmentation– Basics of (HiSp)/(EMI)– Electrical Requirements– Board characteristics– Layout Principles– Components and Assy– Performance Parameters– Analysis and Verification– Documentation

To Board

To layout Principles

Included where needed

To Performance and Analysis

Proposed Segmentationis in order of lectures

EMI Design Module Training

DAY 1 (DAY AND DATE)8:00 AM REGISTRATION AND PRESESSION COFFEE BREAK8:30 AM INTRODUCTION TO DESIGNER CERTIFICATIONBASICS OF EMI

1.1 EMI-Definition & RequirementsEMI-Sources & SpectraInterference Paths & EffectsProduct Requirements: Emission & SusceptibilityOverview Tests & Limiting Values

1.2 RF/EMI- CurrentsCommon- & Differential ModeFormation of Common Mode Currents Detection/Measurement of CM CurrentsSamples of CM Currents on PCB & Cables

1.3 Wave shape and Frequency (= HS-Module)Sine Wave DescriptionDigital Pulses and HarmonicsTime Domain and Fourier Spectrum; BandwidthClock Frequency vs. Switching Frequencies

1.4 Fundamentals of EM-FieldsParasitic Antenna in Electronic SystemsElectromagnetic FieldsStatic Electric & Magnetic FieldHigh frequency Fields: Near/Far Field

Refreshment Break


ELECTRICAL REQUIREMENTS

2.1 Basic Radiation Sources in Electronic SystemsMagnetic Dipole - Samples & CalculationsElectric Dipole - Samples & CalculationsResonances on PCBDipole as Receiver AntennaFrequency & Radiation Spectrum of Digital Signals

2.2 Coupling Mechanism between Circuits (> Franzis-EMV)Description of TEM-LinesCapacitive Coupling - Counter MeasuresGalvanic-Inductive Coupling - Counter Measures (> FED 8.2.6.1)Wave Coupling - Counter Measures

2.3 Power System Design and Decoupling (FED- 3.9.1.0 and 3.9.1.2)Capacitor Selection and Decoupling (> FED 6.2.2.1) (also 5.1)

Transient SuppressionUse of PlanesEmbedded Capacitance

2.4 RF- versus DC-Ground (see also 3.2)Return Path VariationGround Plane StitchingSplit Plane ImpactPower system Radiation; Fringing

Lunch


BOARD CHARACTERISTICS

3.1 Printed Circuit Boards in Principle (> Martin O'Hara "PCBSTD.doc" )PCB TerminologyConstruction of a PCBPCB Design ParametersMultilayer Build (> Martin O'Hara "PCBHS.doc" Chap. 7.2 + 7.2.1)

3.2 PCB Layout for EMC Segmentation (> Martin O'Hara "PCBSTD.doc" )Decouple Local Supplies and IC'sGrounding TechniquesOrder of LayoutOther Tracking Issues

3.3 Double-Sided Boards vs. Multilayer (to be checked against 2.3)Power/GND supply (FED 8.2.3.2 + 3.9.2 ?)Signal Return-PathEMI by Reflection and CrosstalkControlled Impedance Effects (reflection control)

3.4 Impedance Controlled Boards (see HS-Module 3.2; shortened)Impedance DefinitionMicrostrip and StriplinePower Supply ImpedanceRadiation from Power System; Shielding

Refreshment Break


LAYOUT PRINCIPLES

4.1 Single- and Double-sided Boards (> Franzis' Book Chap.4/ FED 8.1.5 + 8.1.6.1)

Disturbance Currents and PathsLayout of Signal- and Power netsC-Blocking/DecouplingRadiation from Power & Signal netsGrounding to Periphery

4.2 EMI Avoidance Strategy with MultilayerI/O Segmentation; Circuit IsolationGND Plane ShieldingLayout Priority OrderInductance Issues

4.3 IC and Passive Placement/ Circuit SegmentationConnector and Filter Placement Analog vs. Digital LayoutHigh/Low Speed ZonesCircuit Group Shields/Circuit Balance

4.4 Contacting of Filters & Ferrites (Periphery)Capacitors (on Board)EMI-Ferrites & InductorsVaristors; Diodes; Gas ShuntsFilter Boxes; Placement & Contacting

4:30 PM QUESTIONS AND ANSWERS5:00 PM ADJOURN


DAY 2 (DAY AND DATE)8:00 AM PRESESSION COFFEE BREAK8:30 AM RECAP OF FIRST DAYCOMPONENTS AND ASSEMBLY

5.1 Passive Components ( > Martin O'Hara "Passives.doc")PackagingResistorsCapacitorsInductorsTransformers

5.2 Active Components ( > Martin O'Hara "ICs.doc")Logic Families PrinciplesPackaging Influence (BGA Layout Concepts?)Digital DevicesAnalog Devices

5.3 Connectors & CablingPin Assignment EMI-ConnectorsShielded Cable; Transfer ImpedanceCable Contacting

5.4 Housing & Mounting (Enclosure Design)Shielding PrincipleMaterials and Coatings Opening Sizes & FormDesign Rules

Refreshment Break


PERFORMANCE PARAMETERS

6.1 Drive Voltage Characteristics (proposal 2E1 DC-Group)Voltage DifferencesCapacitive Charge EffectsPower DistributionDecoupling Character

6.2 System vs. Board Ground (proposal 2E5 DC-Group)Difference ExplanationGrounding PrinciplesShield EffectsImprovement Methods

6.3 Transient SuppressionESD EFT/BurstSurge/LightningVoltage Surges/Drops

6.4 Costs, Availability, Lead timeMultilayer vs. 2 sided Boards Influence Layer Count & Line-width Filtering & Test EffortsTime to Market

Lunch


ANALYSIS AND VERIFICATION

7.1 EMI Evaluation with SW-Tools (i.e. Expert System)Screen Room CharacterizationTransmission Signal SaturationPower Supplements for Leakage Testing Interpretation & Consequences

7.2 EMI Demands/Requirements - Tests (> Rainer)EMI/EMC - StandardsTest Structure; Emission & SusceptibilityÉmission Tests (i.e. EN 55011 etc.)Susceptibility Tests (IEC 1000-4-x)

7.3 EMI-Measurements (> Rainer)Test Equipment (Overview)Emission Test SetupsSusceptibility Test SetupsConformity Declaration

7.4 Assembly Analysis Verification (= HS-Module)Arrangement of Components InfluenceTest Circuits for Radiation EmanationEmbedded Passives RingingExternal Shields & Coating

Refreshment Break


DOCUMENTATION

8.1 General Documentation PracticesFabrication Master Specification TechniquesAssembly Shielding Definition RequirementsGrounding Description and VerificationEMC Approvals and Labeling

8.2 EMI Restricting Materials & TolerancesDescription of Material PropertiesSpecification and Source Control DrawingsApplication Sequence ParametersPreparation and Test Method Specifications

8.3 Multilayer EMI / EMC ConstructionDefinition of Plane LocationDescribing Purpose of Hole Guard BandsRandom Conductor Flooding ParametersSpecific EMI Prevention Stack-up Description

8.4 Board Topology IssuesComponent Assembly Shielding Requirementsinfluence of Coatings and SoldermaskAssembly Sequencing to Facilitate AttachmentSurface Finish and Solder Joint Radiation

4:30 PM QUESTIONS AND ANSWERS5:00 PM ADJOURN

Psychometric Analysis

Topic Percent Beta X & Y X & Y Finals

Sections Q&A? Q&A Need Unique/Dupe– Basics 10% 30 = (20/10) 8/4 = 20– Electrical 15% 45 = (30/15) 12/6 = 30– Boards 10% 30 = (20/10) 8/4 = 20 – Layout 15% 45 = (30/15) 12/6 = 30 – Assembly 10% 30 = (20/10) 8/4 = 20– Perform. 15% 45 = (30/15) 12/6 = 30– Analysis 15% 45 = (30/15) 12/6 = 30– Docum. 10% 30 = (20/10) 8/4 = 20– Totals 100% 300=(200/100) (80/40) = 200

160 + 40 = 200

Beta and Live Q & A Segmentation

Basics of High Speed – 30/20 Basics of EMI – 30/201.1 High Speed Defined

Low and High Frequency Signals

Signal Rise Distance; Edge Rate

Critical Line Length – Rise-time Relationship

Skin Effect; Signal Attenuation

7/4

1.1 EMI – Definition and RequirementsEMI Sources and Spectra

Interference Paths and Effects

Test Structure: Emission & susceptibility

Overview Tests and Limiting Values

7/4

1.2 Wave Shape and FrequencySine Wave Description

Digital Pulses and Harmonics

Time Domain & Fourier Spectrum; Bandwidth

Clock Frequency vs. Switching Frequencies

9/6

1.2 RF/EMI CurrentsCommon and Differential Mode

Formation of Common Mode Currents

Detection and Measurement of CM Currents

Samples of CM Currents on PCB and Cables

9/6

1.3 Impedance DefinitionLine Impedance –Water model

DC- versus Impulse Current

Electrical Line Impedance; Lumped C,L

Power Supply Impedance; Requirements

7/5

1.3 Wave Shape and Frequency Sine Wave Description

Digital Pulses and Harmonics

Time Domain & Fourier Spectrum; Bandwidth

Clock Frequency vs. Switching Frequencies

Duplicate HS 1.2 7/5

1.4 Transmission Line DefinitionSignals on TEM-Lines; Differential Signals

Propagation Delay, Attenuation, Slew & skew

Reflections and Oscillations; Termination topic

Coupled Lines; Crosstalk

7/5

1.4 Fundamentals of EM-FieldsParasitic Antenna in Electronic Systems

Electromagnetic Fields

Static Electric & Magnetic Field

High frequency Fields: Near/Far Field

7/5


Electrical Requirements – 45/30 Electrical Requirements – 45/302.1 Power System Implementation

Distribution Path; Ground Bounce

Bypassing/Decoupling

2-sided Boards

Multilayer; Embedded Capacitor

11/7

2.1 Magnetic Dipole - Samples & CalculationsElectric Dipole - Samples & Calculations

Resonances on PCB

Dipoles as Receiver Antenna

Digital Signal Frequency/Radiation Spectrum

11/7

2.2 Signal TransmissionRF Signal Return Current

Reflections and Oscillation

Topologies and Terminations

Crosstalk (Forward & Backward) & Control

12/8

2.2 Coupling Mechanism Between CircuitsDescription of TEM-Lines

Capacitive Coupling - Counter Measures

Galvanic-Inductive Coupling - Center Measures

Wave Coupling - Counter Measures

12/8

2.3 Circuit AnalysisTiming Margin; Clock Skew

Loaded Line Characteristics & Timing

Branching Issues; Stubs

Layer Skipping

10/7

2.3 Power System Design and DecouplingCapacitor Selection and Decoupling

Transient Suppression

Use of Planes

Embedded Capacitance

10/7

2.4 Differential SignalingRouting Techniques

Terminations

Influence of Planes

Conductor Width & Spacing

12/8

2.4 RF- versus DC-GroundReturn Path Variation

Ground Plane Stitching

Split Plane Impact

Power System Radiation; Fringing

12/8


Board Characteristics – 30/20 Board Characteristics – 30/203.1 General PC Board Fabrication

Standard Materials (Laminates & Prepregs)

Material Properties (DK, CTE, ...)

Copper Requirements; VLP Foils

Process Tolerances & Influence Analysis

7/4

3.1 Printed Circuit Boards in PrinciplePCB Terminology

Construction of a PCB

PCB Design Parameters

Multilayer Build

7/4

3.2 Board ImpedanceImpedance Classes

Single Ended Layering (Microstrip & Stripline)

Differential Pairs

Power planes

9/6

3.2 PCB Layout for EMC SegmentationDecouple Local Supplies and IC's

Grounding Techniques

Order of Layout

Other Tracking Issues

9/6

3.3 Multilayer Constructions4 Layer Structures

6 Layer Construction

8+ Layer Constructions

Layering Approaches

7/5

3.3 Two- sided Boards vs. MultilayerPower/GND supply

Signal Return-Path

EMI by Reflection and Crosstalk

Controlled Impedance Effects (reflection control)

7/5

3.4 HDI-/Microvia ConstructionsMicrostrip Constructions

Stripline Constructions

Dual-Stripline Constructions

Impedance Variations & Tolerances

7/5

3.4 Impedance Controlled BoardsImpedance Definition

Microstrip and Stripline

Power Supply Impedance

Radiation from Power System; Shielding

HS 3.2 shortened 7/5


Layout Principles – 45/30 Layout Principles – 45/304.1 PC Board Design Elements

Optimum Impedance Value

Proper Trace Width & Spaces

Maximum Stub Lengths

Test Structure needed

10/7

4.1 One- and Two- Sided BoardsDisturbance Currents and Paths

Layout of Signal- and Power nets

IC-Blocking/Decoupling

Radiation from Power & Signal nets

Grounding to Periphery 11/7

4.2 Component Placement & Split PlanesCircuitry Analysis; Bus Structures

Split GND/VCC Planes

Component Side Distribution

Periphery & Connectors

12/8

4.2 EMI Avoidance Strategy with MultilayerI/O Segmentation; Circuit Isolation

GND Plane Shielding

Layout Priority Order

Inductance Issues

12/8

4.3 Vias & Via ChainsMechanical Properties

Capacitance & Inductance of Vias

Influence on the Line Impedance

Return-Current Flow

11/7

4.3 IC/Passive Placement/ Circuit SegmentationConnector and Filter Placement

Analog vs. Digital Layout

High/Low Speed Zones

Circuit Group Shields/Circuit Balance

10/7

4.4 Pre-layout Analysis (Line Simulation)Layer Stacking Strategy

Timing, Clock Distribution

Termination Strategies; Noise Budgets

Preventive Crosstalk Analysis

12/8

4.4 Filters & Ferrite Contacting (Periphery)Capacitors (on Board)

EMI-Ferrites & Inductors

Varistors; Diodes; Gas Shunts

Filter Boxes; Placement & Contacting

12/8


Components and Assembly – 30/20 Components and Assembly – 30/205.1 Bypassing/Decoupling Capacitors

Real Capacitors; Impedance vs. Frequency

Dielectric, ESR & Loss Tangent

Parallel Connection of Capacitors

Optimal on Board Contacting

7/4

5.1 Passive ComponentsPackaging

Resistors

Capacitors

Inductors

Transformers 7/4

5.2 Component and Package SelectionParasitic Package Inductance & Capacitance

Rise time, Slew rate, Noise margin, Driving Force

Fan-out Wiring Requirements & Stub Length

Embedded Passives, COB

9/6

5.2 Active ComponentsLogic Family Principles

Packaging Influence (BGA Layout Concepts)

Digital Devices

Analog Devices

9/6

5.3 Connector SystemsMutual Inductive Coupling & Parasitic Capacitance

High Speed Connectors

Estimating Crosstalk

Return-Current Path

7/5

5.3 Connectors & CablingPin Assignment

EMI-Connectors

Shielded Cable

Transfer Impedance Cable Contacting

7/5

5.4 Ribbon CablesSignal Propagation

Frequency Response

Cable Rise-time

Cable Crosstalk

7/5

5.4 Housing/Mounting (Enclosure Design)Shielding Principle

Materials and Coatings

Opening Sizes & Form

Design Rules

7/5


Performance Parameters – 45/30 Performance Parameters – 45/306.1 Concurrent Layout Analysis (Line & BD)

Component IBIS Models; Loads, Terminations

Timing/Delay/Skew Optimization

Crosstalk & Reflections Analysis

Power Distribution System: Integrity Analysis

11/7

6.1 Drive Voltage CharacteristicsVoltage Differences

Capacitive Charge Effects

Power Distribution

Decoupling Character

11/7

6.2 Optimum Layer RelationshipSignal Layer Distribution; Shielding Planes

Split Planes; Cutouts, Field Fringing

Crosstalk in GND Planes

Stack-up Balance, Producability

12/8

6.2 System vs. Board GroundDifference Explanation

Grounding Principles

Shield Effects

Improvement Methods

12/8

6.3 Material Properties & SelectionHigh Speed Dielectric Material

RC-Foil vs. Reinforced Material

Copper Thickness vs. Line width

Thermal Management; Heat sinks

10/7

6.3 Transient SuppressionESD

EFT/Burst

Surge/Lightning

Voltage Surges/Drops

10/7

6.4 Costs, Availability, Lead timeInfluence Layer Count & Line width

HDI/µVia vs. Conventional Boards

Intermixing High Frequency Materials

Back Drilling for Stub Removal

12/8

6.4 Costs, Availability, Lead timeInfluence Layer Count & Line width

Filtering & Test Efforts

Time to Market

Multilayer vs. 2 sided Boards

12/8


Analysis and Verification – 45/30 Analysis and Verification – 45/307.1 Post Layout Analysis (Board Simulation)

Power Integrity: Decoupling & Noise Margin

Signal Integrity: Crosstalk & Reflections

Constraint Driven Routing Analysis

Delay/Skew Situation

11/7

7.1 EMI Evaluation with SW-Tools Screen Room Characterization

Transmission Signal Saturation

Power Supplements for Leakage Testing

Interpretation & Consequences

11/7

7.2 Signal Integrity MeasurementsDefining Test Equipment

Performance Parameters

On-Board Measurements

Interpretation & Consequences

12/8

7.2 EMI Demands/Requirements - TestsEMI/EMC - Standards

Test Structure; Emission & Susceptibility

Emission Tests (i.e. EN 55011 etc.)

Susceptibility Tests (IEC 1000-4-x)

12/8

7.3 Impedance Control Testing Test Setup Methods

Coupon Design and Placement

Testing Differential Pairs

On-Board Measurements

12/8

7.3 EMI-MeasurementsTest Equipment (Overview)

Emission Test Setups

Susceptibility Test Setups

Conformity Declaration

12/8

7.4 Assembly Analysis VerificationRegistration Capability

Test points and Test Nets

Embedded Passives

External Shields & Coating

10/7

7.4 Assembly Analysis Verification Arrangement of Components Influence

Test Circuits for Radiation Emanation

Embedded Passive Ringing

External Shields & Coating

similar to HS 7.4 10/7


Documentation – 30/20 Documentation – 30/208.1 General Documentation Practices

Mixture of Electronic and Hard Copy Data

Re-procurement of “as- built” requirements

Configuration Management Strategy

Field Reports and Maintenance

7/4

8.1 General Documentation PracticesFabrication Master Specification Techniques

Assembly Shielding Definition Requirements

Grounding Description and Verification

EMC Approvals and Labeling

7/4

8.2 Materials/Impedance ToleranceDielectric Parameter Descriptions

Performance Variation Maximum Allowance

Coupon Verification Strategy

Prototype/High Volume Description Controls

9/6

8.2 EMI Restricting Materials & TolerancesDescription of Material Properties

Specification and Source Control Drawings

Application Sequence Parameters

Preparation and Test Method Specifications

9/6

8.3 Multilayer ConstructionSingle Lamination Criteria

Sequential, build-up Multilayer

Embedded Passive Description and Control

Exotic Material Influence/Definition

7/5

8.3 Multilayer EMI / EMC ConstructionDefinition of plane location

Describing purpose of hole guard bands

Random Conductor Flooding Parameters

Specific EMI Prevention Stack-up Description

7/5

8.4 Board Thickness IssuesLimitation for Card Edge Conditions

Assembly Support and Housing Influence

Moisture Influence & Conformal Coating

Sequencing Mat’l, Fabrication, Assembly and Test

7/5

8.4 Board Topology IssuesComponent Assembly Shielding Requirements

Influence of Coatings and Soldermask

Assembly Sequencing to Facilitate Attachment

Surface Finish and Solder Joint Radiation

7/5

New Structure Status Summary

• Thirty two objectives

• Two forms of tests; X and Y

• Three hundred questions in the Beta

• Two hundred questions needed for exams– X form 80 unique questions; 40 identical– Y form 80 unique questions; 40 identical

• Applicants need to be CID minimum

• Can add initials to status on Business Card– CID/H, CID/E, or CID/HE– CID+/H, CID+/E or CID+/HE

40

CERTIFICATION TESTING IPC ADMINISTERED

- IN CONJUNCTION WITH TWO-DAY PREPARATION WORKSHOP- WORKSHOPS SCHEDULED IN

ADVANCE

IMMEDIATE FEEDBACK- SCORED AT TEST SITE- AREA SPECIFIC DISCUSSION- PASS/FAIL RESULTS- CATEGORY ANALYSIS REPORT

41

Education Committee

Volunteer Group

- Independent Designers

- Board Manufacturers

- OEM Representatives

- Consultants

- Representatives from Education Community

42

TRAINING CENTERS

PREMIER - UK SCOTTISH ADVANCED MANUFACTURING

CENTRE (SAMC) COLLIN COUNTY COMMUNITY COLLEGE FERRARI TECHNICAL SERVICES EPTAC PALOMAR COLLEGE PIEK – NETHERLANDS ATTEC – AUSTRALIA SMCBA – AUSTRALIA SKAANNING QUALITY AND CERTIFICATION FED – GERMANY

43

Chapter Activity

Effective Leadership Interesting meetings Establish a Program Committee Have a way for Local Networking Invite Popular Speakers Workshop Study Groups Fund Raising Events

44

Talk to past Officers/Presidents Pull a Chapter together

Keep focused Create the bylaws Keep action oriented Anticipate some friction Involve the group

Chapter Structure and Planning

45

Goals and strategies Don’t do it alone Make the most out of meetings Expect long-term effort Money is important

Constructive Planning

46

Think outside the work place Use the communities around

you. Choose the right fundraisers Make the basic decisions Plan the event Provide the extra’s Promote effectively

Introduction to Fundraising

47

Fundraising Ideas

Auctions Tournaments Dinners

Roast &Toast

CardParties

FleaMarket

MovieBenefit

VendorDemo Day

HolidayThemes

Seminars Raffles Tours

48

LOCAL CHAPTERS ATLANTA AUSTIN – HEART OF TEXAS CASCADE (WA) CHESAPEAKE COLORADO GATEWAY (MO) GREATER BOSTON GREATER OHIO GREATER PHOENIX HOUSTON LONG ISLAND, NY LOS ANGELES, CA MIDWEST (MINNEAPOLIS, MN)

49

LOCAL CHAPTERS - CONT’D NORTH TEXAS (DALLAS) NORTHEAST OHIO NORTHERN ILLINOIS ORANGE COUNTY (CA) PACIFIC NORTHWEST (OR) RESEARCH TRIANGLE PARK (NC) SAN DIEGO SILICON VALLEY (CA) SMOKY MOUNTAIN (TN) SOUTHEAST MICHIGAN SOUTHERN NEW ENGLAND (CT) SPACE COAST (FL) SUSQUEHANNA (NY)

50

INTERNATIONAL CHAPTERS AUSTRALIA GERMANY (FED) CANADA

- MONTREAL- OTTAWA- TORONTO

UNITED KINGDOM IRELAND (in process) INDIA (IPCA)

51

DOMESTIC UNIVERSITY PARTNERS

PALOMAR COMMUNITY COLLEGE COLLIN COUNTY COMMUNITY

COLLEGE LAKE WASHINGTON TECHNICAL

COLLEGE NORTH SEATTLE COMMUNITY

COLLEGE

52

Participation in Standards Assign a chapter guru to the

design tool kit. Highlight chapter member

interests Incorporate a library function at

meetings Do book (Standard) reports Make each event a value add

53

SUMMIT, SYMPOSIUMS AND CONFERENCES

Designers Summit – February 17-22, 2007 in Los Angeles, CA

Designers Day Designers Certification Education Networking Exhibition

Designer Learning Symposiums – Regional, Throughout the Year

Education Certification Networking

54

Path Forward for IPC Designers Council Chapters

Monthly Local Chapter Networking

Quarterly Teleconferences

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Designers Council Future Activities in 2007

Designers Summit – February 17-22 Designers Day – Monday, February 19 Certification Workshops – Sunday, Feb. 18

and Thursday, Feb. 22 Technical Conference – Tuesday, Feb. 20 Face to Face Designer Council Leadership

Breakfast – Tuesday, Feb. 20 Standards Development Meetings Free Forums Exhibitions “It’s Your Party” featuring The Designers

Den – Wednesday, Feb. 21

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Designers Day – February 19th

Learn the latest in high speed design, the lead free initiative, EMI and much more.

Hear from experts about ways to prepare for the future.

Get the latest news on upcoming IPC Designers Council programs and plans.

Network with your peers. Attend the Designers Day Dinner.

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Designers Learning Symposiums May 22 – Bannockburn, IL August 15 – Toronto, Canada More to be announced

Release of Focus Modules for the Designer Certification Program High Speed EMI

Updates to Basic and Advanced Designer Certification Programs

ipc designers council how can we help you and your local chapter be successful?

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