io school of microelectronic engineering lecture 1 introduction to ic fabrication

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School of Microelectronic Engineering

Lecture 1Introduction to IC Fabrication


HISTORY

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What is Semiconductor Process Technology? The technology to produce IC microchips

IC chips are the backbone of the computer industry and have spurred related technologies such as software and internet

Every product of the information age is an offspring of IC technology

IC chips increasingly control functions in cars, TVs, VCRs, cameras, mobile phones, toys, etc.

The current technology is as a result of years of research and development, taken many thousands of scientists, engineers and technicians.

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The Evolution of IC


First Transistor, Bell Lab 1947

John Bardeen and Walter Brattain, demonstrateda solid state device made from germanium. Theyobserved that when electrical signals were appliedto contacts on germanium, the output power waslarger than the input. These results were publishedIn 1948.

William Shockley, found out how the bipolar transistorfunctioned and published the theory in 1949.

Three of them shared the Nobel Prize in physics in1956,

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First Transistor and Its Inventors


Semiconductor industry developed rapidly and germanium based transistor quickly replaced vacuum tubes in electronics equipment due to:

smaller size lower power consumption lower operating temperature quicker response time

Single crystal silicon and germanium based devices introduced in 1950 and 1952 respectively (better defect control, hence higher yield).


Shockley left Bell Labs in 1956, to start his own lab in San Francisco Bay, California. Nowadays known as Silicon Valley. His lab has attracted talented scientist such as Robert Noyce and Gordon Moore.

Gordon Moore and Robert Noyce left Shockley in 1957 to start Fairchild Semiconductor.

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First IC Device by Jack Kilby, Texas Instruments 1958

1st fabricated by Bell Labs in 1958. Jack Kilby demonstrated functional IC, fabricated on germanium strip consists of;

one transistor one capacitor 3 resistors

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First Silicon IC Chip by Robert Noyce, Fairchild Camera, 1961

Fairchild Semiconductor produced the 1st commercialICs in 1961. This IC consists of only 4 transistors sold for USD 150 a piece.

NASA was the main customer.

In 1968, Robert Noyce cofounded Intel Corp. withAndrew Groove and Gordon Moore.

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Moore’s Law

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Moore’s Law, Intel Product

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IC Integration Scale

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Feature Size and Wafer Size

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Road Map Semiconductor Industry

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Limit of IC SizeIs there a limit for the minimum feature size?

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Limit of IC Device

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IC Product Category

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OVERVIEW ON IC MANUFACTURING

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IC Manufacturing

A very complicated process, involves; Circuit design Manufacturing material Clean room technology, processing, equipment Wafer processing technology Die testing Chip packaging and final test


IC Manufacturing Flow

Design

Mask info to MASK-SHOP + GDSII file

Mask making

Generate runcard

Wafer Preparation

Front-end Processes (individual transistor)

Deposition

Oxidation

Diffusion

Photolithography

Etch (wet and dry)

Implantation

Backend Process Deposition (oxide, nitride etc) Metalization Rapid Thermal Process Lithography & Etch

Test (Parametric and Functional) Packaging Final Test


IC Manufacturing Processes

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IC Design: Idea to Design Synthesis

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IC Design: Architecture to Layout

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Architectural Design – Defines the application operating system and devides modules for system.

SDA

GND A2 A0A1

SCL WP VCC

Charge Pump

16K-bits Memory Cell

Timer

Control Logic (Master)

EEPROM Design Layout

E/Wcircuit

E/Wcircuit

Decoder Xe

Decoder Xr

Dec Y

Dat

a ct

rlA

ddre

ss b

lock

Dec

oder

px


Logic Design – Puts logic units such as adders, gates, inverters and registers into each module and run subroutines in each module .

Circuit / Transistor Design – Individual transistors are laid out in each logic unit.

Layout – To transfer from schematic to layout

pMOS

nMOS

VDD

VSS

S

S

D

D

VIN VOUT

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IC Design: Design Flow

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Wafer Fabrication: From Design to Wafer

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IC Design: 1st IC

1st IC design by hand (Jack Kilby)

Currently, hundreds of designers workon single product to design, validateand lay outed will take several monthsto complete with the help of CADtools.

Main considerations; performance die size design time and cost testability


IC Design: State of The Art ICCMOS Inverter - basic building block of digital MOS design

Layout

Cross section


IC Design: Layout and Mask s of CMOS Inverter


Mask / Reticle After IC design is completed, generated layout image is printed on a piece of quartz glass coated with a layer of chromium. A laser beam projects the layout image onto the photoresist coated chrome glass surface. Photon change the chemistry of the exposed photoresist via a photo chemical reaction, and later dissolved in a base developer solution. A pattern etching removes the chromium at the exposed area. Therefore, it transfers the image of the IC layout to the quartz glass. This is done at mask shop


Mask / Reticle Mask – Covers the whole wafer, used in projection, proximity and contact lithography technique. Reticle – Covers only part of the wafer, employed in step and repeat lithography technique.

MASK RETICLE


Typical Wafer Fabrication Process Flow Around 500 process steps to complete IC fabrication Involves 20 masking steps


OVERVIEW ON WAFER FABRICATION


Wafer Fabrication

Objectives


Why Yield Is Important?


Wafer Yield

The ratio between number of good wafers after finishing all the process steps, and total number of starting wafers .


Die Yield

The ratio between number of good dies per total of dies on the tested wafer after functional probe test.


Packaging Yield

The ratio between number of good chips after finishing all the packaging steps, and total of chips packaged.


Overall Yield

Wafer yield depends mainly on processing and wafer handling. Careless handling and robot malfunction could break wafers Faulty process such as misaligned during lithography, large amount of particles, poor process uniformity, etc can also ruin wafers.


How Does Fab Make Money


How Does Fab Make (Loss) Money


Defects and Yield

Y – overall yield D – defect density (minimum level determined by facilities) A – chip area (die size) n – number of processing steps


Yield and Die Size


Yield Curve


Typical Production Wafer


Why Cleanroom ?


Cleanroom


Cleanroom Class


Cleanroom Class (Definition of Airborne Particulate)


Effect of Particles on Mask


Effect of Particles on Wafer


Cleanroom Structure

Main features; raised floor laminar air flow HEPA filters higher pressure controlled humidity and temperature


Gowning Area


Typical Wafer Process Flow


Typical Process Bay


Wafer Test

Parametric Test (Wafer Acceptance Test Data)

Functional Test (Die Yield)


Device Specifications (Transistor)


Device Specifications (Resistance)


Parametric Test Result (WAT Data)


Functional Test


Packaging

4 Main Purposes;

to provide physical protection for the IC chip

to provide a barrier layer against chemical impurities and moisture

to connect the IC chip to the electrical circuit board

to dissipate heat generated during chip operations


Main Packaging Steps

Wafers coated with protective layers on the surface, mechanically polished on the wafer backside to reduce thickness (600 to 300 um)

A thin layer of gold is coated at the wafer backside

Protective layer at the wafer surface is removed, and wafer backside is taped to on a solid frame. Then wafer sawing process.

Die sorting (to pick up good dies)

Die attach (to attach good dies to a packaging socket)

Wire bonding


Chip Bond Structure


Wire Bonding


IC with Bonding Pads


IC Chip Packaging


Chip with Bumps


Flip Chip Packaging


Bump Contact


Heating and Bumps Melt


Molding Cavity for Plastic Packaging


Ceramic Seal

io school of microelectronic engineering lecture 1 introduction to ic fabrication

Documents

ic microchips ic chips

ic manufacturing

functional ic

fairchild semiconductor

germanium strip

gordon moore

robert noyce cofounded

wafer size