i/o, i/o … so much data … oh, no!!!€¦ · ieee waves & devices meeting –phoenix chapter...

IEEE Waves & Devices Meeting – Phoenix Chapter February 18, 2016 Tempe, AZ

Lesley Polka, Ph.D.

Principal Engineer

Assembly and Test Technology Development

Intel Corporation

I/O, I/O … So Much Data … Oh, No!!!High Bandwidth Packaging Challenges in a Connected World

High Bandwidth PackagingLesley Polka

2

A Personal Perspective

IEEE Waves & Devices Meeting

When I joined Intel (11/14/1994)

2008 2010 2012

100 Gbps?~1000x I/O Speed in 20 years!

1994Today


3

The High Bandwidth Interconnect Challenge:

Yesterday



4

The High Bandwidth Interconnect Challenge:

Today


A diversity of

connected devices

… and they all need

to be Packaged!


“We’re all dealing with the same challenges”

… cost, performance, area / scaling

+ commoditization & customization

… and these challenges aren’t new

… what is new is the scale of the challenge today

IEEE Waves & Devices Meeting 5


6

What I’d Like Everyone to Leave with Today

Key Messages

• A connected world drives an accelerated demand for bandwidth.

• The increasing demand for bandwidth results in packaging

challenges and opportunities on a new scale.

• Innovation is needed in materials, process, and design.

• 2.5D and 3D package architectures are uniquely positioned to

address growing bandwidth challenges.

• Opportunities for Packaging Engineers in all disciplines (electrical,

thermal, mechanical, materials, etc.).



Outline

• Drivers• Bandwidth Trends

• Impact on Packaging

• Package Interconnect Challenges & Solutions• Materials

• Processing

• Design

• Package Architecture Challenges & Solutions• 2.5D and 3D Packaging

• An Example: EMIB

• Wrap-Up



Drivers



9

Packaging & the Connected World

Two drivers bound the high bandwidth challenge for packaging:

• The need to “connect” or to transmit data globally• Dominated by Serial I/O

• Example: SerDes

• The need to store and access data locally• Dominated by Parallel I/O

• Example: DDRx


GATEWAY

NETWORKINFRASTRUCTURE

DATA CENTER/ CLOUD

THINGS


10

The Diversity of the Connected World

• Broad Spectrum of Devices, Packages & Form Factors

• Growing Set of Communication Protocols & Specifications

• Variety of IPs and Silicon Nodes



11

Bandwidth Deconstructed

Bandwidth = I/O speed X # of bits transferred

– I/O speed = speed of a single data line (in MTs, GTs or Gbs)

– # of bits transferred = bus width or # of data lines

Example: Bandwidth of a single channel of DDR4 @ 2400 MTs

I/O speed = 2400 MTs = 2.4 GTs

# of bits transferred = channel width = 128 bits = 16 bytes

therefore,

Bandwidth = 2.4 GTs x 128 bits

= 2.4 GTs x 16 bytes

= ~ 40 GB/s



CPU Bandwidth Scaling

• Need 100’s of GB/s memory Bandwidth to CPU, growing at 30% or more per year.

• Given the CPU IO constraints, we are likely to increase speed while keeping bits/wire

efficiency of single ended signaling.

128 GB/s

160 GB/s

25 GB/s102 GB/s

1 TB/s

?


* Used with permission from Suresh Chittor, Intel Corp.


Serial I/O Trending Example: SerDes

Implementation in Packaging• Very high speeds!!!

• Differential signaling

• Two package routes & pins per data bit

• Sensitive to package loss (e.g., S21)

100 Gbps?

CEI 11G-SR, LR

CEI 28G-VSR, SR, LR

CEI 56G MR,

SR, XSR, USR

I/O

Sp

ee

d (

Gb

ps)

2002 2008 2010 2012

10

20

30

40

50

60

20062004 2014+


CEI 6G-SR, LR

Drives Package

I/O Speed

13


0

500

1000

1500

2000

2500

3000

3500

4000

4500

DDRx & LPDDRx Speeds

DDRx Speed LPDDRx Speed

Parallel I/O Trending Example: DDRx & LPDDRx

Implementation in Packaging

• High density routing!

• Signal-ended signaling

• One package route & pin per data bit

• Sensitive to package crosstalk /

coupling (e.g., xtalk, S31)


I/O

Sp

ee

d (

MT

/s)

Drives Package

Routing Density

14


Bandwidth Growth - Historical

• Client Bandwidth growth from speed only, 128 total data bits.

• Server Bandwidth growth from width and speed, 256 wide now.


* Used with permission from Suresh Chittor, Intel Corp.


16

The Scaling of the Challenge

• In Packaging, we care about the “electrical” length, i.e.,

the physical length expressed in wavelengths (l):

l = v / fo = 1.5x108 m/s / fo (for organic packaging)

1994 vs. Today

1994 (66 MHz FSB): 20 mm = 0.0088l (can use circuit theory)

Today (28 Gbps SerDes): 20 mm = 1.87l (need EM theory)


Typical Package Interconnect Length (20 mm) in ls:

1994

2015

D > 200x!


17

Impact on Packaging


• Higher Bandwidth• Higher Speeds

• Higher Frequencies

• Higher Routing

Density

• Higher Pin Counts

• Increasing Diversity

of Protocols

• Diversity of IP Blocks

& Silicon Nodes

• Materials

• Processing

• Design• Tools

• Methods

• Design Rules

• Partitioning &

Architecture

Drivers Packaging Impact


18

The High Bandwidth Interconnect Challenge


We Don’t Want This!The Goal


Package Interconnect



20

Overview

Package I/O speed is directly related to:• Materials

• Process

• Design


Die-Pkg Transition (FLI)

Pkg-Brd Transition (SLI)Routing

0 10 20 30 40 50 60 70 80 90 100-10 110

-0.3

-0.2

-0.1

0.0

0.1

0.2

0.3

-0.4

0.4

time, psec

eye

_o

ut4

S22

S11S21

Package I/O Interconnect

DDR – high-density

SerDes – very high speed


21

Materials & Process

High-speed Signal Transmission at high

frequencies is impacted almost equally by:

• Material selection (tand)

• Process (surface roughness)


Loss Tangent (tand)

DT1

TSTw

Differential Stripline

Tw TT

DT2

Ideal Case The Reality The High-Speed Reality

+ High-speed

Tools & Methods


22

Materials & Process: The Impact

2015 Electronics Packaging Symposium

Reduced Surface

Roughness

Low Loss

Standard

Material

Benefits of improved materials &

processing become appreciable at

high speeds (25+ Gbs)

10 Gbs

25 Gbs


Inse

rtio

n L

oss (

dB

)

Frequency (GHz)

Trace length (for 2dB loss @ 25 Gbs)

• Standard Material & Roughness:

Max. tl = 15.5 mm

• Low-loss & No Roughness:

Max. tl = 21.6 mmD ~ 40%!

22


23

The Impact of Design

Careful Design is critical at High Speeds:• Stack-up & routing

• Vertical stack


Vertical Stack

Inse

rtio

n L

oss (

dB

)

Frequency (GHz)

Standard Material

Low-loss

Optimized Vertical

Stack

Trace length (for 2dB loss @ 25 Gbs)

• Standard Material & Stack:

• Max. tl = 15.5 mm

• Low-loss & Optimized Stack:

Max. tl = 19.5 mm

25 Gbs

D ~ 25%!


Package Architecture



25

Package Architecture & Partitioning

• Optimized Package Architecture & Partitioning enables higher densities,

performance & integration (of heteorogeneous die, silicon nodes, IPs, etc.).

• Evolution from traditional MCP packaging to unique 2.5D and 3D packaging is

needed to enable the high bandwidths needed in today’s connected world.


Traditional MCPs

~30 I/Os / mm2.5D & 3D MCPs

~250 I/Os / mm


26

2.5D and 3D Packaging Examples

• 3D packaging uses TSVs to stack die … memory, logic, etc.

• 2.5D packaging … multiple examples in industry, including silicon interposers,

EMIB, organic interposers, etc.


3D

2.5D

Si InterposerEMIB


27

A 2.5D Example: EMIB

EMIB = Embedded Multi-Die Interconnect Bridge• Improved density for die-to-die high bandwidth connections

• ~250 I/Os / mm / layer

• Package heteorogeneous die integration• Example: integration of disparate silicon nodes / devices

• Example: enables key features ahead of si-node / IP readiness2015 Electronics

Packaging Symposium

EMIB Pkg

Chip 1

Chip

3C

hip

2

Chip

4C

hip

5

Silicon

Bridge

Silicon Bridge Organic Pkg

Substrate



28

EMIB Product Implementation: Altera Stratix-10

Tile architecture integrated on EMIB Packaging enables:• Implementation of product core on leading-edge silicon node (i.e., 14nm)

• Integration of validated, hardened IPs from other silicon nodes

• Fast & cost-effective customization of entire product portfolio

• Scalability to higher speeds, bandwidths, technologies & functionality

The Product The Vision

* Figures used with permission from Altera Corp.

2.5 Tbps

Serial I/O

Bandwidth

2.3 Tbps

Parallel (DDR4)

I/O Bandwidth



Wrap-Up

29IEEE Waves & Devices Meeting


30

Key Messages

• A connected world drives an accelerated demand for bandwidth.

• The increasing demand for bandwidth results in packaging

challenges and opportunities on a new scale.

• Innovation is needed in materials, process, and design.

• 2.5D and 3D package architectures are uniquely positioned to

address growing bandwidth challenges.



31

What Does This Mean for Packaging Engineers?

• There are lots of challenges

& interesting things to work

on today

• Materials & Process

• Design, Tools & Methods

• Architecture & Partitioning

• Even more innovation

needed for tomorrow! I/O, I/O … It’s off

to work we go!!!

… 2025?

… 2035?



32

References

1) Optical Internetworking Forum, http://www.oiforum.com/

2) Chittor, Suresh, “Memory Requirements, Trends and Challenges: Servers to Devices,”

ISSCC forum 2015.

3) Intel Corp., EMIB video, http://www.intel.com/content/www/us/en/foundry/emib.html

4) Altera Whitepaper, “Enabling Next-Generation Platforms Using Altera’s 3D System in

Package Technology,” https://www.altera.com/content/dam/altera-

www/global/en_US/pdfs/literature/wp/wp-01251-enabling-nextgen-with-3d-system-in-

package.pdf

5) Altera Stratix-10 FPGA and SoC Product Sheet,

https://www.altera.com/products/fpga/stratix-series/stratix-10/overview.html


http://www.oiforum.com/

http://www.intel.com/content/www/us/en/foundry/emib.html

https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/wp/wp-01251-enabling-nextgen-with-3d-system-in-package.pdf

https://www.altera.com/products/fpga/stratix-series/stratix-10/overview.html

i/o, i/o … so much data … oh, no!!!€¦ · ieee waves & devices meeting –phoenix chapter...

Documents