[Invited] Energy Efficient Network Design Tool for Green IP/Ethernet Networks

Naoaki YAMANAKA *, Sho SHIMIZU* and Gao Shan* *Department of Information and Computer Science, Faculty of Science and Technology, Keio University,

3–14–1 Hiyoshi, Kohoku-ku, Yokohama, 223–8522, Japan Email: ishikawa@yamanaka.ics.keio.ac.jp

Abstract — New energy efficient network design algorithm and tool for low power consumption named MIDORI is proposed. Network is used minimum set of nodes and links which can transfer all communication traffic under QoS restriction. QoS restrictions are included hop limit, bandwidth limit reliability and stability. Set-covered problem is applied to this algorithm and all links are modeled as “1” for on and “0” for off. To solve the optimum network configuration, parallel data flow type reconfigurable processer, DAPDNA is applied to solve this problem efficiently. The processor automatically produces the node/link set and confirms traffic QoS requirements. This algorithm can achieve optimum network resources. According to our evaluation results, it can achieve more than 25 % higher efficient than conventional holistic algorithm. And also the evaluation results show the 2 decade faster calculation than conventional sequential method using Pentium II processor. Using the design tool and newly developed remote power controlled L2 switch, experimental network is now under development. Using the proposed algorithm and tool, energy efficient IP/ Ethernet network can be realized. We can estimate that it can reduce about 38K ton CO2 par year. Keywords — Low power consumption, IP/Ethernet, Set-covered problem, Reconfigurable processor, PCE, Green IT

I. INTRODUCTION Recent progress on Internet service needs huge

performance on network throughput. Especially, video data transfer and rich web service make heavy load. According to this Internet service demand, energy consumption for IT equipment is also increased. Figure1 shows the forecast data of energy consumption for IT equipment. According to this figure, energy of router is increased dramatically[1]. In year of 2010, 13000 million kwh/year is used. That is double of a nuclear power plant.

To reduce the network energy consumption, there are several techniques are under developed. First one is IEEE, Energy Efficient Ethernet (EEE). This technique change link speed according to the data traffic demand. Second, employing low power voltage LSI reduces system power consumption. Third, dc power supply instead of a.c. power supply is employed to reduce conversion loss. Force, network virtualization technique such as virtual server and virtual router is used.

This paper proposes new energy efficient network design tool for IP and Ethernet network. The proposed method aggregates the traffic and turn off vacant links. In other words, as small number of links as possible are used for the communications. Network can power off the link under hop-limit, and link bandwidth constrain.

Fig.1 Energy consumption for IT equipment from T.Asami and S. Namiki, ECOC 2008, Tu.4.A.3, In Brussels Belgium, Sept. 23, 2008

Fig.2 Basic network configuration using PCE (Path Computation Element) for path control in the AS

II. LOW POWER NETWORK ARCHITECTURE Today’s network structure is shown in Fig.2. The

network consists of AS (Autonomous System) which includes several ten to one hundred of routers with controller. The traffic is controlled by PCE (Path Computation Element). Function of PCE is calculating route according to the traffic demand and network conditions. Our research target is realizing high-performance PCE which can calculate lowest power dispersion of the network.

Approach to the low energy consumption network is as follows;

A. Interface power off Some parallel links can be turn off if the traffic demand

is low. In that case, both side of interface is automatically power off. In addition, PCE takes care of this link as sleep link that state is physically existed but power is off.

B. Node power off Transit router which is not necessary to use will be power

off. We are now try to employ virtual router concept which can partially turn off the power.

Proposed low power desperation network calculation

method is illustrated in Fig.4. In Fig.4, there are 6 nodes and n links. First, creating all the on/off combination of links, total combination is 2n. The most simple or lowest power topology is all link power off. This case, all node cannot communicate each other. Next, one link is on, there are n combinations for this pattern. And so on, all the combination of on/off links are created. Network topology pattern which can carry all traffic demand is selected. For the router architecture, router can operate under the power dispersion proportion to the traffic demand. In addition, low load virtual router can move to another physical router and vacant router will be power off.

Simple diagram of parallel link is shown in Fig.3. The proposal network, parallel number can be automatically changed based on traffic demand. In this example, 1Gb/s × 4HW = 4Gb/s power dispersion can be reduced. However, some QoS restrictions rejected to the power off as describe here after.

Fig.3 Power down technique for parallel link according

to the traffic demand 1) All the traffic can be carried with proper margin. 2) Maximum hop number of the path can be

guaranteed. 3) Link divergence is needed to achieve reliable

communication.

Fig.4 Optimum network topology for Low power consumption

QoS guaranteed and minimum number of link topology will be employed

Flow-chart of the proposed method is shown in Fig.5.

Algorithm creates all combination of the network link topologies .

Fig.5 Flow chart of the proposed link search algorithm

III. HIGH ENERGY EFFICIENT NETWORK TOPOLOGY GENERATION

Combinatorial algorithm can be applied to the problem which is derived from the set cover problem, such as replica placement problem. The calculation time of replica placement problem increases rapidly when the network scale is large. We propose the new method that generates all combinations fast because no greedy algorithm can obtain the optimal solution. Our proposed method divides the combination into different groups which are executed in parallel. First data of each group are entered per clock cycle by pipeline operation. We implemented Beeler’s algorithm, which can generate all combinations in ascending order on DAPDNA-2, which is new parallel reconfigurable processor [3]-[6].

Figure 6 shows the pipeline operation when 6C3 is divided into 4 groups. 1st, 6th, 11th and 16th data are input data because 20 combinations are divided into 4 groups [4]. DNA matrix outputs Data2, Data7, Data12 and Data17, which are the next input data in Figure 6. The result of the last group gets delayed in 3 clocks compared with the one of the first group. The whole execution time is about quarter compared with original execution time. There are two problems that need to be solved. First, how can we calculate the first data of each group when combination is divided into different groups. Beeler’s algorithm can generate all combinations in ascending order but it has data dependence. It’s difficult to calculate any order pattern because each data increases irregularly. In order to solve this problem, we propose the new algorithm that generates any order pattern.

Second, what is the optimal division number which minimizes whole calculation clocks? The more division number increases, the more whole calculation clocks decreases. However, whole calculation clocks increases the other way around when the division number exceeds a certain value because the results get delayed in a clock compared with the one of previous group. The optimal division number depends on the number of combinations and calculation clocks of Beeler’s algorithm. In order to solve this problem, we think about the optimal division number in theory.

Fig.6 First data of each group are entered per clock cycle

by pipeline operation. DNA matrix outputs Data2, Data7, Data12 and Data17, which are next input data.

A. Beeler’s algorithm and Any-order pattern algorithm M.Beeler, R.W.Gosper, R.Schroppel proposed an

algorithm that generates all combinations picking k outcomes from n possibilities [8]. These combinations can be expressed in n-digit binary form. For example, 010110 represents (2, 3, 5) when n = 6. Combinations can be ordered in this way. (2, 3, 5) < (2, 4, 5) because 010110 < 011010. Beeler’s algorithm can generate all combinations from 000111 to 111000 in order. The detail of the algorithm is as follows.

1) Let S1 be what all bits are unset except for the least significant 1 of a combination X.

2) R= X + S1 3) Let S2 be what all bits are unset except for least

significant 1 of R. 4) S3 = (S2/S1) >> 1 – 1 5) Y = R|S3 is next to X. When n = 6, k = 3, X = 001110, for example, Y is

calculated as follows. 1) S1 = 000010 2) R = X + S1 = 010000 3) S2 = 010000 4) S3 = (S2/S1) >> 1 − 1 = 001000 >> 1 − 1 = 000011 5) Y = R|S3 = 010011 We propose the new algorithm that generates any order

pattern in combinations which are sorted in ascending order. Generally, the following equation is true.

∑−

−=−=

1

11

n

kikikn CC (5)

If you want to get m-th pattern, find the smallest x1 which satisfies the following inequation.

)11( 11

1

1

−≤≤−≥∑−=

− nxkmCx

kiki (6)

x1Ck-1 means the patterns whose most significant one is x1 bit and there are k − 1 ones between 0 and x1 – 1 because there are k ones in total. Hence, x1 bit of m-th pattern is 1.

m-th pattern corresponds m− -th in .

Replace m as follows. ∑ −

−= −1

1 11x

ki ki C 11 −kx C

∑−

−=−−→

1

11

1x

kiki Cmm

Next, find the smallest x2 which satisfies the following inequation.

)1( 122

2

2

−≤≥∑−=

− xxmCx

kiki

22 −kx C means the patterns whose most significant one is

x2 bit and there are k−2 ones between 0 and x2−1. Hence, x2 bit of the pattern is 1. x1, x2, · · · , xk can be obtained by repeating k times in a similar way. Set corresponding bit to 1, and you can get the m-th pattern.

For example, 6th pattern (m = 6) in 6C3 can be obtained as follows.

6C3 =2 C2 +3 C2 +4 C2 +5 C2 = 1 + 3 + 6 + 10 Apply the equation (5) to 4C2 because 4C2 includes 6th

pattern. Hence, x1 = 4,m → 2. 4C2 =1 C1 +2 C1 +3 C1 = 1 + 2 + 3 Conventinal (theretical) Conventional (experimental)

1

10

100

1000

24 25 26 27 28 29 30 31

Number of nodes

Theo

retic

al &

exp

erim

enta

l exe

cutio

n tim

e(m

sec)

Proposal (theoretical) Proposal (experimental)Apply the equation (5) to 2C1 because 2C1 includes 2nd pattern. Hence, x2 = 2,m → 1.

2C1 =0 C0 +1 C0 = 1 + 1 1st pattern corresponds 0C0. Hence, x3=0. Set

corresponding bit to 1, and the 6th pattern can be obtained, 010101.

B. Implementation on DAPDNA-2 Let n be the number of nodes except for the origin server

and k(≤ n) be the number of replicas. In our implementation, n ≤ 32 because one word is 32-bit length in PE. For example, we generate all combinations from 0000011 to 1100000 when n = 7, k = 2. Each node is represented by 32-bit data. Let i-th bit be 1 if this node covers node i. In expression 4, v, w-th bit of node w is 1 because w covers v. If OR between 2 replica and the origin server equals 1111111, the replication strategy covers all nodes. For example, the replication strategy is node {1, 5} when the combination is 0010001. Now, the following equations are true in Figure 1.

d(2, 0) ≤ q(2), d(3, 0) ≤ q(3), d(7, 0) ≤ q(7) d(2, 1) ≤ q(2), d(4, 5) ≤ q(4), d(6, 5) ≤ q(6) Node 0 represents 1000110, node 1 represents 0000011,

and node 5 represents 0111000. This replication strategy covers all nodes because OR between 3 data equals 1111111. If some replication strategies cover all nodes, we choose the minimum-cost combination.

After calculating the optimal division number, our proposed algorithm consists of following 3 processes.

1) Calculate m-th pattern according to the optimal division number.

2) Execute Beeler’s algorithm. 3) Using corresponding cover data, check that all

nodes can be covered. The result of process (1) which is executed by DAP is

stored in main memory. DNA reads this result from main memory and execute process (2), (3) by pipeline operation. Note that the proposed method can acheve ideal newwork topology with reasonable calculation period. [9-12]

IV. PERFORMANCE EVALUATION In this section, we compare the execution time of

DAPDNA-2 (166MHz) with that of Pentium 4 (2.8GHz). Let k be the number of replicas and n be the number of nodes except for the origin server and d be the number of partitions.

Figure 7(a) shows the execution time to generate all combinations when k = 8. Black plots represent

conventional method on Pentium 4, and white plots represent proposed method on DAPDNA-2. Circle plots represent theoretical execution time, and square plots represent experimental execution time. Figure 7(b) has a margin of error between theoretical and experimental time but increasing tendency is almost the same. In the proposed method, the execution time increase slowly as n increases because DAPDNA- 2 calculates in parallel using a pipeline operation. When n = 30, DAPDNA-2 reduces the execution time by 40 times compared to Pentium 4.

(a) Small aize of network with experiment and theory

(b) Theoretical estimation of calculation time Fig.7 y 40

tim

V. LINK ON/OFF CONTROL PROTOCOL reates

ne

w physical and logical (TE) Link state, th

s controlled by RSVP or LMP pr

DAPDNA-2 can reduce the execution time bes compared to Pentium 4 when the number of nodes is

30.

Low energy consumption network design engine ctwork topology in PCE. Real router / L2 switch is

controlled by this PCE. New control protocol, based on GMPLS extension has been proposed [13]. The proposed protocol is using OSPF extension, LMP extension and RSVP extension.

OSRF has a neat is power up / off state. Figure 8(a) shows the basic

OSPF extension images. Link power off / on iotocol extension as shown in Fig. 8(b). If the “Link

power off” state information is delivered to higher layer, LSP status is also change an “power off”. LSP will be

1.E-071.E-061.E-051.E-041.E-031.E-021.E-011.E+001.E+011.E+021.E+031.E+041.E+051.E+06

0 10 20 30 40 50 60 70 80 90 100 110

Number of nodes

Theo

retic

al e

xecu

tion

time

(sec

)

Conventional Proposal

(a) Basic OSRF extension

(b) RSVP or LMP protocol extension

(c) New LSP created by link power off

ig.8 New power control extension based on GMPLS

VI. CONCLUSION In orde n of lowest power

de

automatically established as shown in Fig.8(c).

F

r to obtain the optimal solutiospation network topology, we have proposed a fast

calculation method with reconfigurable processor DAPDNA-2 of IPFlex Inc. Our proposed method divides the combination optimally and performs pipeline operation. We have proposed the new algorithm that generates any order pattern in combinations which are sorted in ascending order and derived the optimal division number in theory. While the time complexity of conventional method is O(nCk), the time complexity of proposed algorithm is

kn CO .

eExperim ntal results have showed that the exectim

an

lation method, ideal network topologies ca

CKNOWLEDGMENT This work is su of the

M

REFERENCES [1] T.Asami and S. N y consumption for IT

ution e of the proposed algorithm increases slowly as n

increases because DAPDNA-2 calculates in parallel using a pipeline operation. When n = 30, DAPDNA-2 reduces the execution time by 40 times compared to Pentium 4.

This calculation topology result controls physical link d router by PCE. We have also proposed control

protocols using GMPLS RSVP-TE extension LMP

extension. Using this calcun be achieved. According to our evaluations, about 20%

of the network power can be reduced.

Apported by PREDICT program

inistry of Internal Affairs and Communications (MIC) of Japan. This work is also supported in part by a Grantin- Aid for the Global Center of Excellence for high-Level Global Cooperation for Leading-Edge Platform on Access Spaces from the Ministry of Education, Culture, Sport, Science, and Technology in Japan.

amiki , “Energequipment”,Proc. of, ECOC 2008, Tu.4.A.3, In Brussels Belgium, Sept. 23, 2008

[2] Yutaka Arakawa, Daisuke Ishii, Aya Tsurusaki, Naoaki Yamanaka, Hiroyuki Ishikawa, and Kosuke Shiba “Network Reconfigure Algorithm for Low Power Consumption”, IEICE Technical Reports, Vol.108, No.183, pp.13-18, August2008.

[3] Tomomi Sato, Hiroyuki Watanabe and Ysusyoshi Shiba, “ Implementation of Dynamically Reconfigurable Processor DAPDNA-2 ” IEEE VLSI-TSA International Symposium on VLSI Design, Automation, and Test, April2005.

[4] Hiyoyuki Ishikawa, Sho Shimizu, Yutaka Arakawa, Naoaki Yamanaka, and Kosuke Shiba, “Fast calculation method of Set Cover Problem on parallel reconfigurable processor DAPDNA-2”, TECHNICAL REPORT OF IEICE, Vol.107, No.414, RECONF2007-62, pp.p67-72 , January2008.

[5] Sho Shimizu, Taku Kihara, Yutaka Arakawa, Naoaki Yamanaka, and Kosuke Shiba, “A prototype of a dynamically reconfigurable processor based off-loading engine for accelerating the shortest path calculation with GNU Zebra,” 2008 Workshop on High Performance Switching and Routing (HPSR 2008), pp.131-136, May 2008.

[6] IPFlex Inc. (http://www.ipflex.com) Yutaka Arakawa, Naoaki[7] Hiroyuki Ishikawa, Sho Shimizu,

l) e to

Yamanaka, and Kosuke Shiba, “New Parallel Shortest Path Searching Algorithm based on Dynamically Reconfigurable Processor DAPDNA-2,” IEEE International Conference on Communications 2007 (ICC 2007), No.NSO5.2, June 2007.

[8] M.Beeler, R.W.Gosper, R.Schroeppel, HAKMEM mem.htm(http://www.inwap.com/pdp10/hbaker/hakmem/hak

[9] M.R.Garey, D.S.Johnson, Computers and Intractability: A Guidthe Theory of NP-Completeness. W.H. Freeman and Company, 1979.

[10] Hsiangkai Wang, Pangfeng Liu, Jan-Jan Wu, “A QoS-Aware Heuristic Algorithm for Replica Placement,” Grid Computing 7th IEEE/ACM International Conference, pp.96-103, September 2006.

[11] Xueyan Tang, Jianliang Xu, “QoS-Aware Replica Placement for Content Distribution,” IEEE Transactions on parallel and distributed systems, vol.16, No.10, pp.921-932, October 2005.

[12] David S.Johnson, “Approximation algorithms for combinatorial problems,” Journal of Computer and System Science, pp.256-278, 1974.

[13] Satoru Okamoto, Kou kikuta,” Proposing energy efficient network architecture, MIDOR”, MPLS 2009 booth demonstration, 2009