investigation of scalability of in0.7ga0.3as quantum well … · 2011-05-15 · investigation of...

Solid-State Electronics xxx (2011) xxx–xxx

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Solid-State Electronics

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Investigation of scalability of In0.7Ga0.3As quantum well field effect transistor(QWFET) architecture for logic applications

E. Hwang a,⇑, S. Mookerjea a, M.K. Hudait b, S. Datta a

a The Pennsylvania State University, University Park, PA 16802, USAb Virginia Tech, Blacksburg, VA 24061, USA

a r t i c l e i n f o a b s t r a c t

Article history:Received 7 October 2010Received in revised form 7 April 2011Accepted 12 April 2011Available online xxxxThe review of this paper was arranged byProf. S. Cristoloveanu

Keywords:InGaAsQuantum well FETs (QWFETs)Drift–Diffusion simulationBallistic effectEffective carrier injection velocityDouble-Gate (DG) QWFETs

0038-1101/$ - see front matter � 2011 Elsevier Ltd. Adoi:10.1016/j.sse.2011.04.013

⇑ Corresponding author. Tel.: +1 814 865 0519; faxE-mail address: [email protected] (E. Hwang).

Please cite this article in press as: Hwang E et alogic applications. Solid State Electron (2011), d

In this paper, the scalability of In0.7Ga0.3As QWFET is investigated using two-dimensional numericaldrift–diffusion simulation. Numerical drift–diffusion simulations were calibrated using experimentalresults on short-channel In0.7Ga0.3As QWFETs [7] to include the effects of velocity overshoot. Logic figuresof merit (sub-threshold slope, saturated threshold voltage, drain induced barrier lowering, ION/IOFF ratioover a specified gate swing, effective injection velocity and intrinsic switching delay) extracted fromthe numerical simulations are in excellent agreement with the experimental data. Three alternate QWFETdevice architectures are proposed and thoroughly investigated for 15 nm node and beyond logic applica-tions. Amongst them, double-gate In0.7Ga0.3As QWFET shows the best scalability in terms of logic figuresof merit, thus making it an ideal candidate for the design and demonstration of the ultimate scaledtransistor.

� 2011 Elsevier Ltd. All rights reserved.

1. Introduction

In today’s multi-core CPU era, as the dimension of silicon CMOScontinues to scale to meet the ever increasing demand for highertransistor count, the rising power dissipation (both static and dy-namic) has been identified as the critical brick wall to transistorscaling [1]. Aggressive supply voltage scaling to 0.5 V and belowwhile maintaining transistor performance is a direct path towardreducing power consumption. In this regard, III-V compound semi-conductor based quantum well field effect transistors (QWFETs)have recently attracted attention for low-power logic applications[2–4]. High indium content indium gallium arsenide (In0.7Ga0.3As),indium arsenide (InAs) and indium antimonide (InSb) QWFETs ex-hibit excellent electron transport property at both low and highelectric fields arising from a combination of: (i) low C-valley elec-tron mass, (ii) reduced impurity scattering due to modulation dop-ing, (iii) reduced interface roughness scattering because ofepitaxially grown smooth interfaces and (iv) large energetic sepa-ration between C and L-valleys. The low electron transport masscoupled with minimal back scattering from the channel back intothe source gives rise to higher source side effective injection carriervelocity (veff). The expected enhancement in injection velocity is

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l. Investigation of scalability ofoi:10.1016/j.sse.2011.04.013

sufficient to compensate for lower carrier density in the channelof III–V QWFETs due to the reduced density of states from lowerband mass compared to Si MOSFETs, and, hence, expected to deli-ver higher ON-current particularly at reduced supply voltagescompared to Si MOSFETs, thus enabling supply voltage scaling[5,6]. However, a key question persists on the scalability of theQWFET and its ability to compete with Si MOSFETs at lower supplyvoltage for the 15 nm technology node and below.

Recently, higher indium concentration In0.7Ga0.3As and InAschannel QWFETs have been experimentally demonstrated withgate length (LG) down to 50 nm with excellent short channel per-formance and high speed response operating at 0.5 V supply volt-age [7–9], albeit with large separation between the source anddrain metal electrodes (LSD = 2 lm). In order to implement III–VQWFETs in future high-performance logic applications, its scalabil-ity both in terms of physical gate length as well as the overall foot-print of the transistor should be thoroughly investigated.

In this paper, we provide a systematic study of the scalability ofIn0.7Ga0.3As QWFETs via two-dimensional numerical drift–diffu-sion (DD) simulation [10]. The paper is organized as follows. In Sec-tion 2, we perform calibration of the numerical simulator to theexperimental 50 nm LG In0.7Ga0.3As QWFETs [7,8], to match boththe ON-current in linear and saturation regime as well as thesub-threshold response. In Section 3, we investigate the effect ofboth lateral and vertical scaling on the In0.7Ga0.3As QWFET device

In0.7Ga0.3As quantum well field effect transistor (QWFET) architecture for

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2 E. Hwang et al. / Solid-State Electronics xxx (2011) xxx–xxx

performance down to physical gate length of 15 nm. In Section 4,we extract the effective carrier mobility in short-channel QWFETsand conclude that, with aggressive LG scaling, the ballistic mobilitylimits the short channel mobility due to near ballistic transport inthe channel, and conclude that the effective carrier injection veloc-ity, veff, near the source side is a quantitative and more pertinentindicator of transport in short-channel QWFETs than effectivemobility. Finally, in Section 5, we provide a quantitative estimateof the degradation of short-channel performance of conventionalIn0.7Ga0.3As QWFETs with LG = 15 nm. Therefore, we introducethree different QWFET architectures in this section, provide aquantitative assessment of the logic figure of merit of threeQWFETs, and propose the design for the ultimate scaled In0.7-

Ga0.3As QWFET architecture suitable for 15 nm technology nodeand beyond logic applications. The proposed architecture is genericand could be applied to next generation antimonide-basedQWFETs such as InAsxSb1�x and InyGa1�ySb, currently under inves-tigation [11].

2. Device simulation

Fig. 1 presents the schematic of the simulated and experimentalIn0.7Ga0.3As QWFET. The dimensions of the device are identical tothose reported in [7]. The composite channel consists of 3/8/4 nm thick In0.53Ga0.47As/In0.7Ga0.3As/In0.53Ga0.47As and featuresboth regular and buried-Pt gate stack with LG = 50 nm in directcontact with the upper In0.52Al0.48As barrier forming a Schottkyjunction. The In0.52Al0.48As barrier is doped with Si delta-dopingof 5.5 � 1012 cm�2 which is placed 3 nm above the compositechannel to provide electron carriers into the channel. The 20 nmthick In0.53Ga0.47As cap layer is n-type, heavily-doped one with1 � 1019 cm�3. The devices have total channel thickness ofTCH = 15 nm, the lateral spacer thickness (distance between then + doped layer and the gate electrode) of LSIDE = 80 nm and asource to drain electrode spacing of LSD = 2 lm. While the regularPt Schottky gate device has an effective insulator thickness ofTINS = 11 nm, the buried-Pt gate device has TINS = 7 nm. By model-ling the same device structure as the real device, we attempt tosimulate the associated access resistance including the contactones (RCONTACT = 50 X lm).

Fig. 1. Schematic of In0.7Ga0.3As QWFET device structure. The insulator thickness(TINS), the channel thickness (TCH), the distance between source and drain (LSD), andthe distance between the gate and cap layer (LSIDE) are specified. While the regularPt Schottky gate device has an effective insulator thickness of TINS = 11 nm, theburied-Pt gate device has TINS = 7 nm. For the calibration, the gate length (LG) isequal to 50 nm.

Please cite this article in press as: Hwang E et al. Investigation of scalability oflogic applications. Solid State Electron (2011), doi:10.1016/j.sse.2011.04.013

The two dimensional numerical simulation self-consistentlysolves the Poisson’s equation with carrier continuity equationusing a drift–diffusion model. To accurately capture the non-equi-librium carrier transport (such as velocity overshoot effect), weemploy the Canali mobility model (1) [12] with appropriatemodifications.

lðEÞ ¼ ðaþ 1Þllow

aþ 1þ ðaþ1ÞllowEvsat

� �b� �1

b

ð1Þ

The model parameters are determined by matching the simula-tion results to the experimental results. The parameters used in thecalibration exercise are llow(In0.7Ga0.3As) = 12,000 cm2/V s, llo-

w(In0.53Ga0.47As) = 10,000 cm2/V s, vsat = 9.5 � 107 cm/s, a = 0 andb = 0.6. Here, vsat is the saturation velocity and b is a constantreflecting the steepness of the carrier velocity profile in the chan-nel. They are defined as vsat = 0.93 � 107 cm/s and b = 2 for elec-trons by default. However, in order to take into account thevelocity overshoot effect at high fields and maintain the accuratevelocity at low fields, a high saturation velocity value and a lowerthan unity beta value are used within the drift–diffusion simula-tion framework, which is similar to the approach outlined by Bude[13]. Therefore, it leads to accomplish simulation time efficiencyand accuracy simultaneously [14].

In order to calibrate the simulation results with the experimen-tal results in [7], two 50 nm gate-length In0.7Ga0.3As QWFET de-signs with regular and buried-Pt gate electrodes are simulatedwith TINS = 7 nm and TINS = 11 nm, respectively. Fig. 2 shows excel-lent agreement between the simulated and the experimental re-sults in both sub-threshold as well as in upper-threshold regime,thereby validating the approximation of the carrier transport mod-el and the model parameters defined in this paper. The gate leak-age portion of the device transfer characteristics was notmodelled in our simulation results, and will not affect theconclusions obtained in the succeeding sections.

3. Effect of lateral and vertical scaling

In this section, we first assess the impact of physical gate lengthscaling on the performance of conventional In0.7Ga0.3As QWFETsfor 15 nm logic applications and beyond. We simulate In0.7Ga0.3AsQWFETs with buried-Pt gate (TINS = 7 nm, TCH = 15 nm) for differentgate-lengths ranging from 15 to 200 nm and evaluate the various

-1.5 -1.0 -0.5 0.0 0.510-10

10-8

10-6

10-4

10-2

TINS=7nmTCH=15nm

ID [A

/µm

]

VG [V]

Solid line: SimulationSymbol: Experiment

TINS=11nmTCH=15nm

Fig. 2. Transfer characteristics of 50 nm LG In0.7Ga0.3As QWFETs featuring both theregular Pt Schottky gate and the buried-Pt gate. The simulation results arecalibrated when TINS = 11 nm (blue, solid) and TINS = 7 nm (red, solid). (For inter-pretation of the references to colour in this figure legend, the reader is referred tothe web version of this article.)



0 50 100 150 200 2500

1

2

3

4

BufferQWBarrier Cpar

CGG(intrinsic)

G

S D

Gat

e de

lay(

CV/

I) [p

sec]

Lg [nm]

Simulation Experiment

TINS=7nmTCH=15nmLSIDE=80nm

Fig. 4. Intrinsic gate delay (CV/I) versus LG for In0.7Ga0.3As QWFETs.

E. Hwang et al. / Solid-State Electronics xxx (2011) xxx–xxx 3

figures of merit such as sub-threshold slope (SS), drain-inducedbarrier lowering (DIBL), threshold voltage (Vt) roll-off, and ION/IOFF

ratio. The figures of merit are compared with the experimental re-sults [7] as illustrated in Fig. 3. As a result of the LG scaling, it re-sults in large DIBL, causing the degradation of SS. This isaccompanied by significant Vt roll-off trend and the consequent de-crease in ION/IOFF ratio. To extract the ION and IOFF, we have appliedthe methodology outlined by Chau et al. [1]. First, Vt is defined as avalue of gate voltage where the drain current (ID) corresponds to1 lA/lm. Then, ION is determined from the value of ID at whichVGS corresponds to approximately two-third of VCC above Vt. In asimilar manner, IOFF is chosen as ID where VGS is one-third of VCC

below Vt.Intrinsic gate delay (CV/I), as shown in Fig. 4, is another impor-

tant figure of merit for high-speed logic applications. In extractingthe CV/I, C is the gate capacitance (CGG) defined at the same gatebias condition as ION, I is ION and V is the supply voltage of opera-tion. The gate capacitance takes into account the barrier capaci-tance as well as the quantum capacitance in the channel arisingfrom the limited density of states (DOS) as well as the parasiticcapacitance from the gate to source/drain fringing electric field.The total gate capacitance is reduced with reducing LG due to geo-metric effect, thereby, leading to the decrease in gate delay. How-ever, at LG = 15 nm, the inherent parasitic capacitances arising fromgate to source/drain fringing electric field form a significant por-tion of the total gate capacitance, and, therefore, CGG is hardly re-duced further [15,16]. In addition, ION is greatly decreased due topoor electrostatics, thus adversely affecting the total gate delay.

In addition to LG scaling, LSIDE needs to be scaled in order toachieve a small device footprint needed for 15 nm or below. Ini-tially, LSIDE is kept at 80 nm and subsequently decreased to15 nm. Table 1 summarizes the loss in electrostatic integrity ofthe QWFET as a direct consequence of LSIDE scaling at the 15 nmLG. To sustain a scaling path for QWFET with 15 nm physical gatelength, we first normalize the physical gate length to the electro-static scaling length of the device. As Yan et al. indicate in [17],the scaling rule is dictated by both electrostatic scaling length (k)in (2) and aspect ratio (c = LG/k).

0 50 100 150 20060

80

100

120

140


(c)

SS [m

V/de

c]

LG [nm]

0 50 100 150 200L [nm]

(a)


-0.8

-0.6

-0.4

-0.2

0.0

V t [V]

SimulationExperiment


Fig. 3. Logic figures of merit for In0.7Ga0.3As QWFETs with different LG. In0.7Ga0.3As QWFfrom 15 to 200 nm are designed and the logic figures of merit (SS, DIBL, Vt, ION/IOFF ratio


k ¼ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffieSi

eoxtSitox

rð2Þ

Here, the electrostatic model originally developed for fully-de-pleted SOI MOSFETs (FD-MOSFETs) is applicable for conventionalIn0.7Ga0.3As QWFETs and k is calculated to be 10 nm by takingthe relative contribution of In0.52Al0.48As and composite channelInGaAs layer and their effective permittivity values into account[17,18]. To maintain the appropriate sub-threshold behaviour, cshould be maintained at least at 5 and higher. Therefore, one ofthe promising options is the vertical scaling of the conventionalIn0.7Ga0.3As QWFETs leading to reduction of both TINS and TCH.Table 1 summarizes the improvement in the device performancewith the vertical scaling. The insulator thickness and the channelthickness are reduced from 7 to 4 nm and from 15 to 7 nm, respec-tively. The simulation results indicate that vertical scaling indeedcontributes to a better electrostatic integrity and, therebyimproves the SS, DIBL, Vt-roll off and ION/IOFF ratio. To further im-prove the electrostatic integrity of the In0.7Ga0.3As QWFETs, wealso investigate the effect of compensation doping (NA) of the bot-



(d)

(b)0 50 100 150 200

LG [nm]

0 50 100 150 200LG [nm]

0

100

200

300

400

500

DIB

L [m

V/V]

103

104

105



I ON/I O

FF ra

tio

ETs with buried-Pt gate (TINS = 7 nm, TCH = 15 nm) for different gate-lengths ranging) are extracted.



Table 1Device performance comparison. At LG = 15 nm, LSIDE is reduced from 80 nm to 15 nm (in column 2). To further improve the device performance, TINS and TCH are reduced from7 nm to 4 nm and from 15 nm to 7 nm, respectively (in column 3). To increase the buffer layer doping (NA) to 1 � 1018 cm�3 leads to improvement in the electrostatic integrity,but the increase in access resistance suppresses the ON-current (in column 4). Bold values indicate the change in the current simulation from the previous simulation.

LG = 15 nm TINS = 7 nm TINS = 7 nm TINS = 4 nm TINS = 4 nm(VCC = 0.5) TCH = 15 nm TCH = 15 nm TCH = 7 nm TCH = 7 nm

LSIDE = 80 nm LSIDE = 15 nm LSIDE = 15 nm LSIDE = 15 nmNA = 8 � 1016 cm�3 NA = 8 � 1016 cm�3 NA = 8 � 1016 cm�3 Na = 1 � 1018 cm�3

DIBL (mV/V) 461.3 595 298 135.7SS (mV/dec) 131.9 152.6 109.9 101.8Vt.sat (V) �0.71 �0.85 �0.24 0.26ION/IOFF 1.18 � 103 5.71 � 102 3.59 � 103 4.67 � 103

ION (A/lm) 6.890 � 10�5 4.963 � 10�5 1.184 � 10�4 1.115 � 10�4

0.0 0.1 0.2 0.3 0.4 0.50

2

4

6

8

-0.6 -0.3 0.0 0.3 0.60.0

0.5

1.0

1.5

LG=50nmTINS=7nmTCH=15nm

VD=0.05

ID [A

/um

]

VG-Vt [V]

Analytical Experiment

x10-4

Effe

ctiv

e M

obili

ty c

m2 /V

s

VG-Vt [V]

µeff (LG=50nm)µeff (LG=100nm)µeff (LG=150nm)

x103

TINS=7nmTCH=15nm VD=0.05

0.01 0.1 1 10 100103

104

105

[]

Gate Length [µm]

µeff(In0.7Ga0.3As) (Analytical model in [20]) In0.7Ga0.3As QWFET (Simulation)

T=300K

(a) (b)

Fig. 5. (a) The effective mobility as a function of gate bias for In0.7Ga0.3As QWFETs with 50 nm, 100 nm and 150 nm LG. (b) The effective mobility as a function of LG forIn0.7Ga0.3As QWFETs. The effective mobility values of QWFETs (brown, triangle) from simulations are in close agreement with the one obtained from Mathiessen’s rule

1=leff ¼ 1=lballistic þ 1=lbulk

� �in [20] (green, solid). (For interpretation of the references to colour in this figure legend, the reader is referred to the web version of this article.)

-2 0 20

2

4

6

8

VSAT(In0.53Ga0.47 As)=0.8x107 [cm/s]

TINS=7nmTCH=15nm

Elec

tron

Vel

ocity

[cm

/s]

Normalized LG [x/LG]

LG=50nm LG=100nm LG=150nm

VD=0.5VG-Vt=0.3

x107

VSAT(InAs)=3.5x107 [cm/s]

Fig. 6. The effective carrier injection velocity profile in the channel with thechannel normalized. veff for 50, 100 and 150 nm LG In0.7Ga0.3As QWFETs is directlyextracted from the simulation at the conduction band peak near the source end atVD = 0.5 V and VG � Vt = 0.3 V. vsat for InAs and In0.53Ga0.47As are obtained from [23].

0 100 200 300 400 5000

1

2

3

4

5

6

v eff [c

m/s

]

DIBL [mV/V]

x107

In0.7Ga0.3As QWFET(TCH=15nm, TINS=7nm) In0.7Ga0.3As QWFET(TCH=13nm, TINS=4nm) Strained Si nFETs

Empty symbol : ExperimentalSolid symbol : Simulation

VD=0.5VG-Vt=0.3

Fig. 7. The effective carrier injection velocity (veff) versus DIBL for various LG

In0.7Ga0.3As QWFETs from simulations (solid) with the experimental data for-In0.7Ga0.3As QWFET and strained Si nFETs (symbols) at VD = 0.5 V andVG � Vt = 0.3 V. In0.7Ga0.3As QWFETs from simulations have TINS = 7 nm andTCH = 15 nm, while the experimental In0.7Ga0.3As QWFETs from [24,25] haveTINS = 4 nm and TCH = 13 nm. Also, veff for strained Si nFETs is plotted together atthe same bias conditions.


tom barrier layer on the device performance. As NA is increasedfrom 8 � 1016 cm�3 to 1 � 1018 cm�3, both DIBL and SS improveand Vt increases. However, increasing the buffer layer dopingresults in higher access resistance, as the increased p-type dopingin the bottom barrier layer pinches off the access regions leading tohigh REXT, which reduces the ON-current, as shown in Table 1.


4. Ballistic effect and short channel transport

As the device dimension is scaled down, there is a transition indevice transport behavior from the diffusive toward the ballisticlimit. Unlike silicon MOSFETs with moderate mobility values,




QWFETs with III–V compound semiconductors possess high elec-tron mobility up to 15,000 cm2/V s or even higher. For example,In0.7Ga0.3As QWFET has a low-field electron mobility of12,000 cm2/V s with carrier density of 2 � 1012 cm�2 in the channeland thus, its mean-free-path is calculated to be approximately150 nm. Therefore, QWFETs with gate-length approaching 15 nmare expected to operate close to the ballistic limit [19] across arange of operating bias conditions. In order to quantify the signif-icance of ballistic transport, we have investigated the short-chan-nel mobility of QWFETs in detail in this section.

As mentioned earlier, the high carrier mobility in long channelIII–V based QWFET arises from a combination of its low electronmass, reduced Columbic scattering and lower interface roughnessscattering. However, in the short-channel QWFETs, electrons arelaunched with thermal velocity (Vth) from source into the channeland traverse the channel encountering few collisions. In such a sce-nario, the actual channel resistance is weakly dependent on the

Fig. 8. (a) Schematic of 15 nm LG inverted-In0.7Ga0.3As QWFET with TINS = 1 nm and TC

doping (NA = 5 � 1017 cm�3), TINS = 4 nm and TCH = 7 nm. To mitigate the higher accesIn0.52Al0.48As barrier layer in the InP etch stopper layer. (c) Schematic of 15 nm LG dou60 nm gate-pitch footprint, LSIDE is aggressively reduced down to 15 nm.


physical gate length of the device, and any attempt to estimatethe short-channel mobility as a function of LG results in values low-er than their long channel values. In this respect, the effective car-rier mobility for short-channel devices operating close to theballistic limit is primarily limited by the so-called ‘‘ballistic mobil-ity’’, whereas the one for long-channel devices is primarily gov-erned by the bulk mobility. The ballistic mobility is given by Eq.(3) in [20].

lballistic ¼2qL

pmV thð3Þ

In order to extract the effective mobility for short-channel In0.7-

Ga0.3As QWFETs, the experimental transfer characteristics of In0.7-

Ga0.3As QWFETs (50 nm, 100 nm and 150 nm LG) are obtained[7,8].

H = 7 nm. (b) Schematic of 15 nm LG In0.7Ga0.3As QWFET with high bottom-barriers resistance problem, the second delta doping layer is incorporated 1 nm aboveble-gate In0.7Ga0.3As QWFET with TINS = 4 nm and TCH = 6 nm. To make suitable for




ID ¼ CGGw

LeffðVG � V tÞ

llow

ð1þ ðhðVG � V tÞÞbÞ1b

VD ð4Þ

Effective electron mobility values in the linear operation regimeare calculated using Eq. (4) in [21], where CGG is a combination ofthe barrier capacitance and the centroid capacitance. Also, both hand b are adjustable parameters to reflect the dependence of thegate electric field on the channel transport. As seen in the insetof Fig. 5 (LG = 50 nm), the deviation of the transfer characteristicfrom linear Vg dependence at high gate bias regime is capturedby introducing h = 2.8 and b = 3 (analytical model with b = 1 andhigher values of h results in the underestimation of ID). The ad-justed h and b match well with the experiments for 50 nm,100 nm and 150 nm LG In0.7Ga0.3As QWFETs. Physically, the highervalue of b used in the analytical mobility model reflects the non-stationary effect related to the velocity overshoot near the drainend.

Fig. 5a shows the effective mobility as a function of gate bias forIn0.7Ga0.3As QWFETs with 50 nm, 100 nm and 150 nm gate-length.It is clear that the effective mobility reduces as LG is scaled down.In Fig. 5b, the effective channel mobility of short-channel QWFETsis in close agreement with the one obtained from Mathiessen’s rule1=leff ¼ 1=lballistic þ 1=lbulk

� �in [20] which directly arises from the

transmission factor being the ratio of the mean-free-path to thephysical LG. However, this apparent degradation in short channelmobility is not an actual concern for scaled In0.7Ga0.3As QWFETperformance. Rather, the effective carrier injection velocity (veff)at the conduction band peak near the source end (injection veloc-ity) becomes more significant. The ON-current is primarily limited,not by the effective carrier mobility, but by the effective carrierinjection velocity as short-channel devices enter the ballisticregime [22].

ID ¼ COXWvTtc

1þ rc

ðVGS � V tÞ ð5Þ

0 50 100 150 20060

80

100

120

140

SS [m

V/de

c]

LG [nm]

0 50 100 150 200LG [nm]

-1.0

-0.5

0.0

0.5

V t [V]

Simulation DG-QWFET i-QWFET QWFET with BBD


Fig. 9. Logic figures of merit for different In0.7Ga0.3As QWFET device architectures. ComQWFETs is improved due to better device architecture schemes. Among them, double-interpretation of the references to colour in this figure legend, the reader is referred to


v inj ¼ vTtC

1þ rC

ð6Þ

Eq. (5) shows the dependence of drain current on the transmis-sion (tc = k/(L + k)) and reflection coefficients (rc = L/(L + k)) as pre-dicted from scattering theory [22] and Eq. (6) shows thedependence of injection velocity on the transmission coefficient.Consequently, due to the low electron mass in In0.7Ga0.3As QWFETand very little back scattering from the channel into the source, ahigh injection velocity can be achieved. Further, the increase inthe effective injection velocity with LG scaling improves the drivecurrent.

From a careful calibration of the saturation ON-current for50 nm, 100 nm and 150 nm In0.7Ga0.3As QWFETs [8] by adjustingvsat and b [12], the effective electron velocity is directly extractedfrom the plot of carrier velocity profile in Fig. 6 at the conductionband peak near the source end at VD = 0.5 V and VG � Vt = 0.3 V.InAs and In0.53Ga0.47As vsat values are obtained from [23]. Fig. 7plots veff versus DIBL for In0.7Ga0.3As QWFETs from 15 to 200 nmLG. Since the effective carrier injection velocity for In0.7Ga0.3AsQWFETs in [7] is not available, it is extracted from experimentaldata in [24] and compared with the simulation results. The In0.7-

Ga0.3As QWFETs in [24,25] possess TCH = 13 nm, TINS = 4 nm and LSI-

DE = 80 nm with the gate-length ranging from 30 to 130 nm. Theireffective carrier injection velocity values were also extracted underthe same bias conditions. In Fig. 7, it is clearly shown that the effec-tive carrier injection velocity increases as the electrostatic integrityaggravates. However, at a fixed DIBL value (100 mV/V), the simula-tion result shows about 6.9 times higher veff for In0.7Ga0.3AsQWFETs than the one for strained Si nMOSFETs in [5] which isabout 4.06 � 106 cm/s at VD = 0.5 V and VG � Vt = 0.3 V. This in-crease in injection velocity for III–V compound semiconductors isa necessity in order to compensate for lower carrier density inthe channel of III–V QWFETs due to the reduced density of statesin In0.7Ga0.3As QWFETs compared to Si MOSFETs.

0 50 100 150 200LG [nm]

0 50 100 150 200LG [nm]

0

100

200

300

400

500

DIB

L [m

V/V]

103

104

105



I ON/I O

FF ra

tio

pared to conventional In0.7Ga0.3As QWFETs (red line), the scalability of all threegate In0.7Ga0.3As QWFET shows the best scalability and electrostatic integrity. (Forthe web version of this article.)



0 100 200 300 400 5000

1

2

3

4

5

6v ef

f [cm

/s]

DIBL [mV/V]

x107 DG-QWFET (TCH=6nm, TINS=4nm) i-QWFET (TCH=7nm, TINS=1nm) QWFET with BBD (TCH=7nm, TINS=4nm) In0.7Ga0.3As QWFET(TCH=15nm, TINS=7nm) In0.7Ga0.3As QWFET(TCH=13nm, TINS=4nm) Strained Si nFETs

Empty symbol : ExperimentalSolid symbol : Simulation

VD=0.5VG-Vt=0.3

Fig. 10. The effective carrier injection velocity (veff) versus DIBL for differentIn0.7Ga0.3As QWFET device architectures. It indicates that the extracted veff valuesfor three QWFET architectures exceed that of the conventional QWFETs (red line).Consequently, amongst them, double-gate In0.7Ga0.3As QWFETs represent thehighest veff at a fixed DIBL value. (For interpretation of the references to colour inthis figure legend, the reader is referred to the web version of this article.)


5. Scalable QWFET architectures

Using the calibrated numerical simulation from Sections 3 and4, three different In0.7Ga0.3As QWFET device architectures are stud-ied; inverted QWFET (i-QWFET), QWFET with higher bottom-bar-rier doping (QWFET with BBD) and double-gate QWFET (DG-QWFET). For 15 nm node and beyond logic applications, LG andLSIDE are aggressively scaled down to 15 nm, thus making themsuitable for a 60 nm contacted gate-pitch.

In an inverted-In0.7Ga0.3As QWFET design shown in Fig. 8a, TCH

is kept at 7 nm and TINS is reduced down to 1 nm, thereby, resultingin a better gate control. The gate leakage is ignored in this studysince in future devices a high-k dielectric will be integrated withthe QWFET architecture [26]. Next, we have investigated the In0.7-

Ga0.3As QWFETs with higher bottom-barrier doping shown inFig. 8b, where the overall electrostatic integrity is significantly im-proved compared to the conventional In0.7Ga0.3As QWFETs. ThisQWFET with higher bottom-barrier doping has TINS = 4 nm andTCH = 7 nm. Additionally, to mitigate the high access resistanceassociated with the carrier depletion effects arising from higherbottom barrier p-type doping, a second delta doping layer is incor-porated 1 nm above the In0.52Al0.48As barrier layer in the InP etchstopper layer. Finally, a double-gate In0.7Ga0.3As QWFET structureis shown in Fig. 8c with TINS = 4 nm and TCH = 6 nm. Fig. 9 comparesthe logic figures of merit for the three different QWFET architec-tures. Compared to conventional In0.7Ga0.3As QWFETs (red line),the scalability of all three QWFETs is improved due to better devicearchitecture schemes. The effective carrier injection velocity versusDIBL is also plotted for three QWFET device architectures in Fig. 10.It indicates that the extracted veff values for three QWFET architec-tures exceed that of the conventional QWFETs (red line). However,the reason for the different peak values of veff at LG = 15 nm origi-nates from the relationship between the mean-free-path (k) andthe effective mobility (leff) [19]. From Dn = Vthk/2 and Einstein rela-tion, the mean-free-path is dependent on the mobility values forthe three different QWFET architectures which are different dueto the gate-field dependence as captured quantitatively by theCanali transport model. Consequently, double-gate In0.7Ga0.3AsQWFETs exhibit the highest effective carrier injection velocity ata fixed DIBL value and deliver the best logic performance (SS, DIBL,Vt-roll off and ION/IOFF ratio) due to its electrostatic robustness, thusmaking it a strong candidate for the design of the ultimate scaledtransistor.


6. Conclusions

The scalability of conventional In0.7Ga0.3As QWFETs is thor-oughly investigated using a calibrated two-dimensional numericaldrift–diffusion simulation. The non-equilibrium transport effectdue to velocity overshoot in short channel In0.7Ga0.3As QWFET isaccurately captured in the modified drift–diffusion model. Theconventional In0.7Ga0.3As QWEFTs show a poor scaling behaviourdown to LG = 15 nm. In addition to LG scaling, LSIDE is also scaleddown to achieve a small device footprint, which degrades the over-all device performance further and highlights the necessity ofaggressive vertical scaling of the device. The importance of ballisticeffect in short-channel QWFETs is emphasized and the limitationson the extracted effective short channel mobility due to ballistic ef-fect are examined in detail. The significance of source side injectionvelocity is also pointed out for III-V QWFETs, thus making veff ver-sus DIBL an important figure of merit to benchmark variousQWFET device architectures operating in the quasi or near ballisticregime. Finally, three alternate QWFET device architectures areproposed and thoroughly investigated for the 15 nm node and be-yond logic applications. Amongst them, double-gate In0.7Ga0.3AsQWFET has the best logic figures of merit and the highest effectivecarrier injection velocity, thus making it an ideal candidate for thedesign and demonstration of the ultimate scaled transistor.

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