introduction to physical design

7/29/2019 Introduction to Physical Design

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Physical Design of ICsby

MUNISH VERMA, Astt. Prof.

Dept of ECE,H.C.T.M, KAITHAL


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VLSI Design Cycle

System Specification

Functional Design

Logic Design

Circuit Design

X=(AB*CD)+(A+D)+(A(B+C))

Y=(A(B+C))+AC+D+A(BC+D))


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Physical Design

Fabrication

Packaging

VLSI Design Cycle


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Y-Chart


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Physical Design

Physical design (or layout phase) is the process of

determining the physical location of active devices

and interconnecting them inside the boundary of a

VLSI chip (i.e., an integrated circuit).

The physical design cycle consists of

1. Partitioning

2. Floorplanning and Placement

3. Routing

4. Layout Optimization & verification


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Layout Methodologies

Partitioning is the task of dividinga circuit into smaller parts.

Floorplanning is the determinationof the approximate location of each

module in a rectangular chip area.


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Placement, when each module isfixed, that is, has fixed shape and

fixed terminals, is the determinationof the best position for each module

Global routing decomposes a large

routing problem into small,manageable problems for detailedrouting.


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Detailed routing follows the globalrouting to effectively realize

interconnections in VLSI circuits.


Layout optimization is a post-processing step . In this stage the

layout is optimized, for example, by

compacting the area

Layout verification is the testing of

a layout to determine if it satisfies

design and layout rules .


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Layout Rules & Circuit Abstraction

A circuit is laid out according to a set of layout

rules (or geometric design rules).

The layout rules, being in the form of minimum

allowable values for certain widths, separations,

and overlaps, reflect the constraints imposed by the

current technology .

R1. Wire width : Each wire in layer Li, (1 i v) has a

minimum width wi.

wi > wi-1


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Layout Rules & Circuit Abstraction

R2. Wire separation : Two wires in layer Li have a

minimum separation of si

R3. Contact rule : To connect two wires

in layers Li and Lj (i < j) a contact (via)

must be established . The two wires

must overlap for ej x ej units and the

contact cut must be aj x aj units.


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A circuit C = {M,N} consists of a collection M = {M1, .. . , Mm} of modules-each module being a collection

of active devices-and a set N ={N1, . . . , Nn} of nets.Each net specifies a subset of points on theboundary of the modules to be interconnected.A circuit graph G

C

is a hypergraph associated with C,where vertices correspond to the modules andhyperedges correspond to the nets . A solution to the grid layout problem consists of

embedding each module Mi, (1 < i < m) of the circuiton the grid using a finite collection of tiles andinterconnecting the terminals of each net by meansof wires in the region outside the modules .


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Cell Generation

In VLSI design, a logic function is implemented by

means of a circuit consisting of one or more basic

cells. The set of cells form a library that can be

used in the design phase.Cell generation techniques are classified as

random generation or regular style.A random generation technique is obtained by

placing the basic components and interconnecting

them. That is, there is no regular connection pattern.

It is difficult to create a library of such cells because

of their complexity.

In contrast, in a regular style the interconnection

technique follows a regular pattern.


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1. Programmable Logic Arrays


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3 W i b A d G M i


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3. Weinberger Arrays and Gate Matrices

Weinberger Arrays was one of the firstmethods for regular-style layout. The idea is to

have a set of columns and rows, each rowcorresponding to a gate signal and the columnsresponsible for realization of internal signals.

Gate matrix layout was first introduced byLopez and Law as a systematic approach toVLSI layout. One of the objectives in the gate matrix layout

problem is to find a layout that uses the minimumnumber of rows by permuting columns. The structure of the gate matrix layout is asfollows:

d


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cntd


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L t E i t


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Layout Environments

Full Custom Semi Custom Universal

Designer designs all circuitry

& interconnection paths

Library of pre-designed

cells is available

Designer programs the

interconnections e.g.

PLA, FPGA

No Restrictions Restrictions imposed on

the organization of cells

Designer chooses the

appropriate ones &

places them

Time consuming Can be designed faster Can be designed faster

Good Area utilization Area efficiency is

sacrificed

Area efficiency is

sacrificed


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G t A & S f G t


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Gate Arrays & Sea-of-Gates In a gate array, each cellis an array of transistors. Each cell is capable of

implementing a simple gateor a latch by interconnectinga set of transistors. The cells are arranged inrows to allow spaces for

routing channels. In sea-of-gates architecture,the whole substrate is filled withtransistors. All transistors in gate arrays are prefabricated. The entire

gate array substrate is prefabricated up to contact layer. Thepatterns of metals 1 and 2 define the cell functions and routing. Thus only a fraction of masks needs to be designed. Thisreduces the probability of failure. Also, since the early processing steps are prefabricated,processing time is shortened.

FPGA


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FPGAs All the circuit elements of a FPGA are prefabricated. In aPLA, only the connections are programmable. However in aFPGA, not only are the connections programmable, the cells

are also programmable to achieve different functions. Each cell of a FPGA typically contains flip-flops, multiplexors,and programmable functional gates. The gates can usuallyrealize any function of a small set of inputs. It may also contain testing circuitry for fabrication. This is an

advantage over the standard cells and gate arrays, wheretesting circuitry must be incorporated into the functionalcircuitry and the designer has to take into consideration theextra testing circuitry. The cells may be organized in one-dimensional or two-

dimensional manner. Several types ofrouting resources are available. There areglobal wires that connect to every cell to provide globalcommunication. Shorter wire segments are used for localsignal communication.


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Multichip module (MCM) technologyIn MCM technique,

several s/c chips,interconnected in ahigh densitysubstrate, are placedinto a single package Compared withsingle chip packagesor surface mountpackages, MCMs can reduce circuit board area by five to

ten times and improve system performance by 20% or more. Chips are placed and bonded on a surface at the top layer(called the chip layer). Below the chip layer, a set ofpin redistribution layers isprovided for distributing chip I/O pins forsignal distribution

layers

introduction to physical design

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