introduction to ic test

EL/CCUT T.-C. Huang Apr. 2004

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Introduction to IC TestIntroduction to IC Test

Tsung-Chu Huang(黃宗柱 )

Department of Electronic Eng.Chong Chou Institute of Tech.

Email: [email protected]

2004/04/26


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Bonus Project 1

1. Write a set of C (or C++) programs to read the ISCAS85 benchmark.

2. Construct an internal model (data structure).3. Do functional logic simulation in the internal model.4. Add a bit for fault insertion in each gate and do serial fault

simulation.


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Example for Proj#1/ (1)ISCAS85 Benchmark TDL Example

MODULE : C17;INPUTS : I1gat, I2gat, I3gat, I6gat, I7gat;OUTPUTS : I22gat, I23gat;DESCRIPTION : TDL file created by Carafe of

HemlockUSE :DEFINE : aoi21s_0(q=I7) =

aoi21s(a1=I10,a2=I7gat,b=I13); ai2s_3(q=I10) = ai2s(a=I3gat,b=I6gat); ai2s_2(q=I22gat) = ai2s(a=I8,b=I12); i1s_1(q=I23gat) = i1s(a=I7); i1s_0(q=I13) = i1s(a=I12); ai2s_1(q=I12) = ai2s(a=I2gat,b=I10); ai2s_0(q=I8) = ai2s(a=I1gat,b=I3gat);END : MODULE;


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Example for Proj#1/ (2)ISCAS85 Benchmark Verilog Example

module C17(I1gat, I2gat, I3gat, I6gat, I7gat);input I1gat, I2gat, I3gat, I6gat, I7gat;output I22gat, I23gat;wire I7, I8, I10, I12, I13;// ISCAS85 C17 Circuits in Verilog

aoi21s aoi21s_0(.q(I7), .a1(I10), .a2(I7gat), .b(I13));ai2s ai2s_3 (.q(I10), .a(I3gat), .b(I6gat));ai2s ai2s_2 (.q(I22gat), .a(I8), .b(I12));ils ils_1 (.q(I23gat), .a(I7));ils i1s_0 (.q(I13), .a(I12));ai2s ai2s_1 (.q(I12), .a(I2gat), .b(I10));ai2s ai2s_0 (.q(I8), .a(I1gat), .b(I3gat));endmodule;


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Example for Proj#1/ (3)TDL Parser and Internal Model

#include <stdio.h>#include <stdlib.h>#include <string.h>#include <alloc.h>#define CALLOC(n,x) ((x *)calloc(n,sizeof(x)))

typedef struct line_struct LineType;struct line_struct {

char *line, id[10], ip[6][10];int im; /* max input lead */char valid;int level;LineType *next; };

LineType *Head, *Tail; /* Head and Tail of */

typedef struct IDNode IDnode;struct IDNode {

char *id;IDnode *next; };

IDnode *I[10000];


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main(argc, argv) int argc; char *argv[];{ FILE *tdlf; char firstname_tdl[20], str[100],s[30],*tok,*temp, ok, Y, F; LineType *t,*p,*q; int i; if(argc != 2) {printf("Usage: tdlr file<.tdl>\n"); exit(0);} strcpy(firstname_tdl,argv[1]); strcat(firstname_tdl,".tdl"); if((tdlf=fopen(firstname_tdl,"r"))==NULL) { printf("Open file error!\n"); exit(1);} do{ fgets(str,100,tdlf);

printf("%s",str); sscanf(str,"%s ",s); }while( strcmp(s,"MODULE") ); do{ fgets(str,100,tdlf);

printf("%s",str); tok=strtok(str,",;: "); }while(strcmp(tok,"INPUTS"));


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fgets(str,100,tdlf);printf("%s",str);

tok=strtok(str,",;: "); Head=Tail=NULL;

while(strcmp(tok,"OUTPUTS")){t=CALLOC(1,LineType);t->im=0;t->valid=1;t->level=0;t->next=NULL;strcpy(t->id,tok);if(Head==NULL) Head=Tail=t;else {Tail->next=t; Tail=t;}fgets(str,100,tdlf);

printf("%s",str);tok=strtok(str,",;: ");

}


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fgets(str,100,tdlf); printf("%s",str); tok=strtok(str,",;: "); while(strcmp(tok,"DESCRIPTION")){

fgets(str,100,tdlf);printf("%s",str);tok=strtok(str,",;: ");

}

do{fgets(str,100,tdlf);printf("%s",str);tok=strtok(str,",;: ");

}while(strcmp(tok,"DEFINE"));

fgets(str,100,tdlf); temp=((char *)calloc(1,strlen(str)+1)); strcpy(temp,str); tok=strtok(str,"(=: ");


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while(strcmp(tok,"END")){t=CALLOC(1,LineType);t->next=NULL;t->im=t->valid=t->level=0;t->line=temp;tok=strtok(NULL,"=)");tok=strtok(NULL,"=)");strcpy(t->id,tok);tok=strtok(NULL,"(");tok=strtok(NULL,",); ");while(tok!=NULL) {

if(tok[0]==')'||tok[0]==';'||tok[0]=='\n') break;strcpy(t->ip[t->im++],tok);tok=strtok(NULL,",); ");

}Tail->next=t;Tail=Tail->next;fgets(str,100,tdlf);temp=((char *)calloc(1,strlen(str)+1));strcpy(temp,str);tok=strtok(str,"(=: ");

}}


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Bonus Project 2

1. Be familiar with a test tool in this laboratory environment, say, SynTest, Mentor or Synopsys, e.t.c.

2. Try at least 3 instances in ISCAS89 benchmark, do the full-scan test syntheses and obtain the test patterns and report the associated parameters (i.e., fault coverage, test efficiency and approximated area overhead.)


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Syllabus & Chapter PrecedenceIntroduction

Modeling

Logic Simulation Fault Modeling

Fault Simulation

Testing for Single Stuck Faults

Test Compression

Built-In Self-Test

Design for Testability

(II)


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Testing for Single Stuck Faults

1. Test Generation: Random vs. Diterministic2. ATPG for SSFs in Combinational Circuits3. ATPG for SSFs in Sequential Circuits


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Test Generation: Random vs. Deterministic

Test Selection

Fault Simulation

Fault Dropping

TE enough?

Done

No

Fault Selection

Test Generation

Fault Simulation

Fault Dropping

TE enough?

Done

No


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Test Generation: Random vs. Deterministic

#patterns

Test Efficiency

0 Test set generation time

Expected time per pattern

0


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5-Value Operations

v/vf

0/0 0 0

1/1 1 0

1/0 D ↓

0/1 D ↑

Notations AND

0

1

D

D

X

0

0

0

0

0

0

0

1

D

D

X

1 D D X

0 0 00 0

D

D

X X X

0 D X

X

XD

0

OR

0

1

D

D

X

0

D

X

1

1

D

1

1 D D X

D

X X X

D X

X1

1 11 11

0 1 D D X

1 1


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Test Generation for Fanout-Free Tree1. Set all values to X

X

X

X

X

X

X

X

X

X

X

X

X

2. Justify(l, ~v)

X

X

3. Propagate(l, v/vf )

Justify for Enabling


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State 2

Decision Process in Justification

State 1

1

1 1 1


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Decision Process in Justification

0

000 001 010 011 100 101 110

State 1

Branches of Decision Tree


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Sub-Process

Backtracking in Decision Tree

A

B CB C

Conflictor

Contradiction

In typical circuits, test generation for some faults usually have more than thousands of backtracking


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Test Generation for Fanout-Free Tree1. Set all values to X

X

X

X

X

X

X

X

X

X

X

X

X

2. Justify(l, ~v)

X

X

3. Propagate(l, v/vf )

Justify for Enabling

Possible Backtracking with Fanout

If Conflict?

Backtracking


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Concept of Frontiers

J-Frontier D-Frontier

D-frontier: all gates with any D or \D on their inputs – a queue waiting for propagation.

J-frontier: all gates keeping track of unsolved


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Basic Test Generation AlgorithmTG(){

if( imply_and_check( ) ) {if ( error_at_PO and all_lines_justified ) return(1)

;if ( no error can be propagated to a PO) return(0

);select an unsolved problem;for (all ways) {

select a untried way to solve it;if (TG( ) ) return (1);

}}else return(0);

}


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Implication Process

Purposes1. Compute all values that can be uniquely determined by

implication.2. Check for consistency and assign values.3. Maintain the D-frontier and the J-frontier.

Operations1. Imply_and_check() retrieves in tern every entry in the assign

ment queue (like the time wheel in logic simulation).


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Backward Implication

1xx11

0x101

0xx

g

J-frontier ← J-frontier U {g}

1x x

x

1 1

1


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Forward Implication: Binary Values

x

0 x0

1

1 x1

x

0 0

J-frontier ← J-frontier \ {g}

gx

1 0

J-frontier ← J-frontier \ {g}

g0

E

1 xEg

D-frontier ← D-frontier \ {g}

E

0 x0g


},{ DDE


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Forward Implication: Error Values

x

E xg

D-frontier ← D-frontier U {g}

1

E xEg

},{ DDE

E

E xEg


E x0g


E

frontierD g if

x

E xg

D-frontier ← { }

}{ if gfrontierD

1

E

Unique Drive


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D-AlgorithmRoth 1966

D_Algo(){

if imply_and_check()if(error not at PO){

repeat{select(g, D_frontier);enabling(g);if(D_algo()) return(SUCCESS

);} until(all gates tried)return(FAILURE);

}if(J_frontier)

repeat{select(g, J_frontier);select(input, g);select(input j, g);controlling(j, g);if(D_algo()) return(SUCCESS);enabling(j, g);

} until(all gates tried);else return(SUCCESS);return(FAILURE);

}

Characteristic feature:Multiple-path sensitization,ability to propagateerrors on several reconvergent paths.


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Variety of PG Algorithms

#values

5V

9V

#Paths

Single (PODEM)

Multiple (D-algo)

Sensitization or Desensitization ?

Speeding Skills

Dynamic/static learning


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Example for D-AlgorithmSchneider’s Circuit, 1967

dd’

h

i

ee’

j

k

ff’

l

m

b

c

a

n

g

0

1

1

D-frontier:________________J-frontier:________________ g

1

1

0

i k m n

1

1

1

1

01

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