introduction to embedded systems research: from idea to...

Introduction to Embedded Systems Research:From Idea to Publication and/or Company and Specification

Robert Dick

[email protected] of Electrical Engineering and Computer Science

University of Michigan

Fovea

Lens

Cornea

Variable Resolution

and Position Sampling

Change-Adaptive

Signalling

Spatial State

Cache

(Occipital

Place Area)

Analasys, e.g.,

Classification

Adequate

decision confidence?

Sampling Guidance

Y

N

Long-Term Memory

Decision /

Result

(b) Iterative, multi-round human vision system.

Image Signal

Processor

Application Processor

(CPU and/or GPU)

CloudDecision /

Result

(a) Conventional machine vision pipeline.

Image Sensor: typically

homogeneous RGGB or RCCC.

Demosaicing, binning,

denoising, gamma

correction, and compression.

Hardware Feature

Extraction Accelerator

or

Feature extraction on

raw captured data.

Runs CNN, LSTM or

other analysis algorithm.

May drop computation on less

important data, but already payed

Image Signal Processor transfer cost.

May render decision or (at high

energy cost) do feature extraction

and defer decision to cloud.

Minimalistic

Image Pre-Processor

Application Processor

(CPU and/or GPU)

CloudDecision /

Result

Image Sensor: capture only the

most important

data for decision accuracy.

Efficient gamma

correction

and binning.

Decide based on features.

Very high energy cost for

wireless data transfer.

Scene Cache

Capture ControllerHardware Feature

Extraction Accelerator

or

Adequate

decision confidence?

or

Y

N

Captures most relevant

and rapidly changing data.

Learns important sample locations

from prior rounds.

Maintains state built from

prior still-relevant samples.

Determine and

transmit

relevant data.

Decide based on features.

Very high energy cost for

wireless data transfer.

Issue commands to

capture important data.

(c) Goal: multi-round, energy-efficient, low-latency

continuous learning machine vision.

Feature extraction on sparse captured

data with similar distribution to processed data.

Continuously learn features and important

data based on prior captures.

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2

3

4

5

6

7

8

0 1 2 3 4 5 6 7 8

Pow

er

(mW

)

Time (s)

35 40 45 50 55 60 65 70 75 80 85 90

-8 -6 -4 -2 0 2 4 6 8

-8

-6

-4

-2

0

2

4

6

8

35 40 45 50 55 60 65 70 75 80 85 90

Temperature (°C)

Position (mm)

Temperature (°C)

Topical overviewReading and writing research papers

SpecificationDeadlines

Outline

1. Topical overview

2. Reading and writing research papers

3. Specification

4. Deadlines

2 R. Dick EECS 507

Breadth I

Reading and writing research papers.

Costs, constraints, and optimization.

Specification languages and models. Allocation, assignment, and scheduling.

The role of the memory hierarchy in embedded systems.

Embedded (real-time) operating systems.

Sensors and actuators.

Cyberphysical systems.

Low power sensing (guest lecture)

Energy- and temperature-aware design and embedded power supplies.

Wireless communication and its impact on power consumption.

Breadth II

Reliability-aware design and formal methods.

Testing.

Security.

Applications: smartphones.

Applications: wireless sensor networks.

Applications: wearables.

Applications: autonomous vehicles.

Applications: vision.

Depth I

The IoT problem.

Overview of machine learning in the IoT.

Efficient embedded machine learning algorithms in the IoT.

Devices and circuits for machine learning.

IoT reliability.

LPWAN communication.

IoT security and privacy.

Vision in the IoT.

Data compression in the context of energy efficiency and machine learning.



Outline

1. Topical overview


3. Specification

4. Deadlines

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Finding research papers

Google Scholar, considering publication date and citations.

Recommendations by researchers in the area.

Top conferences and journals in the area.

Find surveys and follow the citations.

Find great papers and follow citations in reverse order.

In some cases, consider patents.

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Embedded systems conferences and journals I

Embedded Systems Week conferences.

Cyber-Physical Systems Week conferences.

Design Automation Conference.

Design, Automation, and Test in Europe Conference.

International Conference on Architectural Support for ProgrammingLanguages and Operating Systems.

Conference on Embedded Networked Sensor Systems.

IEEE Transactions on Mobile Computing.

IEEE Transactions on Very Large Scale Integration Systems.

8 R. Dick EECS 507

https://esweek.org

https://www.cister.isep.ipp.pt/cpsweek2018/

https://dac.com

https://www.date-conference.com/

https://asplos-conference.org/

https://asplos-conference.org/

http://sensys.acm.org/2019/index.html

https://www.computer.org/web/tmc

http://tvlsi.egr.duke.edu/index.html



Embedded systems conferences and journals II

IEEE Transactions on Computer-Aided Design of Integrated Circuits andSystems.

IEEE Design and Test of Computers.

ACM Transactions on Embedded Computing Systems.

Not exhaustive.

9 R. Dick EECS 507

http://tcad.polito.it/

http://tcad.polito.it/

http://ieee-cas.org/publications/design-test-magazine

https://tecs.acm.org/



Reading research papers

Read in detail. If you must skim once, reread in detail.

When you encounter a concept you aren’t yet aware of, note it and move on.

If the paper starts to become incomprehensible, return to missing conceptsand follow citations or search for definitions.

This is hard and slow; it speeds up when you better understand a field.

Check equations and algorithms carefully; most people miss them.

Read experimental setup carefully and skeptically.

Interpret results with an open mind, ignoring the authors’ claims.

Study the ideas that remained unclear at the end of the paper.

Search for the most interesting and important ideas and findings; don’tcopy-paste the abstract.

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From idea to publication

While not novel

Develop idea.

Do literature survey to find best closely related work.

Develop method of evaluating idea. Abandon if it cannot be evaluated.

While not highly rigorous

Evaluate with increasing detail, comparing with best closely related work.

Write the abstract and claims. Abandon if not important.

Identify appropriate conference or journal.

Ask experts in the area.

See where excellent related papers were published.

Consider impact factors and acceptance rates.

See whether similar ideas were published there recently.

Write paper.



Anticipatory writing

Know your audience.

Don’t waste their time.

Don’t spin.

Make novelty clear.

Give credit when it is due.

Be careful, but blunt when comparing.

More novel ideas are harder to publish. . .

. . . but they are eventually heavily cited and win awards.

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Understanding the reviewer

Off record.

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From idea to company

Develop an idea that many people value deeply.

How? Talk to the potential customers first.

Start with the potential customers.

When you prototype, start with quick, low-resolution version.

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How you see your idea

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How your customers see your idea

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How your customers see you

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That’s a great idea!

What they say: That’s a great idea.

What they mean: I don’t want to hurt your feelings you cute widdle engineer.

I would definitely use that!

There are almost no circumstances in which I would use that, let aloneconsider paying for or supporting it.

I have some ideas on how to make it better!

I’m pretending to be someone who would use it and leading you down a falsepath.

Follow your dreams, dude!

Squander your life, dude!

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How to learn more

Talking to Humans by Giff Constable.

The Startup Owner’s Manual by Steve Blank and Bob Dorf.

Market Research on a Shoestring by Naeem Zafar.

Steve Blank’s online videos (steveblank.com).

Contact me for more.

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What you need to learn

How to design, sequence, and deliver questions to minimize bias, both yoursand theirs.

How to talk with strangers.

This is highly unnatural, all the more so for most engineers.

Most must learn it.

You can learn it well enough to do a good job, even if it makes youuncomfortable.

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Other topics

Business plans.

Self funding.

Crowdfunding.

Angel investors.

VCs.

Production.

Marketing.

Sales and distribution.

Customer support.

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Paper discussion mechanics

Papers all posted to website.

Everybody reads them and writes 0.5–1 page summaries (see template)covering the most important points.

Everybody critiques the summaries of other randomly assigned people.

A randomly assigned team presents each paper (slides and 20–30 minutepresentation).

You can swap papers with others based on interest and background.

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https://robertdick.org/iesr/

https://robertdick.org/iesr/refs/review-template.pdf



Software oriented design representationsHardware oriented design representationsGraph based design representationsResource descriptions

Outline

1. Topical overview


3. Specification

4. Deadlines

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Why learn about specification languages

Understand different ways of describing design to other people.

Find most appropriate language for your application.

Use for synthesis.

Use for model checking.

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Available resources – system-level

General-purpose SW processors

Digital signal processors (DSPs)

Application-specific integrated circuits

Dynamically reconfigurable hardware

E.g., field-programmable gate arrays (FPGAs)

Busses

Wireless communication channels

Wires

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Available resources – high-level

Simple arithmetic/logic units.

Multiplexers.

Registers.

Wires.

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Specification language requirements

Describe hardware (HW) and software (SW) requirements.

Specify constraints on design.

Indicate system-level building blocks.

To allow flexibility in synthesis, must be abstract.

Differentiate HW from SW only when necessary.

Concentrate on requirements, not implementation.

Make few assumptions about platform.

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Section outline

3. SpecificationSoftware oriented design representationsHardware oriented design representationsGraph based design representationsResource descriptions

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Software oriented design representations

ANSI-C.

SystemC.

Other SW language-based.

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ANSI-C

Advantages.

Huge code base.

Many experienced programmers.

Efficient means of SW implementation.

Good compilers for many SW processors.

Disadvantages.

Little implementation flexibility.

Strongly SW oriented.Makes many assumptions about platform.

Poor support for fine-scale HW synchronization.

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SystemC.

Advantages.

Support from big players.

Synopsys, Cadence, ARM, Red Hat, Ericsson, Fujitsu, InfineonTechnologies AG, Sony Corp., STMicroelectronics, and TexasInstruments.

Familiar for SW engineers.

Disadvantages.

Extension of SW language.

Not designed for HW from the start.

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Many SW language-based

Numerous competitors.

ANSI-C, C++, and Java are most popular starting points.

In the end, few can be widely used.

SystemC has broad support.

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Section outline


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Hardware oriented design representations

VHDL.

Verilog.

Esterel.

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VHDL

Advantages.

Supports abstract data types.

System-level modeling supported.

Better support for test harness design.

Disadvantages.

Requires extensions to easily operate at the gate-level

Difficult to learn

Slow to code

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Verilog

Advantages.

Easy to learn.

Easy for small designs.

Disadvantages.

Not designed to handle large designs.

Not designed for system-level.

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Verilog vs. VHDL

March 1995, Synopsys Users Group meeting.

Create a gate netlist for the fastest fully synchronous loadable 9-bitincrement-by-3 decrement-by-5 up/down counter that generated even parity,carry and borrow.

5 / 9 Verilog users completed.

0 / 5 VHDL users competed.

Does this mean that Verilog is better? Maybe, but maybe it only means that

Verilog is easier to use for simple designs.

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Esterel

Easily allows synchronization among parallel tasks.

Works above RTL.

Doesn’t require explicit enumeration of all states and transitions.

Recently extended for specifying datapaths and flexible clocking schemes.

Amenable to theorem proving.

Translation to RTL or C possible.

Commercialized by Esterel Technologies.

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Section outline


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Graph based design representations

Dataflow graph (DFG).

Synchronous dataflow graph (SDFG).

Control flow graph (CFG).

Control dataflow graph (CDFG).

Finite state machine (FSM).

Petri net.

Periodic vs. aperiodic.

Real-time vs. best effort.

Discrete vs. continuous timing.

Example from research.




Dataflow graph (DFG)

NEG

IOP

FIL

FT

DCT

3 kb

4 kb 4 kb

6 kb

3 kb

Soft DL = 230 ms

Soft DL = 150 ms

5 kbNEG

IOP

FIL

FT

DCT

3 kb

4 kb 4 kb

6 kb

3 kb

Soft DL = 230 ms

Soft DL = 150 ms

Nodes are tasks.

Edges are data dependencies.

Edges have communication quantities.

Used for digital signal processing(DSP).

Often acyclic when real-time.

Can be cyclic when best-effort.

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Synchronous dataflow graph (SDFG)

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Control flow graph (CFG)

false

false true

trueif i < 2

if k = 3

240 Kb

30 Kb

387 Kb

27 Kb

j = j + 5

k = k − 1

Nodes are tasks.

Supports conditionals, loops.

No communication quantities.

SW background.

Often cyclic.

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Control dataflow graph (CDFG)

≤ 3 msfalse

false true

trueif i < 2

if k = 3

240 Kb

30 Kb

387 Kb

27 Kb

j = j + 5

k = k − 1

Supports conditionals, loops.

Supports communication quantities.

Used by some high-level synthesisalgorithms.

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Finite state machine (FSM)

1 1 0

1

0

1 0

0

00 01

1011

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Finite state machine (FSM)

input0 1

00 10 0001 01 0010 00 0111 10 00

current next

Normally used at lower levels.

Difficult to represent independent behavior.

State explosion.

No built-in representation for data flow.

Extensions have been proposed.

Extensions represent SW, e.g., co-design finitestate machines (CFSMs).

46 R. Dick EECS 507




Petri net

Graph composed of places, transitions, and arcs.

Tokens are produced and consumed.

Useful model for asynchronous and stochastic processes.

Places can have priorities.

Not well-suited for representing dataflow systems.

Timing analysis quite difficult.

Large flat graphs difficult to understand.

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Petri net

busy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

think

busy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

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enter

service

waiting

processes

thinking

processesserve

thinkbusy

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available

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enter

service

waiting

processes

thinking

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available

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enter

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enter

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thinking

processesserve

think

M/D/3/2: Markov arrival, deterministic service delay,

From A. Zimmermann’s token game demonstration.

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Petri net

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48 R. Dick EECS 507




Periodic graphs

Some system specifications contain periodic graphs.

Can guarantee scheduling validity by scheduling to the least commonmultiple of periods.

Can also meet aperiodic specifications, however, resources will sometimes beidle.

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Periodic graphs

period = 20 msdeadline = 20 ms

3 copies


system hyperperiod = 60 ms

2 copies

time


3 copies



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time

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Aperiodic graphs

No precise periods imposed on task execution.

Useful for representing reactive systems.

Difficult to guarantee hard deadlines in such systems.

Possible if minimum inter-arrival time known.

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Periodic vs. aperiodic

Periodic applications.

Power electronics.

Transportation applications.

Engine controllers.

Brake controllers.

Many multimedia applications.

Video frame rate.

Audio sample rate.

Many digital signal processing (DSP) applications.

However, devices which react to unpredictable external stimuli haveaperiodic behavior

Many applications contain periodic and aperiodic components




Aperiodic to periodic

Can design periodic specifications that meet requirements posed by aperiodicspecifications.

Some resources will be wasted.

Example

At most one aperiodic task can arrive every 50 ms.

It must complete execution within 100 ms of its arrival time.

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Aperiodic to periodic

Can easily build a periodic representation with a deadline and period of50 ms.

Problem, requires a 50 ms execution time when 100 ms should be sufficient.

Can use overlapping graphs to allow an increase in execution time.

Parallelism required.

The main problem with representing aperiodic problems with periodicrepresentations is that the tradeoff between deadline and period must be

made at the time of synthesis.

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Real-time vs. best effort

Why make decisions about system implementation statically?

Allows easy timing analysis, hard real-time guarantees.

If a system doesn’t have hard real-time deadlines, resources can be moreefficiently used by making late, dynamic decisions.

Can combine real-time and best-effort portions within the same specification.

Reserve time slots

Take advantage of slack when tasks complete sooner than theirworst-case finish times

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Discrete vs. continuous timing

System-level: continuous.

Operations are not small integer multiples of the clock cycle.

High-level: discrete.

Operations are small integer multiples of the clock cycle.

Implications

System-level scheduling is more complicated. . .

. . . however, high-level also very difficult.

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Section outline


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Processing resource description

Often table-based.

Price, area.

For each task.

Execution time

Power consumption

Preemption cost

etc.

Similar characterization for communication resources.Wise to use process-based.

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Communication resource description

Can use bus-bridge based models for distributed systems.

Wireless models.

However, in the future, it will become increasingly important to base SOCcommunication model on process parameters.

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System-level representations summary

No single representation has been decided upon.

Software-based representations becoming more popular.

System-level representations will become more important.

This is still an active area of research.

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Notes on clustering and partitioning

Interdependence with architecture.

Heterogeneity’s impact on partitioning.

Applications to grid computing.

Dynamic partitioning.

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Some future direction

Can specification be so simple for some embedded application domains thatapplication experts who are not computer engineers easily do it?

What HCI, compiler, and synthesis support is required?

What impact will increasing use of machine learning in embedded systemshave on specification?

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Outline

1. Topical overview


3. Specification

4. Deadlines

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Homework

64 R. Dick EECS 507

Homework

Pages 1–2 by 16 January, finish by 21 January: Read S. A. Edwards, “Designand verification languages,” Columbia University, Tech. Rep., Nov. 2004 andwrite a 0.5–1 page ungraded summary.

21 January.

0.5–1 page project description with 2–5 citations.

Indicate the goal.

Describe the best closely related prior work.

Indicate what is novel about your idea or the data you will gather.

Describe the solution(s) you will consider.

Explain how the solution(s) will be evaluated.

Upload PDF before class that day.

Allows suggestions and team formation.



Announcement: Optional team formation meeting

4pm 23 January.

3316 EECS.

Also watch Piazza. Will post examples.

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introduction to embedded systems research: from idea to...

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