introduction to digitally assisted analog and rf circuit ... assist... · introduction to digitally...

2008.11.06

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Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.

Introduction to Digitally Assisted Analog and RF Circuit Design

Akira Matsuzawa

Department of Physical ElectronicsTokyo Institute of Technology

2008.11.06

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Contents

• Tradeoffs in analog: area, cost, mismatch, power consumption, and response;

Solution by DAA in DAC

• Power consumption and mismatch in analog

Solution by DAA in ADC

• Not robust and programmable in analog

Solution by DAA in RF-CMOS Tuner

DAA: Digitally Assisted Analog technology

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“Digitally Assisted Analog and RF Design”

• What is “Digitally Assisted Analog and RF Design”

To use digital technology for analog and RF circuits as much as possible to solve analog issues.

• Why digital technology is needed…?– Digital is more robust and programmable– Digital is more power efficient– Digital is cheaper and low power in scaled CMOS

• Will analog go out?– No, important forever, however needs assists by digital

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Tradeoff: Area, cost, mismatch, power dissipation, and response

The nature of analog and breakthrough by digital assistance

Example: DAC

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Cost up issue by analog parts in scaled CMOS

Cost of mixed A/D LSI will increase with technology scaling, dueto the increase of cost in non-scalable analog.

Large analog must be unacceptable.

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

0.35um 0.25um 0.18um 0.13um0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

0.35um 0.25um 0.18um 0.13um

（0.35um : 1）

Chip area Chip cost

I/OAnalog

Digital

Wafer cost increases 1.3xfor one generation

Akira Matsuzawa, “RF-SoC- Expectations and Required Conditions,”IEEE Tran. On Microwave Theory and Techniques, Vol. 50, No. 1, pp. 245-253, Jan. 2002

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Technology trend in RF CMOS LSI

Analog & RF CMOS will be replaced by Digitally assisted RF CMOS.

Wireless LAN, 802.11 a/b/g0.25um, 2.5V, 23mm2, 5GHz

Discrete-time Bluetooth0.13um, 1.5V, 2.4GHz

M. Zargari (Atheros), et al., ISSCC 2004, pp.96 K. Muhammad (TI), et al., ISSCC2004, pp.268

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Nature of analog: Mismatch and area

Mismatch of analog components is inversely proportional to squire root of area.

Thus accuracy and performance and cost in analog circuits always trade off.

AreaMismatch 1

∝

12 bit

10 bit

14 bit

12 bit

10 bit

14 bit

1

0.1

0.01

0.0010.1 1 10 100

Capacitance (pF)

Mis

mat

ch (%

)

1 10 100 1 .1030.1

1

10

100

δVT LW( )0

δVT LW( )1

δVT LW( )2

LW

LWTV ox

T ∝∆

0.4um Nch

0.13um Nch

0.13um Nch

)mV(VT∆

)m(LW 2µ

VT mismatch vs. gate size

)(

4102)(pFCC

C −×=σ

∆

Capacitor mismatch vs. capacitance

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Essential issue in analog technologyTo realize high precision circuits always increases power dissipation and area & cost and decreases frequency performance.The digital assistance can solve this essential issue of analog.

LargePower

dissipation

LargePower

dissipationLarge capacitance

Expensivecost

Expensivecost

Highprecisioncircuits

Highprecisioncircuits

SmallmismatchSmall

mismatchLarge

Gate sizeLarge

Gate size

Large area

Lowcutoff

frequency

Lowcutoff

frequency

Large capacitance

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Pioneer work in digital assistanceConventionally large area is required to realize high precision DAC, such 14 bit.However this results in increase of power and degrade frequency characteristics.

INL DNL

Iowa university demonstrated extremely small area and power can be realizedby digital calibration.

+/- 9 LSB

+/- 0.4 LSB

+/- 5 LSB

+/- 0.35 LSB

Before

After

14b 100MS/s DAC 1.5V, 17mW, 0.1mm2, 0.13umSFDR=82dB at 0.9MHz, 62dB at 42.5MHz

Area: 1/50 Pd: 1/20

Y. Cong and R. L. Geiger, Iowa state university, ISSCC 2003 14bit DAC

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Architecture of digitally compensated DAC

External ADC measure the nonlinearity and CAL DAC compensates it.

An idea is excellent, but the implementation (needs ADC) is not smart.

14bit 100MHz DAC

External ADC

Compensation circuitsY. Cong and R. L. Geiger, Iowa state university, ISSCC 2003

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Our developed 14b DAC without ADC

We developed 14b digitally calibrated DAC without ADC for error measurement.

Good SFDR of 83dB has been attained in spite of bare SFDR is 69 dB.

Yusuke Ikeda, Matthias Frey, and Akira Matsuzawa A-SSCC, 13-3, pp 356-359, Korea, Jeju, Nov, 2007.

0 5000 10000 15000-0.5

-0.4

-0.3

-0.2

-0.1

0

0.1

0.2

0.3

code

INL(

LSB

)

0 5000 10000 15000-8

-6

-4

-2

0

2

4

6

8

code

INL(

LSB

)

0 5000 10000 15000-4

-2

0

2

4

6

8

code

DN

L(LS

B)

0 5000 10000 15000-0.4

-0.3

-0.2

-0.1

0

0.1

0.2

0.3

code

DN

L(LS

B)

Before Calibration After Calibration

0

4

8

-4

-8

0

4

8

-4

-8

0

0.2

-0.2

-0.4

0

0.2

-0.2

-0.4

0 5000 10000 15000

0 5000 10000 15000 0 5000 10000 15000

0 5000 10000 15000IN

L (L

SB)

DN

L (L

SB

)

0 5000 10000 15000-0.5

-0.4

-0.3

-0.2

-0.1

0

0.1

0.2

0.3

code

INL(

LSB

)

0 5000 10000 15000-8

-6

-4

-2

0

2

4

6

8

code

INL(

LSB

)

0 5000 10000 15000-4

-2

0

2

4

6

8

code

DN

L(LS

B)

0 5000 10000 15000-0.4

-0.3

-0.2

-0.1

0

0.1

0.2

0.3

code

DN

L(LS

B)

Before Calibration After Calibration

0

4

8

-4

-8

0

4

8

-4

-8

0

0.2

-0.2

-0.4

0

0.2

-0.2

-0.4

0 5000 10000 15000

0 5000 10000 15000 0 5000 10000 15000

0 5000 10000 15000IN

L (L

SB)

DN

L (L

SB

)

INL>6LSB INL<0.5LSB

DNL>6LSB DNL>0.3LSB

14 dB UP

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Method for compensation

Only comparator and cal DAC are required to extract linearity error.Nature of binary weighted values

im

i

nnmm +

=+ += ∑ 2

12

121

188765 2

121

21

21

21

+++=

The error can be extracted by comparing two values and balanced with CAL DAC

RL

Vout

Main DAC

Cal DAC

2oI

±4oI

± 12 −± NoI

NoI

2± 12 +−± jN

oIijN

oI+−±

222 +−± jNoI

ijNoI+−±

2

Comparator

Logic

Data in

5887655 21

21

21

21

21 δδ =⎟

⎠⎞

⎜⎝⎛ +++−⎟

⎠⎞

⎜⎝⎛ +

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Calibration pass and chip photograph

Extracted errors is stored in registers and used for compensation digitally.

Yusuke Ikeda, Matthias Frey, and Akira Matsuzawa A-SSCC, 13-3, pp 356-359, Korea, Jeju, Nov, 2007.

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OPamp-base design to comparator-base design

Conventional analog circuits consume static current

Low power dissipation by digital assistance

Example: ADC

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Issues of pipeline ADCsMajor issues of pipeline ADCs are caused by OpAmp. High OPamp gain is required for high precision ADC,however it becomes quite difficult with technology scaling.

dBbdBb

NdBGDC

82:1270:10

106)( +>

in+vout-vout+

2Veff

Vdd-4V

2Veff

Vin-

Vdd

Vin+vout-vout+

2Veff

Vdd-4V

2Veff

Vin-

Vdd

CL

Vsig_max

ndBVVG

nn

eff

ADC ×≈⎟

⎠⎞

⎜⎝⎛≈⎟

⎟⎠

⎞⎜⎜⎝

⎛≈ 16

15.01

Sub-100nm CMOS

dBGn

DC 805<

<

0

1

2

3

4

5

6

7

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7

Vds[V]

VA[V]

90m 0.13μ 0.18μ 0.25μ 0.35μ

eff

A

ds

m

ds

dsA

VV2

ggG

gIV

==

≈ 350nm

180nm250nm

130nm

90nm

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Conversion speed of pipeline ADCSpeed of pipeline ADC is proportional to the OPamp current basically.

⎟⎟⎠

⎞⎜⎜⎝

⎛++⎟⎟

⎠

⎞⎜⎜⎝

⎛+⎟⎟

⎠

⎞⎜⎜⎝

⎛+

=

⎟⎟⎠

⎞⎜⎜⎝

⎛++⎟⎟

⎠

⎞⎜⎜⎝

⎛+⎟⎟

⎠

⎞⎜⎜⎝

⎛+

=⋅

=

o

dspi

o

dspo

o

dspieffo

ds

o

pi

o

po

o

pio

m

L

mclose

CI

CI

CIVC

ICC

CC

CCC

gC

gGBW

ααα

β

112

1

112

122_

π

ππ

eff

dsm V

I2g =

dspopodspipi I�C,IC αα ==

αpi,αpo are design rule dependent

100

1000

0.1 1.0 10.0

Ids[mA]

GBW_close[MHz]

・0.18μmプロセス・PMOS入力・N=10bit・Vsig=0.5V・CO=0.7pF

Cf

Cs Cpi gm Cpo COLRL2

1

1

p

sω

+

Performance model

vovi

o

i

vvfactorFeedback =）（β

CL

A. Matsuzawa, “Analog IC Technologies for Future Wireless Systems,” IEICE, Tan on Electronics, Vol. E89-C, No.4, pp. 446-454, April, 2006.

)()(3 _

dsL

dsdsclosec IC

IIN

GBWf β

∝≈

Con

vers

ion

spee

d

Current

dsc If ∝

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Mega-technology trend in ADCsA major conversion scheme of ADCs is now changing from pipeline to SA

Pipeline ADC

2C

4C

8C

16C

16CC

CMPDAC

-

-+

+

Op amp

CMPDAC

-

-+

+

Op amp

1st stage 2nd stage

Sample Amplify

Cf

Cs

Cf

Cs

1st stage 2nd stage

Opamp-base design

Comparator-base design

Opamp determines performance

Comparator determines performance

Static current flows

No static current flows

SA ADC

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SA ADCSpeed of SA ADC is determined by speed of switches, comparators, and logics.Basically independent of static current.

Vin

Vref

Comparator Logics

Switches

Capacitor

bcT

( ) bcc

c TNf

T 21+≈=

digcmpsetbc TTTT ++= timedelayLogicTtimedecisionComparatorT

timesettlingSwitchTtimecycleBitT

dig

cmp

set

bc

:

:::

( ) bcd ENfP 2+≈

convEnergyEb /:

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Performance overview of SA ADCsSA ADCs become dominant in every performance range.In particular FoM has rapidly lowered.

ENOBc

d

fPFoM2×

=FoM: 1/200 during past three years.

FoM

0.1

1

10

100

1000

2005 2006 2007 2008 2009 2010Year

FoM

[fJ/c

onv.

step

]

SAR ADC Power vs Sampling Freq.

0.001

0.01

0.1

1

10

100

1000

10000

0.1 1 10 100 1000 10000 100000

Sampling Freq.[MSps]

Pow

er[m

W] 14bit

12bit10-9bit7-5bit

ISSCC2008

Courtesy Y. Kuramochi

2008.11.06

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Progress of CMOS ComparatorSmall size MOS can be used for small mismatch circuits owing to analog compensation, however static current flows.

Yukawa, et al., JSC, 1986.

1 10 100 1 .1030.1

1

10

100

δVT LW( )0

δVT LW( )1

δVT LW( )2

LW

LWTV ox

T ∝∆

0.4um Nch

0.13um Nch

0.13um Nch

)mV(VT∆

)m(LW 2µ

Vsig

Vref

Vg

CS1 S2

Vout

Dingwall, RCA, 1979

Trade offSmall areaLow powerHigh speed

Small mismatch

Chopper comparator solved this problem

Mismatch vs. gate size

Chopper comparator Staticcurrent

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Recent dynamic comparatorsDynamic comparator can cut of the static current,however analog compensation is difficult to use.

GND

VDD

OUTpOUTn

INp INn

Comp

CLK

CLK CLK

CLK

INP

SPSN

INNFN FP

1 20

FNFP

SN

SP

V

0

b

V

0

b

V. Giannini, P. Nuzzo, V. Chironi, A. Baschirotto, G. van der Plas, and J. Craninckx, “An 820uW 9b 40MS/s Noise Tolerant Dynamic-SAR ADC in 90nm Digital CMOS,”IEEE ISSCC 2008, Dig. of Tech. Papers, pp.238-239, Feb. 2008.

Dynamic comparators use the fast voltage fall depended on input voltage difference

Fast voltage fall

FoM can be reduced

M. van Elzakker, Ed van Tujil, P. Geraedts, D. Schinkel, E. Klumperink, B.Nauta, “A 1.9uW 4.4fJ/Conversion-step 10b 1MS/s Charge-Redistribution ADC,” IEEE ISSCC 2008, Dig. of Tech. Papers, pp.244-245, Feb. 2008.

2008.11.06

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Mismatch compensation for dynamic comparator

We developed mismatch compensation technique for dynamic comparatorby using charge pump circuit.

Feedback loop become stable when mismatch reaches zero.

M. Miyahara, Y. Asada, D. paik, and A. MatsuzawaA-SSCC 2008

2008.11.06

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Effect of digital mismatch compensation

mV7.13)( =σoffsetV

mV69.1)( =σoffsetV

M. Miyahara, Y. Asada, D. paik, and A. MatsuzawaA-SSCC 2008

Mismatch voltage successfully reduced from 13.7 mV to 1.69mV @sigma

2008.11.06

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Small sized SA ADC One issue of current SAR is not small occupied area.This is due to large capacitance ratio; CMSB/CLSB=2N

Serial capacitors can reduce this ratio, however parasitic capacitors degrade accuracy. We solved it by calibration.

COMPOUT

VCM

VINN

VREFPVREFN

VINP

VREFNVREFP

Calibration ControlSystem

Yasuhide Kuramochi, Akira Matsuzawa, and Masayuki Kawabata "A 0.05-mm2 110-uW 10-b Self-Calibrating Successive Approximation ADC Core in 0.18-um CMOS" A-SSCC, 8-1, pp 224-227, Korea, Jeju, Nov, 2007.

Voffset

VCM

CCAL

Ck Ck_err

C(k+1~N)

VREFP

VREFN

Ck-1C1Cdum

SAR

Cm+Cdum=Ckk-1

m=1

Calibration DAC

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Effect of digital calibrationWe can realize 10b ADC with high SFDR of 72dB ADC in world smallest chip size,by using digital calibration technique.

[1] J. Craninckx, et. al. ISSCC 2007[2] Y. Jeon, et. al., ISSCC 2007

12Bit11Bit10Bit9BitFo

M [J

/con

v. s

tep]

100f

0.01 0.1 1 10

1p

10p

10f

Area [mm2]

This work (0.18µm)

Good

This work(Estimationwith Digital)

[1] (90nm)

[2] (90nm)[2] (90nm)

*MSps ADC

Input frequency [Hz]1k 10k 100k 1M

SFD

R [d

B]

40

60

80

Calibration Off

Calibration On23.3dB

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Analog vs. DigitalDigital (ON, OFF) control can realize lossless conversion.

Analog regulationRreg

Vref

VoVi

OPampRL

Comp+LogicVref

RL

Vi SW1

SW2

VoL

C

Digital regulation

Clean voltage, but low efficiency

Noisy, but high efficiency

DC/DC converterPolar modulator

Ideally efficiency of 100% can be realized

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ΔΣ modulation

Delta-Sigma modulation method can generate average value without low frequency noise and large super tones. High frequency noise can be suppressed by filter.

Pulse width control Issues: Large Super tones (Fixed frequency spectrums)

103

104

105

106

107

-200

-180

-160

-140

-120

-100

-80

-60

-40

-20

0

1st order

20dB/dec

2nd order

40dB/dec

dBFS

Frequency (Hz)

fs=26MHz

103

104

105

106

107

-200

-180

-160

-140

-120

-100

-80

-60

-40

-20

0

1st order

20dB/dec

2nd order

40dB/dec

dBFS

Frequency (Hz)

fs=26MHz

( ) )z(Qz1)z(X)z(YL1−−+=

TonToff cycle

onio T

TVV =

offoncycle TTT +=

X YQuantizer

Z-1

Z-1

Nfcy

+

-

(1, 0, 0, 0, 1, 0, 0, 1, 1,…)

ΔΣ modulator

Noise spectrum

Lowe frequency noise is suppressed

==cycle

cy Tf 1

Output

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From analog centric RF to digitally assisted RF

Digital is more stable, robust, and programmable

Example: Tuner

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Technology trend in RF-CMOS LSI

Analog & RF CMOS will be replaced by digitally assisted analog &RF CMOS. High performance, low cost, stable and robust circuits, no or less external components, no adjustment points, and high testability are the keys. DSP and ADC will play important roles.

Analog & RFCMOS

Digitally Assisted Analog & RF CMOS

Signal processing Analog circuitsAnalog processing+External component

DSP+ADC+ Small and robust analog ckts.

Adjustment External Digital on chip, no external

No or lessExternal components Large #

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For example: AM/ FM tuner

Current AM/FM tuner uses 3 ICs and large # of external components.Furthermore 12 adjustment points are needed.Large # of products, but not expensive product.More efforts to reduce the cost are still required. Courtesy Niigata Seimitsu

Bipolar IC = 1 (RF)CMOS IC = 2 (PLL, RDS)External Components=187

12 adjustment pointsAM/FM Tuner for home use

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Analog-centric vs. digitally assisted

Digitally assisted RF-CMOS tuner can provide user merits.Very small # of external components and no adjustment points.

Digitally assisted Analog & RF CMOS technologyAnalog & RF CMOS technology

External components 187 69 # of external components are 11 No adjustment pointsCourtesy Niigata Seimitsu

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Analog-centric RF CMOS tuner

1st trial to realize AM/FM tuner by analog-centric RFCMOS technologyCourtesy Niigata Seimitsu

FMLNA

FMMIX

FM IFBPF

LIMITER FMDEMOD

STEREODECODER

LOCALOSC(AM)

LOCALOSC(FM)

AMLNA

AMMIX

AM IFBPF

AM IFA AMDEMOD

SERIALINTERFACE

FREQUENCYSYNTHESIZER

RDSDECODER

SW LEFT

RIGHT

AM Bar Antenna and Varactor

FM inter-stageTunig L and varactor

＋

-VCC

AGC smoothingCapacitor

RSSILevel

XtalElementfor

Synthe.

FMDemod

FM IFT andCeramic filters

AM IFT andCeramic filter

De-couplingCapacitors

Ceramic resonatorfor Stereo decoderand LPF for PLL

FM AntennaTunig L and varactor

LO inductorand Varactor

LPF for Synthesizer

De-couplingCaps for amplifier

Can be integrated on a chip

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Analog-centric CMOS tuner technology

1st trial used analog-centric CMOS tuner technology.

External circuits have been replaced by CMOS, however still use analog.Thus it had many issues and many external components were still needed.

Parts Methods for on-chip Problems

AGC smoother Time division charge and discharge Needs large capacitor for low audio frequency

AM/FM IF BPF 1. Low IF( a few hundred KHz)2.Gm-C BPF with auto alignment, SCF

1.poor selectivity(-45dB), 2. SCF Switch noise 3. Center frequency shift by DC offset4. Poor image rejection ratio (25 to 35dB)

FM Demodulator Pulse count FM detector Poor THD (0.5%)Stereo Decoder Multi-vibrator VCO, SCF filter Large variation of free-run frequency

Still need external LPF for PLLRSSI Level adj. Signal detector with DC

compensationCan’t cover all process corner

Varactor MOS varactor Too much sharp C-V curve, distorted signal

Capacitors Stages Direct connection, use small value coupling capacitor

High impedance required, Difficult for low frequency

Courtesy Niigata Seimitsu

2008.11.06

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Digitally assisted CMOS tuner

FMLNA

＋

-

FMMIX

Anti-AliasLPF

VGA ADC DAC

LOCALOSC(FM)

FREQUENCYSYNTHESIZER

AMLNA

SERIALINTERFACE

REGISTER

Cap.Array

AM Bar Antenna(No need for Car radio)

AGC

AGC

AGC

AGC

FM Tuneor BPF

Xtal

XOSC

SYSCLKGEN

PowerDecouplingCap

VCC

DSP

STEREODECODER

FMIFBPF

FMDEMOD

RDSDEC

DECI.LPF

AGC GENERATOR

AMMIX

AMIFBPF

AMDEMOD

DIGITALAM LO

To/FromMPU

LEFT

RIGHTCap.Array

Digitally assisted CMOS tuner has been developed.

DSP realizes Sensitivity: FM: 9dBuV, AM: 16dBuVSelectivity: FM/AM >65dBSNR: FM: 63dB, AM: 53dBStereo sep: 55dBImage ratio: FM: 65dB, AM: InfinityDistortion: FM: 0.09%, AM=0.25%

Performance


1. AM/FM demodulations2. Stereo decoder3. AM mixer4. Channel select filter5. Support for image reject6. Watch the signal revel and control gain of each stage7. Parameter control and adjustment with MCU

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Image rejection in low IF receiver

Desired Image

( )tLOωcos

LPF

+

LPF

Vin (t) Vout(t)( )tLOωsin

°90

LOω ωimωdesω

Image rejection mixer ω

IFω IFω

0

IFω

IFω

Input

Output

V1

V2

( ) ( )

( ) ( )tVtVtV

tVtVtV

imLOim

LOdesdes

imLOim

LOdesdes

ω−ω+ω−ω=

ω−ω+ω−ω−=

cos2

cos2

)(

sin2

sin2

)(

2

1

( ) ( )

( )tVtV

tVtVtVshifttV

LOdesdesout

imLOim

LOdesdes

ω−ω=

ω−ω−ω−ω==°→

cos)(

cos2

cos2

)(90)( 31

Image signal can be rejected by using I/Q mixer and phase shift.

Image can be rejected theoretically, however,…

V3

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Required gain and phase mismatch

0.1 deg and 0.01% are needed for IRR of 60dBand very difficult to attain by analog technology.

IRR: Image rejection ratio

A. Rofougaran, et al., IEEE J.S.C. Vol.33, No.4, April 1998. PP. 515-534.

( )

4

22

θ∆+⎟⎠⎞

⎜⎝⎛ ∆

≈ GG

IRR

Conventional IRR: 35dB

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Digital image rejectionThe dummy image signal is generated by IMO and the controller controls signal delay and amplitude on Q path to minimize the I/Q imbalance.

ADCVGA+FilterMIXERLNA

FMI


Q

Deci.LPF

Vari.Delay

Vari.Gain BPF

IMO Controller

Deci.LPF

Fixed.Delay BPF

DSP

to DSP

Image Rejection Ratio >60dB

Image frequency oscillator

From ADCsIM detect

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Summary

• Analog has serious tradeoffs– area, cost, mismatch, power consumption, and response

• Analog consumes static power– OPamp-base Comparator-base

• Analog is weak in robustness and programmability

• Digital assistance can solve these analog issues and will be inevitable and reasonable with technology scaling.

• Analog and RF circuit design will make great advance assisted by digital technology.

introduction to digitally assisted analog and rf circuit ... assist... · introduction to digitally...

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