introduction to digital logic -...

© Egemen K. Çetinkaya

Introduction to Digital Logic Missouri S&T University CPE 2210

Counters/Timers

Egemen K. Çetinkaya

Department of Electrical & Computer Engineering

Missouri University of Science and Technology

[email protected]

http://web.mst.edu/~cetinkayae/teaching/CPE2210Fall2016

14 November 2016 rev. 16.0 © 2014–2016 Egemen K. Çetinkaya


Counters/Timers Outline

• Introduction

• Counters

• Timers

• Summary

MST CPE2210 – Counters/Timers 14 November 2016 2


Digital Logic Systems Overview

• Combinatorial logic circuits for no memory systems

– Boolean algebra to mathematically design/analyze

– logic gates are building blocks

• Sequential logic circuits for memory systems

– Finite State Machines to mathematically design/analyze

– flip-flops and latches store memory

• flip-flops and latches are building blocks of sequential logic

• Sequential logic circuits (aka controllers) combine

– combinatorial circuits

– storage elements (e.g. registers)



Digital Systems Components

• Transducer: sensor + actuator

• Not all sensors/actuators require A2D/D2A conversion

• Digital system can be implemented:

– microprocessor

• readily available, cheap, easy to program, easy to reprogram

– custom circuit

• smaller, faster, consume less power

14 November 2016 MST CPE2210 – Counters/Timers 4

sensors and other inputs

Digital System

actuators and other outputs

A2D

D2A

analog phenomena

electric signal

digital data

digital data

electric signal

digital data

digital data


Digital Systems Paths

• Digital systems have two paths:

– datapath circuit

– control circuit

• Datapath circuit

– store data

– manipulate data

– transfer data from one part to another

• Control circuit

– controls the operation of datapath circuit



Datapath Components Building Block examples

• Registers

• Shifters

• Counters/timers

• Multiplexer/demultiplexers

• Decoders/encoders

• Adders

• Comparators

• Subtractors

• ALUs: Arithmetic Logic Units



SR Flip-Flop Symbol and Characteristic Table

• SR flip-flop: Similar to SR latch, edge-triggered


S Q

Q R

S R 𝑸(t+1)

0 0 no change Q(t)

0 1 0

1 0 1

1 1 X


D Flip-Flop Symbol and Characteristic Table

• The output follows input on the rising edge of clock


D Q

Q

D 𝑸(t+1)

0 0

1 1


T Flip-Flop Symbol and Characteristic Table

• T flip-flop: toggle flip-flop

• The output toggles on the rising edge of clock


T Q

Q

T 𝑸(t+1)

0 Q(t)

1 Q’(t)


JK Flip-Flop Symbol and Characteristic Table

• JK flip-flop: toggle flip-flop when JK is 11


J Q

Q K

J K 𝑸(t+1)

0 0 no change Q(t)

0 1 0

1 0 1

1 1 toggle Q’(t)


Counters Overview

• Sequential component that increments or decrements

• Example: – 4-bit up-counter example: 0000, 0001, …, 1111, 0000

– 4-bit down-counter example: 1111, 1110, …, 0000, 1111

• Counter wraps around

– terminal count (tc) control output becomes 1

• in the last clock cycle before wrapping around

• once wrapped around, tc value becomes 0 again


cnt

tc C

4-bit up-counter

4

clr


Counters Internal Design

• How can we design a simple counter?



Four-Bit Binary Ripple Up-Counter Internal Design

• Ripple counter is also called asynchronous counter


Q3 Q2 Q1 Q0

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1


Four-Bit Binary Ripple Up-Counter Internal Design

• What is the problem with ripple counters?


Q3 Q2 Q1 Q0

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1


Four-Bit Synchronous Up-Counter Internal Design

• Synchronous counters avoid settling time problem



Three-Bit Ripple Down-Counter Internal Design

• Ripple counter is also called asynchronous counter


Q2 Q1 Q0

0 0 0

1 1 1

1 1 0

1 0 1

1 0 0

0 1 1

0 1 0

0 0 1

0 0 0

T Q

Q Clock

T Q

Q

T Q

Q

1

Q 0 Q 1 Q 2

Clock

Q 0

Q 1

Q 2

Count 0 7 6 5 4 3 2 1 0


Synchronous Mod-10 Counter Internal Design

• Note that: clear has priority over load and count



8-bit Synchronous Counter Internal Design

• Can we construct 8-bit counter from 4-bit counter?



8-bit Synchronous Counter Internal Design

• We can construct 8-bit counter from 4-bit counter


It can be done via cascading.

Carry Output (CO) is connected

to the second counter. CO is

also known as terminal count (tc).

When CO is one it means we are

at 00001111, transitioning to

00010000 (assuming count-up)


Mod-4 Ring Counter Internal Design

• Ring counter: only 1 flip-flop is in 1 state



Synchronous Mod-6 Counter Using JK Flip-Flops

• Three clocked JK flip-flops. Why?




• Imagine we are counting a pattern


Q1 Q2 Q3

0 0 0

0 1 0

0 1 1

1 1 0

1 0 1

0 0 1

0 0 0

- - -

Pay attention that

it is not binary increments

Pattern repeats itself





Present State Next State

Q1 Q2 Q3 Q1 Q2 Q3

0 0 0

0 1 0

0 1 1

1 1 0

1 0 1

0 0 1





Present State Next State

Q1 Q2 Q3 Q1 Q2 Q3

0 0 0 0 1 0

0 1 0 0 1 1

0 1 1 1 1 0

1 1 0 1 0 1

1 0 1 0 0 1

0 0 1 0 0 0


JK Flip-Flop Symbol and Characteristic Table

• JK flip-flop: toggle flip-flop when JK is 11

• Application table is shown on the right


J K 𝑸(t+1)

0 0 no change Q(t)

0 1 0

1 0 1

1 1 toggle Q’(t)

Q(t) Q(t+1) J K

0 0 0 -

0 1 1 -

1 0 - 1

1 1 - 0





Present State Next State Flip-flop Input

Q1 Q2 Q3 Q1 Q2 Q3 J1 K1 J2 K2 J3 K3

0 0 0 0 1 0

0 1 0 0 1 1

0 1 1 1 1 0

1 1 0 1 0 1

1 0 1 0 0 1

0 0 1 0 0 0





Present State Next State Flip-flop Input

Q1 Q2 Q3 Q1 Q2 Q3 J1 K1 J2 K2 J3 K3

0 0 0 0 1 0 0 - 1 - 0 -

0 1 0 0 1 1 0 - - 0 1 -

0 1 1 1 1 0 1 - - 0 - 1

1 1 0 1 0 1 - 0 - 1 1 -

1 0 1 0 0 1 - 1 0 - - 0

0 0 1 0 0 0 0 - 0 - - 1


Synchronous Mod-6 Counter Using Flip-Flops

• Work at your pleasure on other FF implementations



D Flip-Flop Symbol and Characteristic Table

• The output follows input on the rising edge of clock



D Q(t+1)

0 0

1 1

Q(t) Q(t+1) D

0 0 0

0 1 1

1 0 0

1 1 1


Synchronous Mod-6 Counter Using D Flip-Flops



T Flip-Flop Symbol and Characteristic Table

• T flip-flop: toggle flip-flop

• The output toggles on the rising edge of clock



T Q(t+1)

0 Q(t)

1 Q’(t)

Q(t) Q(t+1) T

0 0 0

0 1 1

1 0 1

1 1 0


Synchronous Mod-6 Counter Using T Flip-Flops



SR Flip-Flop Symbol and Characteristic Table

• SR flip-flop: Similar to SR latch, edge-triggered



S R Q(t+1)

0 0 no change Q(t)

0 1 0

1 0 1

1 1 X

Q(t) Q(t+1) S R

0 0 0 -

0 1 1 0

1 0 0 1

1 1 - 0


Synchronous Mod-6 Counter Using SR Flip-Flops



Up/Down Counter Internal Design

• Can count either up or down


ld 4-bit register

C t c

4

4 4 4 4

4

c n t clr clr

dir

4-bit up/down counter

4 4

–1 +1

1 0 2 x 1

1 0 4-bit 2 x 1


Timers Overview

• Pulses output at user-specified timer interval

– when enabled

• “Ticks” like a clock

• Interval specified as multiple of base time unit

– if base is 1 µs and user wants pulse every 300 ms,

• loads 300,000 into timer

• Width is bitwidth that can be loaded

– e.g. 32-bit timer, with 1µs base, has a max. interval of 232 µs


Q


Timers Internal Design

• Can design using oscillator, register, down-counter


C tc

Q

1 microsec

oscillator

ld

32-bit down-counter

unused

enable cnt

ld load

32

M

32-bit register

1 0 4-bit 2x1

-1

load

enable

Q

32-bit 1-microsec

timer

32

M


Counters/Timers Summary

• Counters are sequential components that

– increments or decrements

• Ripple counters are known as asynchronous counters

– causes problems related to propagation delay

• Ring counter: only 1 flip-flop is in 1 state

• Binary patterns can be counted too

• Up/down counter can count both directions

• Timers pulse output at user-specified timer interval



References and Further Reading

• [V2011] Frank Vahid, Digital Design with RTL Design, VHDL, and Verilog, 2nd edition, Wiley, 2011.

• [G2003] Donald D. Givone, Digital Principles and Design, McGraw-Hill, 2003.

• [BV2009] Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design, 3rd edition, McGraw-Hill, 2009.



End of Foils


introduction to digital logic -...

Documents