introduction to analog integrated circuits design

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EECT 6326 Analog IC Design

Introduction

Instructor: Prof. Hoi Lee

Department of Electrical Engineering

The University of Texas at Dallas

[email protected]

EE6326 Introduction H. Lee pg. 2

Course Information

Prerequisite

• EE 4340 / EECT 5340 (Senior Level: Analog IC

Design)

Objective

• To introduce the principles of analog integrated circuit

design and to provide the circuit level analog IC

design knowledge required in the analog IC design

industry and research.

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Textbook and Reference Books

Textbook

• Design of Analog CMOS Integrated Circuits, by Behzad Razavi, McGraw-Hill, 2001. ISBN: 0072380322.

Recommended

• Analysis and Design of Analog Integrated Circuits, Paul R. Gray, Paul J. Hurst, Stephen H. Lewis, and Robert G. Meyer, John Wiley & Sons, Inc., 5th edition, 2009. ISBN: 0470245996.

• CMOS Analog Circuit Design, Phillip E. Allen and Douglas R. Holberg, Oxford University Press, 2nd edition, 2002. ISBN: 0-19-511644-5

• Operational Amplifiers – Theory and Design, Johan H. Huijsing, Kluwer. ISBN: 0792372840

• Analog Design for CMOS VLSI Systems, Franco Maloberti, Kluwer Academic Publishers, 2001. ISBN: 0792375505.


Coverage of Topics

Topics Gray Razavi

MOSFET & BJT Device Models 1 2, 16

Single-Stage Amplifier 3 3

Differential Amplifiers 3 4

Current Sources and Sinks 4 5

References 4 11

Opamp Design 6 9

Input Offset Voltage 3 Handout

Frequency Response 7 6

Stability and Compensation 9 10

Transient Responses Handout Handout

Two-Stage Amplifier Design Handout Handout

Hspice Tutorial (2/10 TA) Handout Handout

Cadence Tutorial (2/10 TA) Handout Handout

Review

(1/14 – 1/30)

HW & Proj.

Major Topics

(2/4 – 5/1)

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Course Grading Policy

Course Grading Policy • Quiz 20%

• Project 20%

• Midterm Exam 20%

• Final Exam 40%.

Exams • All the exams are closed book with an one-sided letter-sized notes

allowed for Midterm Exam and a two-sided paper for the Final Exam. All grades become final one week after they are returned in class.

• Midterm: 3/6/13 class time

• Final: 5/10/13 2:00p.m. – 4:45p.m.

Homework and Project • Homework will be assigned on a bi-weekly basis and be collected at the

beginning of the class on the due date except the first homework. No late homework. The homework solution will be posted on the professor’s webpage. Some of the homework and the project require the use of cadence/analog artist design tools; tutorial will be given at the beginning of the semester. In order to use Cadence tools at UTD, a UTD UNIX account is required. It is OK to use Cadence tools at your workplace if preferred.

Any student scored 80/100 in the

final examination will automatically

get A.


Academic Honesty

It is the responsibility of the instructor to

encourage an environment where you can learn

and your accomplishments will be rewarded

fairly.

Any behavior that compromises the University’s

rules of academic honesty will be reported to the

Dean of Students.

The penalty of academic dishonesty ranges from

receiving F grade in this class to being expelled

from the university.

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Attendance and Email Announcement

You are responsible for all course materials,

announcements, and notes, etc. made during

our regular class meeting time.

If you send email to ask for questions, please

start with “EECT 6326 ****” in the title of the

email.

• Example 1: “EECT 6326 Project submission”

• Example 2: “EECT 6326 Unable to attend class due

to sickness”

• Example 3: “EECT 6326 Scope of midterm exam”


Professor Contact Information

Contact Information

• Office: ECSN 4.918

• Phone: (972) 883-4841

• Email: [email protected]

• Webpage: www.utdallas.edu/~hoilee

Office Hours

• 2:00pm – 3:00pm on Mondays or by appointment

• This is the time I set aside just to help you - the

students in EECT 6326 class.

TA and TA office hours - TBD.

http://www.utdallas.edu/~hoilee

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Class Information

All course materials including syllabus, notes,

etc will be distributed through UTD elearning

• elearning.utdallas.edu (using netid and password to

login)

No homework in the first week

TA information will be updated in the second

week


Power Input/Output

Signals

An IC System

Power Management

Sensor

Interface

Circuits

DSP

Data

Converter

Wireline

Communication

Circuits

Wireless

Communication

Circuits

Data

Converter

Natural

Signal

Electrical/optical

Data Links

High-speed

Data

Wireless Channel

Modulated

Signal

Analog & Mixed-Signal Integrated Systems

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Related “Analog” Courses at UTD

Undergraduate Level

• EE 3311

• EE 4340

Graduate Level

• EECT 5340 Analog IC Design and Analysis (Same as EE 4340)

• EECT 6326 Analog IC Design (Core)

• EECT 6378 Power Management Circuits (Elective)

• EECT 7326 Advanced Analog IC Design (Elective)

• EECT 7327 A/D & D/A Converters (Elective)

• EERF 6330 RFIC Design (Elective)

• EECT 6379 Energy Harvesting (offer in Spring 13)

• EECT 7v88 High Speed Data Communication Circuits (offer in

Spring 13)


DIGITAL CIRCUITS ARE ON OR OFF

‘ANALOG DEALS WITH THE GRAY’†

“Global use of products such as cell phones, digital cameras, digital music players and satellite radios continues to grow. And more content, such as music, video and data, are being digitized to run on such devices. In order for digital devices to operate, they need chips that can take signals from the real world -- such as sound, power and temperature -- and compress them into a format that can be understood by a computer as zeros and ones.”

“The demand for many types of analog chips in the $32 billion-a-year analog market continues to grow. So does demand for these specialized designers.”

“With digital engineers outnumbering analog ones by an estimated 200-to-1, one headhunter has even said recruiting analog engineers is like using a pig to sniff out truffles in the forest.”

† Dennis Monticelli, Fellow at National in Santa Clara, quoted by MercuryNews http://www.siliconvalley.com/mld/siliconvalley/13493561.htm

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Analog Education†

“Analog chip design is highly collaborative -- passed down from generation to generation, like artisans learning from master tradesmen.”

“Analog engineers describe their apprenticeship much like the residency that doctors go through at a hospital. Because there are few automated tools in the field, they learn how to do chip layouts from being mentored and hearing the stories, tricks and mistakes of others.”

“Many companies, such as Texas Instruments, the leader in the field, and others like National Semiconductors, Analog Devices, Maxim and Linear, sponsor programs at universities, and then recruit heavily from that pack of engineers.”

† MercuryNews, http://www.siliconvalley.com/mld/siliconvalley/13493561.htm

Introduction (1)


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Introduction (2)


Introduction (3)


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Analog Design Flow


Analog Design (1)


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Analog Design (2)


Analog Design (3)


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Analog Design (4)


Analog Design (5)


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Analog Design (6)



13

Understanding Technology



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15

Analog Today


Future of Analog


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Notation, Terminology and Symbology

(1)



(2)


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(3)



(4)


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Applications of Analog IC

Example of Analog IC Applications

• Power management ICs for portable applications

Low-dropout regulators:

Convert a time varying battery voltage to a regulated

constant DC voltage for noise sensitive RF transceiver

Involve amplifier design, voltage reference design,

negative feedback concept, current mirrors and sinks,

frequency responses and compensation, transient

responses…

Why Power Management in Portable

Devices? (1)


Battery-Operated Portable Devices Energy Sources

Li-Ion Batteries

NiMH /NiCd Batteries

Long Battery Life,

Small Size, Light

Weight, & More

Functions

But, Limited

Battery Capacity

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Why Power Management in Portable

Devices? (2)


Provide a regulated power source • Low Dropout Regulator (LDO)

• Switched-Inductor DC-DC Regulator (SMPC)

• Switched-Capacitor Power Converter (SCPC)

Energy Source

Power Management Circuits ( 1)

Analog Part Digital Part RF Part Interface

Part


Low Dropout Regulator for Portable

Applications (1)

Key Achievements: • Developed dynamically-biased shunt feedback in the LDO to

minimize output transient overshoots and undershoots under massive load step changes.

• A 20mV undershoot under load step changes of 200mA/100ns.

IEEE CICC 2006, IEEE JSSC Aug. 2007

0.35m standard CMOS

CL

ErrorAmp

Rf1

Vbg

Vin

RL

Pass Device

Vout

Rf2

Dynamically-Biased

Shunt Feedback Buffer

Low dropout regulator design

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Low Dropout Regulator for Portable

Applications (2)

Total Vout = 54mV

Vdo

(V)

IL,max

(mA)

Iq

(mA)

Current

(%)

Vout

(mV) Tr (s)

CL

(F) ESR

Tech.

(m)

FOM

(ns)

JSSC 98 0.3 50 0.023 99.5 19 1.8 4.7 No 2.0 8.2

JSSC 00 N. A. 200 0.03 N. A. 220 1.1 1 Yes 1.0 0.165

JSSC 03 0.2 100 0.038 N. A. 130 2 10 Yes 0.6 4.9

TCAS-I 04 N. A. 160 0.025 N. A. 200 2.75 2.2 No 0.5 0.43

JSSC 07 N. A. 200 0.02 99.8 54 0.27 1 No 0.35 0.027

introduction to analog integrated circuits design

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