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8-bit AVR Microcontroller

ATmega128A

DATASHEET COMPLETE

Introduction

The Atmel® ATmega128A is a low-power CMOS 8-bit microcontroller basedon the AVR® enhanced RISC architecture. By executing powerful instructionsin a single clock cycle, the ATmega128A achieves throughputs close to1MIPS per MHz. This empowers system designer to optimize the device forpower consumption versus processing speed.

Features

• High-performance, Low-power Atmel AVR 8-bit Microcontroller• Advanced RISC Architecture

– 133 Powerful Instructions - Most Single-clock Cycle Execution– 32 × 8 General Purpose Working Registers + Peripheral Control

Registers– Fully Static Operation– Up to 16MIPS Throughput at 16MHz– On-chip 2-cycle Multiplier

• High Endurance Non-volatile Memory segments– 128Kbytes of In-System Self-programmable Flash program

memory– 4Kbytes EEPROM– 4Kbytes Internal SRAM– Write/Erase cycles: 10,000 Flash/100,000 EEPROM– Data retention: 20 years at 85°C/100 years at 25°C(1)

– Optional Boot Code Section with Independent Lock Bits• In-System Programming by On-chip Boot Program• True Read-While-Write Operation

– Up to 64 Kbytes Optional External Memory Space– Programming Lock for Software Security– SPI Interface for In-System Programming

• JTAG (IEEE std. 1149.1 Compliant) Interface– Boundary-scan Capabilities According to the JTAG Standard– Extensive On-chip Debug Support

Atmel-8151J-8-bit AVR Microcontroller_Datasheet_Complete-09/2015

– Programming of Flash, EEPROM, Fuses and Lock Bits through the JTAG Interface• Atmel QTouch® library support

– Capacitive touch buttons, sliders and wheels– Atmel QTouch and QMatrix acquisition– Up to 64 sense channels

• Peripheral Features– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes– Two Expanded 16-bit Timer/Counters with Separate Prescaler, Compare Mode and Capture

Mode– Real Time Counter with Separate Oscillator– Two 8-bit PWM Channels– 6 PWM Channels with Programmable Resolution from 2 to 16 Bits– Output Compare Modulator– 8-channel, 10-bit ADC

• 8 Single-ended Channels• 7 Differential Channels• 2 Differential Channels with Programmable Gain at 1x, 10x, or 200x

– Byte-oriented Two-wire Serial Interface– Dual Programmable Serial USARTs– Master/Slave SPI Serial Interface– Programmable Watchdog Timer with On-chip Oscillator– On-chip Analog Comparator

• Special Microcontroller Features– Power-on Reset and Programmable Brown-out Detection– Internal Calibrated RC Oscillator– External and Internal Interrupt Sources– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and

Extended Standby– Software Selectable Clock Frequency– ATmega103 Compatibility Mode Selected by a Fuse– Global Pull-up Disable

• I/O and Packages– 53 Programmable I/O Lines– 64-lead TQFP and 64-pad QFN/MLF

• Operating Voltages– 2.7 - 5.5V

• Speed Grades– 0 - 16MHz

Atmel ATmega128A [DATASHEET]Atmel-8151J-8-bit AVR Microcontroller_Datasheet_Complete-09/2015

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Table of Contents

Introduction......................................................................................................................1

Features.......................................................................................................................... 1

1. Description.................................................................................................................9

2. Configuration Summary...........................................................................................10

3. Ordering Information................................................................................................ 11

4. Block Diagram......................................................................................................... 12

5. ATmega103 and ATmega128A Compatibility.......................................................... 135.1. ATmega103 Compatibility Mode.................................................................................................13

6. Pin Configurations................................................................................................... 146.1. Pin Descriptions..........................................................................................................................14

7. Resources................................................................................................................18

8. Data Retention.........................................................................................................19

9. About Code Examples.............................................................................................20

10. Capacitive Touch Sensing....................................................................................... 21

11. AVR CPU Core........................................................................................................ 2211.1. Overview.....................................................................................................................................2211.2. ALU – Arithmetic Logic Unit........................................................................................................2311.3. Status Register...........................................................................................................................2311.4. General Purpose Register File................................................................................................... 2511.5. Stack Pointer.............................................................................................................................. 2611.6. Instruction Execution Timing...................................................................................................... 2811.7. Reset and Interrupt Handling..................................................................................................... 29

12. AVR Memories.........................................................................................................3212.1. Overview.....................................................................................................................................3212.2. In-System Reprogrammable Flash Program Memory................................................................3212.3. SRAM Data Memory...................................................................................................................3312.4. EEPROM Data Memory............................................................................................................. 3512.5. I/O Memory.................................................................................................................................3612.6. External Memory Interface......................................................................................................... 3612.7. Register Description................................................................................................................... 43

13. System Clock and Clock Options............................................................................ 5413.1. Clock Systems and their Distribution..........................................................................................5413.2. Clock Sources............................................................................................................................ 55

13.3. Default Clock Source..................................................................................................................5613.4. Crystal Oscillator........................................................................................................................ 5613.5. Low-frequency Crystal Oscillator................................................................................................5713.6. External RC Oscillator................................................................................................................ 5813.7. Calibrated Internal RC Oscillator................................................................................................5813.8. External Clock............................................................................................................................ 5913.9. Timer/Counter Oscillator.............................................................................................................6013.10. Register Description...................................................................................................................60

14. Power Management and Sleep Modes................................................................... 6314.1. Sleep Modes...............................................................................................................................6314.2. Idle Mode....................................................................................................................................6414.3. ADC Noise Reduction Mode.......................................................................................................6414.4. Power-down Mode......................................................................................................................6414.5. Power-save Mode.......................................................................................................................6414.6. Standby Mode............................................................................................................................ 6514.7. Extended Standby Mode............................................................................................................ 6514.8. Minimizing Power Consumption................................................................................................. 6514.9. Register Description................................................................................................................... 67

15. System Control and Reset.......................................................................................6915.1. Resetting the AVR...................................................................................................................... 6915.2. Reset Sources............................................................................................................................6915.3. Internal Voltage Reference.........................................................................................................7315.4. Watchdog Timer......................................................................................................................... 7315.5. Timed Sequences for Changing the Configuration of the Watchdog Timer............................... 7415.6. Register Description................................................................................................................... 75

16. Interrupts................................................................................................................. 7916.1. Interrupt Vectors in ATmega128A...............................................................................................7916.2. Register Description................................................................................................................... 84

17. External Interrupts................................................................................................... 8717.1. Register Description................................................................................................................... 87

18. I/O Ports.................................................................................................................. 9418.1. Overview.....................................................................................................................................9418.2. Ports as General Digital I/O........................................................................................................9518.3. Alternate Port Functions.............................................................................................................9918.4. Register Description................................................................................................................. 113

19. Timer/Counter3, Timer/Counter2, and Timer/Counter1 Prescalers....................... 13619.1. Overview...................................................................................................................................13619.2. Internal Clock Source............................................................................................................... 13619.3. Prescaler Reset........................................................................................................................13619.4. External Clock Source..............................................................................................................13619.5. Register Description................................................................................................................. 137

20. 16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3).................................139


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20.1. Features................................................................................................................................... 13920.2. Overview...................................................................................................................................13920.3. Accessing 16-bit Registers.......................................................................................................14220.4. Timer/Counter Clock Sources.................................................................................................. 14420.5. Counter Unit............................................................................................................................. 14420.6. Input Capture Unit.................................................................................................................... 14520.7. Output Compare Units..............................................................................................................14820.8. Compare Match Output Unit.....................................................................................................14920.9. Modes of Operation..................................................................................................................15020.10. Timer/Counter Timing Diagrams.............................................................................................. 15820.11. Register Description................................................................................................................. 159

21. 8-bit Timer/Counter0 with PWM and Asynchronous Operation............................. 19421.1. Features................................................................................................................................... 19421.2. Overview...................................................................................................................................19421.3. Timer/Counter Clock Sources.................................................................................................. 19521.4. Counter Unit............................................................................................................................. 19521.5. Output Compare Unit................................................................................................................19621.6. Compare Match Output Unit.....................................................................................................19821.7. Modes of Operation..................................................................................................................19921.8. Timer/Counter Timing Diagrams...............................................................................................20321.9. Asynchronous Operation of the Timer/Counter........................................................................ 20521.10. Timer/Counter Prescaler.......................................................................................................... 20621.11. Register Description................................................................................................................. 207

22. 8-bit Timer/Counter2 with PWM.............................................................................21722.1. Features................................................................................................................................... 21722.2. Overview...................................................................................................................................21722.3. Timer/Counter Clock Sources.................................................................................................. 21822.4. Counter Unit............................................................................................................................. 21822.5. Output Compare Unit................................................................................................................21922.6. Compare Match Output Unit.....................................................................................................22122.7. Modes of Operation..................................................................................................................22222.8. Timer/Counter Timing Diagrams...............................................................................................22622.9. Register Description................................................................................................................. 227

23. Output Compare Modulator (OCM1C2).................................................................23523.1. Overview...................................................................................................................................23523.2. Description................................................................................................................................235

24. SPI – Serial Peripheral Interface........................................................................... 23724.1. Features................................................................................................................................... 23724.2. Overview...................................................................................................................................23724.3. SS Pin Functionality................................................................................................................. 24024.4. Data Modes.............................................................................................................................. 24124.5. Register Description................................................................................................................. 242

25. USART...................................................................................................................24725.1. Features................................................................................................................................... 247


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25.2. Overview...................................................................................................................................24725.3. Clock Generation......................................................................................................................24925.4. Frame Formats.........................................................................................................................25225.5. USART Initialization..................................................................................................................25325.6. Data Transmission – The USART Transmitter......................................................................... 25425.7. Data Reception – The USART Receiver.................................................................................. 25725.8. Asynchronous Data Reception.................................................................................................26025.9. Multi-Processor Communication Mode.....................................................................................26325.10. Examples of Baud Rate Setting............................................................................................... 26425.11. Register Description................................................................................................................. 267

26. TWI - Two-wire Serial Interface............................................................................. 27626.1. Features................................................................................................................................... 27626.2. Overview...................................................................................................................................27626.3. Two-Wire Serial Interface Bus Definition..................................................................................27826.4. Data Transfer and Frame Format.............................................................................................27926.5. Multi-master Bus Systems, Arbitration and Synchronization....................................................28226.6. Using the TWI...........................................................................................................................28326.7. Multi-master Systems and Arbitration.......................................................................................30026.8. Register Description................................................................................................................. 301

27. Analog Comparator............................................................................................... 30827.1. Overview...................................................................................................................................30827.2. Analog Comparator Multiplexed Input...................................................................................... 30827.3. Register Description................................................................................................................. 309

28. ADC - Analog to Digital Converter.........................................................................31328.1. Features................................................................................................................................... 31328.2. Overview...................................................................................................................................31328.3. Starting a Conversion...............................................................................................................31528.4. Prescaling and Conversion Timing...........................................................................................31528.5. Changing Channel or Reference Selection.............................................................................. 31728.6. ADC Noise Canceler................................................................................................................ 31928.7. ADC Conversion Result............................................................................................................32228.8. Register Description................................................................................................................. 324

29. JTAG Interface and On-chip Debug System..........................................................33429.1. Features................................................................................................................................... 33429.2. Overview...................................................................................................................................33429.3. TAP – Test Access Port............................................................................................................33529.4. TAP Controller.......................................................................................................................... 33629.5. Using the Boundary-scan Chain...............................................................................................33729.6. Using the On-chip Debug System............................................................................................ 33729.7. On-chip Debug Specific JTAG Instructions.............................................................................. 33829.8. Using the JTAG Programming Capabilities.............................................................................. 33929.9. Bibliography..............................................................................................................................33929.10. IEEE 1149.1 (JTAG) Boundary-scan........................................................................................33929.11. Data Registers..........................................................................................................................34029.12. Boundry-scan Specific JTAG Instructions................................................................................ 342


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29.13. Boundary-scan Chain...............................................................................................................34329.14. ATmega128A Boundary-scan Order........................................................................................ 35329.15. Boundary-scan Description Language Files............................................................................ 36229.16. Register Description.................................................................................................................362

30. Boot Loader Support – Read-While-Write Self-Programming............................... 36530.1. Features................................................................................................................................... 36530.2. Overview...................................................................................................................................36530.3. Application and Boot Loader Flash Sections............................................................................36530.4. Read-While-Write and No Read-While-Write Flash Sections...................................................36630.5. Boot Loader Lock Bits.............................................................................................................. 36830.6. Entering the Boot Loader Program...........................................................................................36930.7. Addressing the Flash During Self-Programming...................................................................... 37030.8. Self-Programming the Flash.....................................................................................................37130.9. Register Description................................................................................................................. 379

31. Memory Programming........................................................................................... 38231.1. Program and Data Memory Lock Bits.......................................................................................38231.2. Fuse Bits...................................................................................................................................38331.3. Signature Bytes........................................................................................................................ 38531.4. Calibration Byte........................................................................................................................ 38531.5. Page Size................................................................................................................................. 38631.6. Parallel Programming Parameters, Pin Mapping, and Commands..........................................38631.7. Parallel Programming...............................................................................................................38831.8. Serial Downloading...................................................................................................................39531.9. Serial Programming Pin Mapping.............................................................................................39631.10. Programming Via the JTAG Interface.......................................................................................400

32. Electrical Characteristics....................................................................................... 41432.1. DC Characteristics....................................................................................................................41432.2. Speed Grades.......................................................................................................................... 41632.3. Clock Characteristics................................................................................................................41632.4. System and Reset Characteristics........................................................................................... 41732.5. Two-wire Serial Interface Characteristics................................................................................. 41832.6. Parallel Programming Characteristics...................................................................................... 41932.7. SPI Timing Characteristics....................................................................................................... 42132.8. ADC Characteristics................................................................................................................. 42332.9. External Data Memory Timing.................................................................................................. 426

33. Typical Characteristics...........................................................................................43233.1. Active Supply Current...............................................................................................................43233.2. Idle Supply Current...................................................................................................................43633.3. Power-down Supply Current.....................................................................................................43933.4. Power-save Supply Current......................................................................................................44033.5. Standby Supply Current........................................................................................................... 44133.6. Pin Pull-up................................................................................................................................ 44233.7. Pin Driver Strength................................................................................................................... 44333.8. Pin Thresholds and Hysteresis.................................................................................................44533.9. BOD Thresholds and Analog Comparator Offset..................................................................... 446


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33.10. Internal Oscillator Speed..........................................................................................................44833.11. Current Consumption of Peripheral Units.................................................................................45433.12. Current Consumption in Reset and Reset Pulse width............................................................ 457

34. Register Summary.................................................................................................461

35. Instruction Set Summary....................................................................................... 464

36. Packaging Information...........................................................................................46936.1. 64A........................................................................................................................................... 46936.2. 64M1.........................................................................................................................................470

37. Errata.....................................................................................................................47137.1. ATmega128A Rev. U................................................................................................................ 471

38. Datasheet Revision History................................................................................... 47338.1. Rev. 8151J – 07/2015...............................................................................................................47338.2. Rev. 8151I – 08/2014............................................................................................................... 47338.3. Rev. 8151H – 02/11.................................................................................................................. 47338.4. Rev. 8151G – 07/10..................................................................................................................47338.5. Rev. 8151F – 06/10.................................................................................................................. 47338.6. Rev. 8151E – 02/10..................................................................................................................47338.7. Rev. 8151D – 07/09..................................................................................................................47338.8. Rev. 8151C – 05/09..................................................................................................................47438.9. Rev. 8151B – 03/09..................................................................................................................47438.10. Rev. 8151A – 08/08..................................................................................................................474


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1. DescriptionThe Atmel AVR core combines a rich instruction set with 32 general purpose working registers. All the 32registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers tobe accessed in one single instruction executed in one clock cycle. The resulting architecture is more codeefficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.

The ATmega128A provides the following features: 128Kbytes of In-System Programmable Flash withRead- While-Write capabilities, 4Kbytes EEPROM, 4Kbytes SRAM, 53 general purpose I/O lines, 32general purpose working registers, Real Time Counter (RTC), four flexible Timer/Counters with comparemodes and PWM, 2 USARTs, one byte oriented Two-wire Serial Interface, an 8-channel, 10-bit ADC withoptional differential input stage with programmable gain, programmable Watchdog Timer with InternalOscillator, one SPI serial port, IEEE std. 1149.1 compliant JTAG test interface, also used for accessingthe On-chip Debug system and programming and six software selectable power saving modes. The Idlemode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system tocontinue functioning. The Power-down mode saves the register contents but freezes the Oscillator,disabling all other chip functions until the next interrupt or Hardware Reset. In Power-save mode, theasynchronous timer continues to run, allowing the user to maintain a timer base while the rest of thedevice is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules exceptAsynchronous Timer and ADC, to minimize switching noise during ADC conversions. In Standby mode,the Crystal/Resonator Oscillator is running while the rest of the device is sleeping. This allows very faststart-up combined with low power consumption. In Extended Standby mode, both the main Oscillator andthe Asynchronous Timer continue to run.

The device is manufactured using Atmel’s high-density nonvolatile memory technology. The On-chip ISPFlash allows the program memory to be reprogrammed in-system through an SPI serial interface, by aconventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core.The boot program can use any interface to download the application program in the application Flashmemory. Software in the Boot Flash section will continue to run while the Application Flash section isupdated, providing true Read- While-Write operation. By combining an 8-bit RISC CPU with In-SystemSelf-Programmable Flash on a monolithic chip, the Atmel ATmega128A is a powerful microcontroller thatprovides a highly flexible and cost effective solution to many embedded control application

The ATmega128A AVR is supported with a full suite of program and system development tools including:C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.


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2. Configuration SummaryFeatures ATmega128A

Pin count 64

Flash (KB) 128

SRAM (KB) 4

EEPROM (KB) 4

External Memory (KB) 64

General Purpose I/O pins 53

SPI 1

TWI (I2C) 1

USART 2

ADC 10-bit, up to 76.9ksps (15ksps at max resolution)

ADC channels 6 (8 in TQFP and QFN/MLF packages)

AC propagation delay Typ 400ns

8-bit Timer/Counters 2

16-bit Timer/Counters 2

PWM channels 6

RC Oscillator +/-3%

VREF Bandgap

Operating voltage 2.7 - 5.5V

Max operating frequency 16MHz

Temperature range -55°C to +125°C

JTAG Yes


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3. Ordering InformationSpeed (MHz) Power Supply Ordering Code(2) Package(1) Operational Range

16 2.7 - 5.5V

ATmega128A-AUATmega128A-AUR(3)

ATmega128A-MU

ATmega128A-MUR(3)

64A64A

64M1

64M1

Industrial (-40oC to 85oC)

Note: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for

detailed ordering information and minimum quantities.2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances

(RoHS directive). Also Halide free and fully Green.3. Tape and Reel

Package Type

64A 64-lead, 14 × 14 × 1.0 mm, Thin Profile Plastic Quad Flat Package (TQFP)

64M1 64-pad, 9 × 9 × 1.0 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)


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4. Block DiagramFigure 4-1 Block Diagram

CPU

ADC ADC[7:0]AREF

I/OPORTS

DATABUS

SRAM

OCD FLASH

NVMprogramming

JTAG

TC 0(8-bit async)

SPI

ACAIN0AIN1ACOADCMUX

EEPROMEEPROMIF

TC 3(16-bit)

OC3A/BT3ICP3

TWISDASCL

USART 1RxD1TxD1XCK1

InternalReference

WatchdogTimer

Power management

and clock control

VCC

GND

PowerSupervisionPOR/BOD &

RESET

TOSC2

XTAL2

RESET

XTAL1

TOSC1

TCKTMSTDI

TDO

INT[7:0]

OC0

MISOMOSISCK

SS

PA[7:0]PB[7:0]PC[7:0]PD[7:0]PE[7:0]PF[7:0]PG[4:0]

USART 0RxD0TxD0XCK0

TC 1(16-bit)

OC1A/B/CT1ICP1

TC 2(8-bit)

T2OC2

AD[7:0]A[15:8]RD/WR/ALE

ExtMem

ExtInt

SERPROG

PARPROGPENPDI

PDOSCK

Clock generation

1MHz intosc

32.768kHzXOSC

Externalclock

8MHzCrystal Osc

12MHzExternalRC Osc

8MHzCalib RC


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5. ATmega103 and ATmega128A CompatibilityThe ATmega128A is a highly complex microcontroller where the number of I/O locations supersedes the64 I/O locations reserved in the AVR instruction set. To ensure backward compatibility with theATmega103, all I/O locations present in ATmega103 have the same location in ATmega128A. Mostadditional I/O locations are added in an Extended I/O space starting from 0x60 to 0xFF, (that is, in theATmega103 internal RAM space). These locations can be reached by using LD/LDS/LDD andST/STS/STD instructions only, not by using IN and OUT instructions. The relocation of the internal RAMspace may still be a problem for ATmega103 users. Also, the increased number of interrupt vectors mightbe a problem if the code uses absolute addresses. To solve these problems, an ATmega103 compatibilitymode can be selected by programming the fuse M103C. In this mode, none of the functions in theExtended I/O space are in use, so the internal RAM is located as in ATmega103. Also, the ExtendedInterrupt vectors are removed.

The Atmel AVR ATmega128A is 100% pin compatible with ATmega103, and can replace the ATmega103on current Printed Circuit Boards. The application note “Replacing ATmega103 by ATmega128A”describes what the user should be aware of replacing the ATmega103 by an ATmega128A.

5.1. ATmega103 Compatibility ModeBy programming the M103C fuse, the ATmega128A will be compatible with the ATmega103 regards toRAM, I/O pins and interrupt vectors as described above. However, some new features in ATmega128Aare not available in this compatibility mode, these features are listed below:

• One USART instead of two, Asynchronous mode only. Only the eight least significant bits of theBaud Rate Register is available.

• One 16 bits Timer/Counter with two compare registers instead of two 16-bit Timer/Counters withthree compare registers.

• Two-wire serial interface is not supported.• Port C is output only.• Port G serves alternate functions only (not a general I/O port).• Port F serves as digital input only in addition to analog input to the ADC.• Boot Loader capabilities is not supported.• It is not possible to adjust the frequency of the internal calibrated RC Oscillator.• The External Memory Interface can not release any Address pins for general I/O, neither configure

different wait-states to different External Memory Address sections.• In addition, there are some other minor differences to make it more compatible to ATmega103:• Only EXTRF and PORF exists in MCUCSR.• Timed sequence not required for Watchdog Time-out change.• External Interrupt pins 3 - 0 serve as level interrupt only.• USART has no FIFO buffer, so data overrun comes earlier.

Unused I/O bits in ATmega103 should be written to 0 to ensure same operation in ATmega128A.


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6. Pin ConfigurationsFigure 6-1 Pinout ATmega128A

1

2

3

4

44

43

42

41

40

39

38

5

6

7

8

9

10

11

33

32313029282726252423

37

36

35

34

12

13

14

15

16

17 18 19 20 21 2245

46

47

48

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

RESE

T

VCC

GN

D

GN

D

VCC

ARE

F

AVCC

GN

DPA3 (AD3)

PA4 (AD4)

PA5 (AD5)

PA6 (AD6)

PA7 (AD7)

PG2 (ALE)

PC7 (A15)

PC6 (A14)

PC5 (A13)

PC4 (A12)

PC3 (A11)

PC2 (A10)

PC1 (A9)

PC0 (A8)

PG1 (RD)

PG0 (WR)

PA0

(AD

0)

PA1

(AD

1)

PA2

(AD

2)

PF7

(AD

C7/T

DI)

PF6

(AD

C6/T

DO

)

PF5

(AD

C5/T

MS)

PF4

(AD

C4/T

CK)

PF3

(AD

C3)

PF2

(AD

C2)

PF1

(AD

C1)

PF0

(AD

C0)

XTA

L2

XTA

L1

(TO

SC1)

PG

4

(TO

SC2)

PG

3

(OC2

/OC1

C) P

B7

(SCL

/INT0

) PD

0

(SD

A/IN

T1) P

D1

(RX

D1/

INT2

) PD

2

(TX

D1/

INT3

) PD

3

(ICP1

) PD

4

(XCK

1) P

D5

(T1)

PD

6

(T2)

PD

7

PEN

(RXD0/PDI) PE0

(TXD0/PDO) PE1

(XCK0/AIN0) PE2

(OC3A/AIN1) PE3

(OC3B/INT4) PE4

(OC3C/INT5) PE5

(T3/INT6) PE6

(ICP3/INT7) PE7

(SS) PB0

(SCK) PB1

(MOSI) PB2

(MISO) PB3

(OC0) PB4

(OC1A) PB5

(OC1B) PB6

PowerGround

Programming/debug

Digital

Analog

Crystal/Osc

External Memory

Note: The Pinout figure applies to both TQFP and MLF packages. The bottom pad under the QFN/MLFpackage should be soldered to ground.

6.1. Pin Descriptions

6.1.1. VCCDigital supply voltage.


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6.1.2. GNDGround.

6.1.3. Port A (PA7:PA0)Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port Aoutput buffers have symmetrical drive characteristics with both high sink and source capability. As inputs,Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The PortA pins are tristated when a reset condition becomes active, even if the clock is not running.

Port A also serves the functions of various special features of the ATmega128A as listed in AlternateFunctions of Port A.

Related LinksAlternate Functions of Port A on page 100

6.1.4. Port B (PB7:PB0)Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port Boutput buffers have symmetrical drive characteristics with both high sink and source capability. As inputs,Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The PortB pins are tristated when a reset condition becomes active, even if the clock is not running.

Port B also serves the functions of various special features of the ATmega128A as listed in AlternateFunctions of Port B.

Related LinksAlternate Functions of Port B on page 102

6.1.5. Port C (PC7:PC0)Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port Coutput buffers have symmetrical drive characteristics with both high sink and source capability. As inputs,Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The PortC pins are tristated when a reset condition becomes active, even if the clock is not running.

Port C also serves the functions of special features of the ATmega128A as listed in Alternate Functions ofPort C. In ATmega103 compatibility mode, Port C is output only, and the port C pins are not tri-statedwhen a reset condition becomes active.

Note: The Atmel AVR ATmega128A is by default shipped in ATmega103 compatibility mode. Thus, if theparts are not programmed before they are put on the PCB, PORTC will be output during first power up,and until the ATmega103 compatibility mode is disabled.

Related LinksAlternate Functions of Port C on page 104

6.1.6. Port D (PD7:PD0)Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port Doutput buffers have symmetrical drive characteristics with both high sink and source capability. As inputs,Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The PortD pins are tristated when a reset condition becomes active, even if the clock is not running.

Port D also serves the functions of various special features of the ATmega128A as listed in AlternateFunctions of Port D.

Related LinksAlternate Functions of Port D on page 106


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6.1.7. Port E (PE7:PE0)Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port Eoutput buffers have symmetrical drive characteristics with both high sink and source capability. As inputs,Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The PortE pins are tristated when a reset condition becomes active, even if the clock is not running.

Port E also serves the functions of various special features of the ATmega128A as listed in AlternateFunctions of Port E.

Related LinksAlternate Functions of Port E on page 108

6.1.8. Port F (PF7:PF0)Port F serves as the analog inputs to the A/D Converter.

Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins canprovide internal pull-up resistors (selected for each bit). The Port F output buffers have symmetrical drivecharacteristics with both high sink and source capability. As inputs, Port F pins that are externally pulledlow will source current if the pull-up resistors are activated. The Port F pins are tri-stated when a resetcondition becomes active, even if the clock is not running. If the JTAG interface is enabled, the pull-upresistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a Reset occurs.

The TDO pin is tri-stated unless TAP states that shift out data are entered.

Port F also serves the functions of the JTAG interface.

In ATmega103 compatibility mode, Port F is an input Port only.

6.1.9. Port G (PG4:PG0)Port G is a 5-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port Goutput buffers have symmetrical drive characteristics with both high sink and source capability. As inputs,Port G pins that are externally pulled low will source current if the pull-up resistors are activated. The PortG pins are tristated when a reset condition becomes active, even if the clock is not running.

Port G also serves the functions of various special features.

The port G pins are tri-stated when a reset condition becomes active, even if the clock is not running.

In Atmel AVR ATmega103 compatibility mode, these pins only serves as strobes signals to the externalmemory as well as input to the 32kHz Oscillator, and the pins are initialized to PG0 = 1, PG1 = 1, andPG2 = 0 asynchronously when a reset condition becomes active, even if the clock is not running. PG3and PG4 are oscillator pins.

6.1.10. RESETReset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even ifthe clock is not running. The minimum pulse length is given in System and Reset Characteristics. Shorterpulses are not guaranteed to generate a reset.

Related LinksSystem and Reset Characteristics on page 417

6.1.11. XTAL1Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

6.1.12. XTAL2Output from the inverting Oscillator amplifier.


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6.1.13. AVCCAVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally connected to VCC,even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter.

6.1.14. AREFAREF is the analog reference pin for the A/D Converter.

6.1.15. PENPEN is a programming enable pin for the SPI Serial Programming mode, and is internally pulled high. Byholding this pin low during a Power-on Reset, the device will enter the SPI Serial Programming mode.PEN has no function during normal operation.


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7. ResourcesA comprehensive set of development tools, application notes and datasheets are available for downloadon http://www.atmel.com/avr.


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http://www.atmel.com/avr

8. Data RetentionReliability Qualification results show that the projected data retention failure rate is much less than 1 PPMover 20 years at 85°C or 100 years at 25°C.


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9. About Code ExamplesThis datasheet contains simple code examples that briefly show how to use various parts of the device.These code examples assume that the part specific header file is included before compilation. Be awarethat not all C compiler vendors include bit definitions in the header files and interrupt handling in C iscompiler dependent. Please confirm with the C compiler documentation for more details.

For I/O registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructionsmust be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS”combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.


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10. Capacitive Touch SensingThe Atmel QTouch Library provides a simple to use solution to realize touch sensitive interfaces on mostAtmel AVR microcontrollers. The QTouch Library includes support for the QTouch and QMatrix®

acquisition methods.

Touch sensing can be added to any application by linking the appropriate Atmel QTouch Library for theAVR Microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors,and then calling the touch sensing API’s to retrieve the channel information and determine the touchsensor states.

The QTouch Library is FREE and downloadable from the Atmel website at the following location: www.atmel.com/qtouchlibrary. For implementation details and other information, refer to the AtmelQTouch Library User Guide - also available for download from the Atmel website.


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http://www.atmel.com/qtouchlibraryhttp://www.atmel.com/dyn/resources/prod_documents/doc8207.pdfhttp://www.atmel.com/dyn/resources/prod_documents/doc8207.pdf

11. AVR CPU Core

11.1. OverviewThis section discusses the Atmel AVR core architecture in general. The main function of the CPU core isto ensure correct program execution. The CPU must therefore be able to access memories, performcalculations, control peripherals, and handle interrupts.

Figure 11-1 Block Diagram of the AVR MCU Architecture

FlashProgramMemory

Ins tructionRegis te r

Ins tructionDecoder

ProgramCounter

Control Lines

32 x 8Genera lPurpose

Regis tre rs

ALU

Sta tusand Control

I/O Lines

EEPROM

Data Bus 8-bit

DataSRAM

Dire

ct A

ddre

ssin

g

Indi

rect

Add

res s

ing

Inte rruptUnit

SPIUnit

WatchdogTimer

AnalogCompara tor

i/O Module 2

i/O Module1

i/O Module n

In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separatememories and buses for program and data. Instructions in the Program memory are executed with asingle level pipelining. While one instruction is being executed, the next instruction is pre-fetched from theProgram memory. This concept enables instructions to be executed in every clock cycle. The Programmemory is In-System Reprogrammable Flash memory.

The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clockcycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALUoperation, two operands are output from the Register File, the operation is executed, and the result isstored back in the Register File – in one clock cycle.

Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Spaceaddressing – enabling efficient address calculations. One of the these address pointers can also be usedas an address pointer for look up tables in Flash Program memory. These added function registers arethe 16-bit X-, Y-, and Z-register, described later in this section.

The ALU supports arithmetic and logic operations between registers or between a constant and aregister. Single register operations can also be executed in the ALU. After an arithmetic operation, theStatus Register is updated to reflect information about the result of the operation.


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The Program flow is provided by conditional and unconditional jump and call instructions, able to directlyaddress the whole address space. Most AVR instructions have a single 16-bit word format. EveryProgram memory address contains a 16- or 32-bit instruction.

Program Flash memory space is divided in two sections, the Boot program section and the Applicationprogram section. Both sections have dedicated Lock Bits for write and read/write protection. The SPMinstruction that writes into the Application Flash memory section must reside in the Boot program section.

During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack.The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is onlylimited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in thereset routine (before subroutines or interrupts are executed). The Stack Pointer SP is read/writeaccessible in the I/O space. The data SRAM can easily be accessed through the five different addressingmodes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps.

A flexible interrupt module has its control registers in the I/O space with an additional global interruptenable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vectortable. The interrupts have priority in accordance with their Interrupt Vector position. The lower theInterrupt Vector address, the higher the priority.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI,and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locationsfollowing those of the Register File, 0x20 - 0x5F. In addition, the ATmega128A has Extended I/O spacefrom $60 in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used.

11.2. ALU – Arithmetic Logic UnitThe high-performance Atmel AVR ALU operates in direct connection with all the 32 general purposeworking registers. Within a single clock cycle, arithmetic operations between general purpose registers orbetween a register and an immediate are executed. The ALU operations are divided into three maincategories – arithmetic, logical, and bit-functions. Some implementations of the architecture also providea powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the“Instruction Set” section for a detailed description.

11.3. Status RegisterThe Status Register contains information about the result of the most recently executed arithmeticinstruction. This information can be used for altering program flow in order to perform conditionaloperations. Note that the Status Register is updated after all ALU operations, as specified in theInstruction Set Reference. This will in many cases remove the need for using the dedicated compareinstructions, resulting in faster and more compact code.

The Status Register is not automatically stored when entering an interrupt routine and restored whenreturning from an interrupt. This must be handled by software.


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11.3.1. SREG – The AVR Status RegisterWhen using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. Whenaddressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offsetaddresses. The device is a complex microcontroller with more peripheral units than can be supportedwithin the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O spacefrom 0x60 in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

Name: SREGOffset: 0x3FReset: 0x00Property:

When addressing I/O Registers as data space the offset address is 0x5F

Bit 7 6 5 4 3 2 1 0 I T H S V N Z C

Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0

Bit 7 – I: Global Interrupt EnableThe Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interruptenable control is then performed in separate control registers. If the Global Interrupt Enable Register iscleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enablesubsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLIinstructions, as described in the Instruction Set Reference.

Bit 6 – T: Bit Copy StorageThe Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination forthe operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, anda bit in T can be copied into a bit in a register in the Register File by the BLD instruction.

Bit 5 – H: Half Carry FlagThe Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is useful in BCDarithmetic. See the “Instruction Set Description” for detailed information.

Bit 4 – S: Sign Bit, S = N ⊕ VThe S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement OverflowFlag V. See the “Instruction Set Description” for detailed information.

Bit 3 – V: Two’s Complement Overflow FlagThe Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction SetDescription” for detailed information.

Bit 2 – N: Negative FlagThe Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “InstructionSet Description” for detailed information.

Bit 1 – Z: Zero FlagThe Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction SetDescription” for detailed information.


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Bit 0 – C: Carry FlagThe Carry Flag C indicates a Carry in an arithmetic or logic operation. See the “Instruction SetDescription” for detailed information.

11.4. General Purpose Register FileThe Register File is optimized for the Atmel AVR Enhanced RISC instruction set. In order to achieve therequired performance and flexibility, the following input/output schemes are supported by the RegisterFile:

• One 8-bit output operand and one 8-bit result input.• Two 8-bit output operands and one 8-bit result input.• Two 8-bit output operands and one 16-bit result input.• One 16-bit output operand and one 16-bit result input.

The following figure shows the structure of the 32 general purpose working registers in the CPU.

Figure 11-2 AVR CPU General Purpose Working Registers7 0 Addr.

R0 0x00

R1 0x01

R2 0x02

…

R13 0x0D

Genera l R14 0x0E

Purpose R15 0x0F

Working R16 0x10

Regis ters R17 0x11

…

R26 0x1A X-regis te r Low Byte

R27 0x1B X-regis te r High Byte

R28 0x1C Y-regis te r Low Byte

R29 0x1D Y-regis te r High Byte

R30 0x1E Z-regis te r Low Byte

R31 0x1F Z-regis te r High Byte

Most of the instructions operating on the Register File have direct access to all registers, and most ofthem are single cycle instructions.

As shown in the figure above, each register is also assigned a Data memory address, mapping themdirectly into the first 32 locations of the user Data Space. Although not being physically implemented asSRAM locations, this memory organization provides great flexibility in access of the registers, as the X-,Y-, and Z-pointer Registers can be set to index any register in the file.

11.4.1. The X-register, Y-register and Z-registerThe registers R26:R31 have some added functions to their general purpose usage. These registers are16-bit address pointers for indirect addressing of the Data Space. The three indirect address registers X,Y and Z are defined as described in the following figure.


25

Figure 11-3 The X-, Y- and Z-Registers15 XH XL 0

X-regis te r 7 0 7 0

R27 (0x1B) R26 (0x1A)

15 YH YL 0

Y-regis te r 7 0 7 0

R29 (0x1D) R28 (0x1C)

15 ZH ZL 0

Z-regis te r 7 0 7 0

R31 (0x1F) R30 (0x1E)

In the different addressing modes these address registers have functions as fixed displacement,automatic increment, and automatic decrement (see the Instruction Set Reference for details).

11.5. Stack PointerThe Stack is mainly used for storing temporary data, for storing local variables and for storing returnaddresses after interrupts and subroutine calls. Note that the Stack is implemented as growing fromhigher to lower memory locations. The Stack Pointer Register always points to the top of the Stack. TheStack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located.A Stack PUSH command will decrease the Stack Pointer.

The Stack in the data SRAM must be defined by the program before any subroutine calls are executed orinterrupts are enabled. Initial Stack Pointer value equals the last address of the internal SRAM and theStack Pointer must be set to point above start of the SRAM, see Figure Data Memory Map in SRAM DataMemory.

See table below for Stack Pointer details.

Table 11-1 Stack Pointer instructions

Instruction Stack pointer Description

PUSH Decremented by 1 Data is pushed onto the stack

CALLICALLRCALL

Decremented by 2 Return address is pushed onto the stack with a subroutine call orinterrupt

POP Incremented by 1 Data is popped from the stack

RETRETI

Incremented by 2 Return address is popped from the stack with return from subroutine orreturn from interrupt

The Atmel AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bitsactually used is implementation dependent. Note that the data space in some implementations of the AVRarchitecture is so small that only SPL is needed. In this case, the SPH Register will not be present.

Related LinksSRAM Data Memory on page 33


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11.5.1. SPH and SPL - Stack Pointer High and Stack Pointer Low RegisterBit 15 14 13 12 11 10 9 8

0x3E SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH

0x3D SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL

7 6 5 4 3 2 1 0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

R/W R/W R/W R/W R/W R/W R/W R/W

Initia l Value0

0 0 0 0 0 0 0

0 0 0 0 0 0 0 0


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11.5.2. RAMPZ – RAM Page Z Select RegisterWhen using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. Whenaddressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offsetaddresses. The device is a complex microcontroller with more peripheral units than can be supportedwithin the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O spacefrom 0x60 in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

Name: RAMPZOffset: 0x3BReset: 0x00Property:

When addressing I/O Registers as data space the offset address is 0x5B

Bit 7 6 5 4 3 2 1 0 RAMPZ0

Access R/W Reset 0

Bit 0 – RAMPZ0: Extended RAM Page Z-pointerThe RAMPZ Register is normally used to select which 64K RAM Page is accessed by the Z-pointer. Asthe Atmel AVR ATmega128A does not support more than 64K of SRAM memory, this register is used onlyto select which page in the program memory is accessed when the ELPM/SPM instruction is used. Thedifferent settings of the RAMPZ0 bit have the following effects:

• RAMPZ0 = 0: Program memory address 0x0000 - 0x7FFF (lower 64Kbytes) is accessed byELPM/SPM

• RAMPZ0 = 1: Program memory address 0x8000 - 0xFFFF (higher 64Kbytes) is accessed byELPM/SPM

Note that LPM is not affected by the RAMPZ setting.

11.6. Instruction Execution TimingThis section describes the general access timing concepts for instruction execution. The Atmel AVR CPUis driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. Nointernal clock division is used.

The following figure shows the parallel instruction fetches and instruction executions enabled by theHarvard architecture and the fast-access Register File concept. This is the basic pipelining concept toobtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions perclocks, and functions per power-unit.


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Figure 11-4 The Parallel Instruction Fetches and Instruction Executions

clk

1s t Ins truction Fe tch1s t Ins truction Execute

2nd Ins truction Fe tch2nd Ins truction Execute

3rd Ins truction Fe tch3rd Ins truction Execute

4th Ins truction Fe tch

T1 T2 T3 T4

CPU

The next figure shows the internal timing concept for the Register File. In a single clock cycle an ALUoperation using two register operands is executed, and the result is stored back to the destinationregister.

Figure 11-5 Single Cycle ALU Operation

Tota l Execution Time

Regis te r Operands Fe tch

ALU Opera tion Execute

Result Write Back

T1 T2 T3 T4

clkCPU

11.7. Reset and Interrupt HandlingThe Atmel AVR provides several different interrupt sources. These interrupts and the separate ResetVector each have a separate Program Vector in the Program memory space. All interrupts are assignedindividual enable bits which must be written logic one together with the Global Interrupt Enable bit in theStatus Register in order to enable the interrupt. Depending on the Program Counter value, interrupts maybe automatically disabled when Boot Lock Bits BLB02 or BLB12 are programmed. This feature improvessoftware security. See the section Memory Programming for details.

The lowest addresses in the Program memory space are by default defined as the Reset and InterruptVectors. The complete list of Vectors is shown in Interrupts . The list also determines the priority levels ofthe different interrupts. The lower the address the higher is the priority level. RESET has the highestpriority, and next is INT0 – the External Interrupt Request 0. The Interrupt Vectors can be moved to thestart of the boot Flash section by setting the Interrupt Vector Select (IVSEL) bit in the MCU ControlRegister (MCUCR). Refer to Interrupts for more information. The Reset Vector can also be moved to thestart of the boot Flash section by programming the BOOTRST Fuse, see Boot Loader Support – Read-While-Write Self-Programming.

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. Theuser software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can theninterrupt the current interrupt routine. The I-bit is automatically set when a Return from Interruptinstruction – RETI – is executed.

There are basically two types of interrupts. The first type is triggered by an event that sets the InterruptFlag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to


29

execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. InterruptFlags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interruptcondition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set andremembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or moreinterrupt conditions occur while the global interrupt enable bit is cleared, the corresponding InterruptFlag(s) will be set and remembered until the global interrupt enable bit is set, and will then be executed byorder of priority.

The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts donot necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled,the interrupt will not be triggered.

When the AVR exits from an interrupt, it will always return to the main program and execute one moreinstruction before any pending interrupt is served.

Note that the Status Register is not automatically stored when entering an interrupt routine, nor restoredwhen returning from an interrupt routine. This must be handled by software.

When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. Nointerrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction.The following example shows how this can be used to avoid interrupts during the timed EEPROM writesequence.

Assembly Code Example

in r16, SREG ; store SREG valuecli ; disable interrupts during timed sequencesbi EECR, EEMWE ; start EEPROM writesbi EECR, EEWEout SREG, r16 ; restore SREG value (I-bit)

C Code Example

char cSREG;cSREG = SREG; /* store SREG value *//* disable interrupts during timed sequence */_CLI();EECR |= (1

C Code Example

_enable_interrupt(); /* set global interrupt enable */_SLEEP(); /* enter sleep, waiting for interrupt *//* note: will enter sleep before any pending interrupt(s) */

Related LinksMemory Programming on page 382Interrupts on page 79Boot Loader Support – Read-While-Write Self-Programming on page 365

11.7.1. Interrupt Response TimeThe interrupt execution response for all the enabled Atmel AVR interrupts is four clock cycles minimum.After four clock cycles, the Program Vector address for the actual interrupt handling routine is executed.During this 4-clock cycle period, the Program Counter is pushed onto the Stack. The Vector is normally ajump to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs duringexecution of a multi-cycle instruction, this instruction is completed before the interrupt is served. If aninterrupt occurs when the MCU is in sleep mode, the interrupt execution response time is increased byfour clock cycles. This increase comes in addition to the start-up time from the selected sleep mode.

A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, theProgram Counter (2 bytes) is popped back from the Stack, the Stack Pointer is incremented by 2, and theI-bit in SREG is set.


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12. AVR Memories

12.1. OverviewThis section describes the different memories in the Atmel AVR ATmega128A. The AVR architecture hastwo main memory spaces, the Data memory and the Program Memory space. In addition, theATmega128A features an EEPROM Memory for data storage. All three memory spaces are linear andregular.

12.2. In-System Reprogrammable Flash Program MemoryThe ATmega128A contains 128K bytes On-chip In-System Reprogrammable Flash memory for programstorage. Since all AVR instructions are 16- or 32-bits wide, the Flash is organized as 64K x 16 bits. Forsoftware security, the Flash Program memory space is divided into two sections, Boot Program sectionand Application Program section.

The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega128A ProgramCounter (PC) is 16 bits wide, thus addressing the 64K Program memory locations. The operation of BootProgram section and associated Boot Lock Bits for software protection are described in detail in BootLoader Support – Read-While-Write Self-Programming. Memory Programming contains a detaileddescription on Flash Programming in SPI, JTAG, or Parallel Programming mode.

Constant tables can be allocated within the entire Program memory address space (see the LPM – LoadProgram memory instruction description).

Timing diagrams for instruction fetch and execution are presented in Instruction Execution Timing.

Figure 12-1 Program Memory Map

$0000

$FFFF

Applica tion Flash Section

Boot Flash Section

Related LinksBoot Loader Support – Read-While-Write Self-Programming on page 365Memory Programming on page 382Instruction Execution Timing on page 28


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12.3. SRAM Data MemoryThe Atmel AVR ATmega128A supports two different configurations for the SRAM data memory as listedin the table below

Table 12-1 Memory Configurations

Configuration Internal SRAM Data Memory External SRAM Data Memory

Normal mode 4096 up to 64K

ATmega103 Compatibility mode 4000 up to 64K

Figure 12-2 Data Memory Map on page 34 shows how the ATmega128A SRAM Memory is organized.

The ATmega128A is a complex microcontroller with more peripheral units than can be supported withinthe 64 location reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. The ExtendedI/O space does not exist when the ATmega128A is in the ATmega103 compatibility mode.

In normal mode, the first 4352 Data Memory locations address both the Register file, the I/O Memory,Extended I/O Memory, and the internal data SRAM. The first 32 locations address the Register file, thenext 64 location the standard I/O memory, then 160 locations of Extended I/O memory, and the next 4096locations address the internal data SRAM.

In ATmega103 compatibility mode, the first 4096 Data Memory locations address both the Register file,the I/O Memory and the internal data SRAM. The first 32 locations address the Register file, the next 64location the standard I/O memory, and the next 4000 locations address the internal data SRAM.

An optional external data SRAM can be used with the ATmega128A. This SRAM will occupy an area inthe remaining address locations in the 64K address space. This area starts at the address following theinternal SRAM. The Register file, I/O, Extended I/O and Internal SRAM occupies the lowest 4352bytes innormal mode, and the lowest 4096 bytes in the ATmega103 compatibility mode (Extended I/O notpresent), so when using 64 Kbytes (65536 bytes) of External Memory, 61184 bytes of External Memoryare available in normal mode, and 61440 bytes in ATmega103 compatibility mode. Refer to ExternalMemory Interface on page 36 for details on how to take advantage of the external memory map.

When the addresses accessing the SRAM memory space exceeds the internal data memory locations,the external data SRAM is accessed using the same instructions as for the internal data memory access.When the internal data memories are accessed, the read and write strobe pins (PG0 and PG1) areinactive during the whole access cycle. External SRAM operation is enabled by setting the SRE bit in theMCUCR Register.

Accessing external SRAM takes one additional clock cycle per byte compared to access of the internalSRAM. This means that the commands LD, ST, LDS, STS, LDD, STD, PUSH, and POP take oneadditional clock cycle. If the Stack is placed in external SRAM, interrupts, subroutine calls and returnstake three clock cycles extra because the two-byte program counter is pushed and popped, and externalmemory access does not take advantage of the internal pipe-line memory access. When external SRAMinterface is used with wait-state, onebyte external access takes two, three, or four additional clock cyclesfor one, two, and three wait-states respectively. Interrupts, subroutine calls and returns will need five,seven, or nine clock cycles more than specified in the instruction set manual for one, two, and three wait-states.

The five different addressing modes for the data memory cover: Direct, Indirect with Displacement,Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register file, registers R26to R31 feature the indirect addressing pointer registers.


33

The direct addressing reaches the entire data space.

The Indirect with Displacement mode reaches 63 address locations from the base address given by theY- or Zregister.

When using register indirect addressing modes with automatic pre-decrement and post-increment, theaddress registers X, Y, and Z are decremented or incremented.

The 32 general purpose working registers, 64 I/O registers, and the 4096 bytes of internal data SRAM inthe Atmel AVR ATmega128A are all accessible through all these addressing modes. The Register file isdescribed in General Purpose Register File.

Figure 12-2 Data Memory Map

Memory Configuration B

32 Regis te rs64 I/O Regis te rs

Inte rna l SRAM(4000 x 8)

$0000 - $001F$0020 - $005F

$1000$0FFF

$FFFF

$0060

Data Memory

Externa l SRAM(0 - 64K x 8)

Memory Configuration A

32 Regis te rs64 I/O Regis te rs

Inte rna l SRAM(4096 x 8)

$0000 - $001F$0020 - $005F

$1100$10FF

$FFFF

$0060 - $00FF

Data Memory

Externa l SRAM(0 - 64K x 8)

160 Ext I/O Reg.$0100

Related LinksGeneral Purpose Register File on page 25

12.3.1. Data Memory Access TimesThis section describes the general access timing concepts for internal memory access. The internal dataSRAM access is performed in two clkCPU cycles as described in the figure below.


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Figure 12-3 On-chip Data SRAM Access Cycles

clk

WR

RD

Data

Data

Address Address Valid

T1 T2 T3

Compute Address

Rea

dW

rite

CPU

Memory Vccess Ins truction Next Ins truction

12.4. EEPROM Data MemoryThe Atmel AVR ATmega128A contains 4Kbytes of data EEPROM memory. It is organized as a separatedata space, in which single bytes can be read and written. The EEPROM has an endurance of at least100,000 write/erase cycles. The access between the EEPROM and the CPU is described below,specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM ControlRegister.

Memory Programming contains a detailed description on EEPROM Programming in SPI, JTAG, orParallel Programming mode.

Related LinksMemory Programming on page 382

12.4.1. EEPROM Read/Write AccessThe EEPROM Access Registers are accessible in the I/O space.

The write access time for the EEPROM is given in Table 12-2 EEPROM Programming Time on page48. A self-timing function, however, lets the user software detect when the next byte can be written. Ifthe user code contains instructions that write the EEPROM, some precautions must be taken. In heavilyfiltered power supplies, VCC is likely to rise or fall slowly on Power-up/down. This causes the device forsome period of time to run at a voltage lower than specified as minimum for the clock frequency used.See Preventing EEPROM Corruption on page 36 for details on how to avoid problems in thesesituations.

In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer tothe description of the EEPROM Control Register for details on this.

When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction isexecuted. When the EEPROM is written, the CPU is halted for two clock cycles before the next instructionis executed.

12.4.2. EEPROM Write during Power-down Sleep ModeWhen entering Power-down sleep mode while an EEPROM write operation is active, the EEPROM writeoperation will continue, and will complete before the Write Access time has passed. However, when thewrite operation is completed, the Oscillator continues running, and as a consequence, the device does


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not enter Power-down entirely. It is therefore recommended to verify that the EEPROM write operation iscompleted before entering Power-down.

12.4.3. Preventing EEPROM CorruptionDuring periods of low VCC, the EEPROM data can be corrupted because the supply voltage is too low forthe CPU and the EEPROM to operate properly. These issues are the same as for board level systemsusing EEPROM, and the same design solutions should be applied.

An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regularwrite sequence to the EEPROM requires a minimum voltage to operate correctly. Second, the CPU itselfcan execute instructions incorrectly, if the supply voltage is too low.

EEPROM data corruption can easily be avoided by following this design recommendation:

Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be doneby enabling the internal Brown-out Detector (BOD). If the detection level of the internal BOD does notmatch the needed detection level, an external low VCC Reset Protection circuit can be used. If a resetoccurs while a write operation is in progress, the write operation will be completed provided that thepower supply voltage is sufficient.

12.5. I/O MemoryThe I/O space definition of the ATmega128A is shown in Register Summary.

All ATmega128A I/Os and peripherals are placed in the I/O space. The I/O locations are accessed by theIN and OUT instructions, transferring data between the 32 general purpose working registers and the I/Ospace. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI andCBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBICinstructions. Refer to the instruction set section for more details. When using the I/O specific commandsIN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data spaceusing LD and ST instructions, 0x20 must be

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