CSE307

COMPUTER ARCHITECTURE

Introduction

Course Overview and Basic understanding of Computer Architecture

CSE307

COMPUTER ARCHITECTURE

Assistant ProfessorDept. of Computer Science and Engineering

Jahangirnager University, Savar, DhakaBangladesh

Instructor:

Abu Sayed Md. Mostafizur Rahaman

Teaching Assistant:Rezaur Rahman (Reza)

4th year 2nd year student (Appeared)Dept. of Computer Science EngineeringJahangirnagar University, Savar, Dhaka

Bangladesh

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omSeat Plan during this course

1st Column 2nd Column 3rd column

408 407 427   393 1404 403   422 391 397

406 1407 400   421 1575 420   423 405 424

411 416 419   399 392 410   390 389 1406

1402 1403 1652   414 396 417   1401 418 425

401 398 409   415 402 1405   413 426 394

DoorDoor

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Schedule may subject to change

From 23 May, 2011 to 19 September, 2011 Every week (excluding holydays)

Monday

11:00 -13:00 (2 classes)

Wednesday

10:20 - 12:10 (2 classes)

Schedule

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Lecture Materials

Computer Architecture

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Contains News and schedule update Lecture slides Exercises (at least 5) Assignments Additional materials for further readings

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References

Computer Architecture

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D.A. Patterson and J.L. Hennessy, Computer Architecture and Design: The Hardware/Software Interface, 4th edition, Elsevier/Morgan Kauffman. 3rd edition OK if 4th edition not available.

Mostafa ABD-Al-Barr & Hesham El-Rewini “Fundamentals of computer organization and architecture” Willy press.

J. Hennessy and D. Patterson, “Computer Architecture: A Quantitative Approach” (3rd Edition), Morgan Kaufmann Publishers, 2003. ISBN 1558605967.

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Grading Policy

Computer Architecture

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Attendance = 10 % Assignments = 05 % Exercises test = 05 %

Instant exams Class Test (Best of three) = 20 %======================================

= 40 % Final Examination = 60 %======================================

= 100 %

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Class Test Schedule

Computer Architecture

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Test number Date and Time Syllabus

CT-01 WednesdayJuly 13, 2011

Chapter: 01Chapter: 02

CT-02 MondayAugust 08, 2011

Chapter: 03

CT-03 MondayAugust 29, 2011

Chapter: 04

CT-04 MondaySeptember 19, 2011

Chapter: 05 and others

**Schedule may subject to change

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omCourse Overview Introduction: Instruction codes, formats, cycle, timing etc; Addressing modes;

Types of instruction; RISC characteristics; CISC characteristics and Yields. Chapter 1 & 2 from first reference book (3 lectures)

Computer Arithmetic: Different types of data representation; Addition and subtraction; Multiplication algorithms; Division algorithms. Chapter 3 from 1st reference book (3 lectures)

Fundamentals of parallel processing: Parallel processing; Pipelining; Vector processing; Multiprocessors; Array processor, Bit-slice processor Interconnection structures. From 1st and 3rd reference books (4 lectures)

Memory Organization: Main memory; Auxiliary memory; Associative memory; Cache memory; Virtual memory; Memory management requirements and hardware. Chapter 5 from 1st reference book (2 lectures)

Parallel Computer Architecture(1 lecture) Distributed Memory Architecture(1 lecture) Input-Output Organization: Input-Output Interfaces; Data transfer,

Interrupts; Direct Memory Access (DMA); Input-output channel. Chapter 6 from first reference book (1 lecture)

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Sl Task description Duration Date1 First Meeting for the course no: CSE-307 2 hrs Monday, May 23, 20112 Lecture 01 2 hrs Wednesday, May 25, 20113 Lecture 02 2 hrs Monday, May 30, 20114 Lecture 03 2 hrs Wednesday, June 01, 20115 Summer vocation 20 days Monday, June 06, 20116 Exercise: 01 from chapter 1 2 hrs Monday, July 04, 20117 Exercise: 02 from chapter 2 2 hrs Wednesday, July 06, 20118 Lecture 04 2 hrs Monday, July 11, 20119 Lecture 05 with CT-01 2 hrs Wednesday, July 13, 2011

10 Lecture 06 2 hrs Monday, July 18, 201111 Reserved Day 2 hrs Wednesday, July 20, 201112 Exercise: 03 in computer arithmetic 2 hrs Monday, July 25, 201113 Lecture 07 2 hrs Wednesday, July 27, 201114 Lecture 08 2 hrs Monday, August 01, 201115 Lecture 09 2 hrs Wednesday, August 03, 201116 Lecture 10 with CT-02 2 hrs Monday, August 08, 201117 Reserved Day 2 hrs Wednesday, August 10, 201118 Exercise: 04 in parallel processing 2 hrs Wednesday, August 17, 201119 Lecture 11 2 hrs Monday, August 22, 201120 Lecture 12 2 hrs Wednesday, August 24, 201121 Lecture 13 with CT-03 2 hrs Monday, August 29, 201122 Lecture 14 2 hrs Wednesday, August 31, 201123 Reserved Day 2 hrs Monday, September 05, 201124 Exercise: 05 in memory and others 2 hrs Wednesday, September 07, 201125 Reserved Day 2 hrs Monday, September 12, 201126 Reserved Day 2 hrs Wednesday, September 14, 201127 Lecture:15 with CT-04 2 hrs Monday, September 19, 2011

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omWhat is Computer Architecture?Easy Answer

Computer Architecture =

Instruction Set Architecture +

Machine Organization

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omThe Instruction Set: a Critical Interface

instruction set

software

hardware

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omInstruction Set Architecture

A very important abstraction: interface between hardware and low-level

software standardizes instructions, machine language

bit patterns, etc. advantage: allows different implementations of

the same architecture disadvantage: sometimes prevents adding

new innovations Modern instruction set architectures:

80x86/Pentium/K6, PowerPC, DEC Alpha, MIPS, SPARC, HP

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I/O systemInstars. Set Proc.

Compiler

OperatingSystem

Application

Digital DesignCircuit Design

Instruction Set Architecture

Firmware

Datapath & Control

Layout

What is Computer Architecture?Better (More Detailed) Answer

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omClassic Components of a Computer

Input (mouse, keyboard, …) Output (display, printer, …) Memory

main (DRAM), cache (SRAM) secondary (disk, CD, DVD, …)

Datapath Control

Input

Processor

Control

Datapath

Output

Memory100101001011000000101001010100011111011101100110100101001011000010010100101100001001010010110000

Processor(CPU)

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omFeatures and benefits

Intel® Core™2 Duo processor With an you will get performance-rich technologies, including up to 6MB of shared L2 cache, up

to 1333 MHz Front Side Bus, plus these additional Intel® technologies built in: Intel® multi-core processing

Provides greater multitasking performance by combining two independent processor cores in one physical package¹

Intel® Wide Dynamic Execution Improves execution time and energy efficiency with more instructions per clock cycle

Intel® Intelligent Power Capability Enables smarter, more energy-efficient performance

Intel® Smart Memory Access Improves system performance by optimizing the use of the available data bandwidth

Intel® Advanced Smart Cache Enables higher performance and more efficient cache subsystem by optimizing for multi-core

processors Intel® Advanced Digital Media Boost accelerates

A broad range of applications including video, speech and image, photo processing, encryption, financial, engineering, and scientific applications

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CSE-307 20Computer Architecture

Thank YouNext

Computer Abstractions and Technology