introduction and basic hardware supportweb.cse.ohio-state.edu/~babic.1/a.4s.pdf · introduction and...

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01/07/2020

Introduction and Basic Hardware Support

Presentation A

CSE 2431/5431: Introduction to Operating Systems

Gojko BabićStudy: 1.1−1.5, 9.1.1, 11.1.1, 12.1−12.2

g. babic Presentation A 2

• to give students an understanding of functions and structures of operating systems and issues in the design of operating systems;

• to provide students with appreciations of process concept (single thread processes and multi thread processes) and process/thread synchronization and communication;

• To give students understanding of memory hierarchy.

Course Objectives

A process is an operating system concept that captures

the idea of a program in execution.


1. Hardware – provides basic computing resources (CPU,

memory, I/O devices).

2. Operating system – controls and coordinates the use of

the hardware among the various application programs for

the various users.

3. Applications programs – define the ways in which the

system resources are used to solve the computing

problems of the users (compilers, database systems,

video games, business programs).

Computer System Components


Abstract View of Computer Components

Thus, an operating system is the software layer between the hardware and the user programs.

2


Computer Architecture• A modern meaning of the term computer architecture covers

three aspects of computer design:– instruction set architecture,– computer organization and– computer hardware.

• Instruction set architecture - ISA refers to the programmer visible machine interface such as instruction set, data representation (integers, real, characters, etc.), registers,memory organization and exception (i.e. interrupt) handling.One can think of an ISA of a particular computer as a hardware functionality of that computer.

• A computer organization and computer hardware are twocomponents of the implementation of a machine (to provide functionality defined by ISA).

• Instruction set architecture - ISA is of particular importance to an operating system.

Basic (Single CPU) Computer Structure

• CPU and device controllers connect through common bus providing access to shared memory

• Symmetric multiprocessor (SMP) architecture has several CPU’s


• A bus is a collection of parallel wires that carry address, data, and control signals.

• Buses are typically shared by multiple devices.

7Presentation A

Bus Structure Connecting CPU & Memory

Mainmemory

I/O bridge

Bus interface

ALU

Register file

Processor chip

System bus Memory bus

Program Counter

Instruct. Register

g. babic 8

Typical System Organization

Presentation A

Processor chip

Mainmemory

I/O bridge

Bus interface

ALU

Register file

System bus Memory bus

Disk controller

Graphicsadapter

USBcontroller

Mouse Keyboard Monitor

Disk

I/O bus Expansion slots forother devices such

as network adapters.

Prog. Counter

Instr. Register

g. babic

3


Approaches to Instruction Set Architecture

• For many years the interaction between ISA and implementat-ions was believed to be small, and implementation issueswere not a major focus in designing instruction set architecture.

• In the 1980’s, it becomes clear that both the difficulty of designing processors and performance inefficiency of processors could be increased by instruction set architecturecomplications.

• Two main approaches of ISA:– RISC (Reduced Instruction Set Computer) architecture– CISC (Complex Instruction Set Computer) architecture.

• The exploitation of instruction-level parallelism, through multiple instruction issue and out of order execution.

• And since mid 90’s all new processors are of RISC architecture.

• Complex Instruction Set Computer: dominant style through mid-80’s.

• Philosophy: include instructions to perform “typical” programming tasks.

• Stack-oriented instruction set: use stack to pass arguments and save program counter, explicit push and pop instructions.

• Intel x86-64 processors found in over 90% desktop computers• Arithmetic instructions may access memory, e.g. the instruction addq %rax, 12(%rbx,%rcx,4)

adds two 64-bit integers, one as a content of register %raxand another as a content of memory location (complex address calculation) and store result in the same memory location (requires memory read & write).

CISC Instruction Set Architecture

Presentation A 10g. babic

• x86 (IA-32) instruction (length from one to 17 bytes) consist of: optional instruction prefixes (in any order), 1-3 opcode bytes – determines the action of the statement, an addressing-form specifier (if required) consisting of: the ModR/M byte - addressing modes register/memory, sometimes the SIB (Scale-Index-Base) byte, a displacement (if required),

an immediate data field (if required).11

Intel x86-64 Instruction Format

g. babic Presentation A

• Reduced Instruction Set Computer:

internal project at IBM, later popularized by Hennessy (Stanford) and Patterson (Berkeley)

• Fewer & simpler instructions, fewer addressing modes:

thus it might take more instructions to get given task done,

but can execute them with small and fast hardware.

• Register-oriented instruction set:

many (typically several sets of 32) registers,

use for arguments, return pointer, temporaries.

• Only few load and store instructions can access memory.

• Simple memory addressing

• All instructions one size (32 bits) and few instruction formats.

• Three address instructions (2 operands and destination)

RISC Instruction Set Architecture


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MIPS Instruction Layout

/ft

/fs/fd

/offset

/ft

and fd fs funct ft

jump_target

• 32-bit fixed format instruction and 3 formats;• Totally dominate laptop/desktop/server market.

• Evolutionary design:

backwards compatible up until 8086, introduced in 1978,

added more features as time goes on.

• Have complex instruction set computer (CISC):

many different instructions with many different formats,

but, only small subset of instructions encountered with Linux/gcc application programs.

• Hard to match performance of reduced instruction set computers (RISC):

but, Intel has done just that!

in terms of speed, but less so for low power.

Intel x86-64 Processors


• Original debate in late 1980’s: very strong opinions! CISC proponents easy for compiler, fewer code bytes, RISC proponents better for optimizing compilers, can

make run fast with simple chip design.• ISA choice isn’t a technical issue for desktop processors today: with enough hardware, can make anything run fast, code compatibility may be more important.

• For embedded processors, RISC makes sense: smaller, cheaper, less power, most cell phones and tablets use RISC ARM processor.

• Intel has evolved from x86 (IA-32) to x86-64: x86-64 uses 64-bit words (including addresses), x86-64 adopted some features found in RISC, such as

more registers (16) and less reliance on stack.

CISC vs. RISC


• At the beginning of an instruction execution, CPU places an address (say AA) from the program counter on the memory bus.

16Presentation A

Machine Instruction Execution

• Main memory reads address AA from the memory bus, retrie-ves instruction XX from address AA, and places it on the bus.

ALU

Register file

Bus interface

AA0

AAXX

Main memoryI/O bridge

Instr. Register

Prog. Counter

ALU

Register file

Bus interface

XX 0

AAXX

Main memoryI/O bridge

Prog. Counter

Instr. Register

g. babic

5

• The processor reads instruction XX from the bus and copies it in the instruction register, and then continue its execution.

17Presentation A

Machine Instruction Execution (cont.)

ALU

Register file

Bus interface XX

Main memory0I/O bridge

Prog. Counter

Instr. Register

• Main memory is accessed in the similar way by an instruction that reads from memory during its execution, with the following difference: the address is calculated by the processor using

parameters in the instruction, a content from memory is loaded in one of registers.

g. babic

• Memory write happens during execution of an instruction that store some result into some memory location.

• The processor calculates address AA from parameters in the instruction and places address AA on bus.

• Main memory reads it and waits for the corresponding data to arrive.

18Presentation A

Main Memory(RAM) Write

YYALU

Register file

Bus interface

AA

Main memory0

AA

I/O bridge

Prog. Counter

Instr. Register

g. babic

• CPU places data YY, from the register specified by the instruction, on the bus.

19Presentation A

Main Memory(RAM) Write (cont.)

YYALU

Register file

Bus interface

YY

Main memory0

AA

I/O bridge

Prog. Counter

Instr. Register

YYALU

Register file

Bus interface YY

Main memory0

AA

I/O bridge

Prog. Counter

Instr. Register

• Memory reads data YY from bus and stores it at address AA.

g. babic g. babic Presentation A 20

• I/O controllers (devices) and the CPU can execute concurrently.

• Each device controller is in charge of a particular device and a device controller normally has a small local buffer.

• I/O is transfer from the device to local buffer of controller.

• For device controllers without DMA, CPU moves data from/to main memory to/from local buffers. Device controller informs CPU that it has finished its operation by causing an I/O interrupt(usually per each byte).

• DMA (Direct Memory Access) is used for high-speed I/O devices able to transmit information at close to memory speeds. DMA device controller transfers blocks of data from buffer storage directly to main memory without CPU intervention. With DMA, only one interrupt is generated per block, rather than the one interrupt per byte.

Computer System Operation

6


Moving-Head Disk Mechanism

• A sector (usually 512 bytes) is a basic unit of transfer (read/write)

• CPU initiates a disk read by writing a read command, logical sector (block) number, and destination memory address to a port (registers) associated with disk controller.

22Presentation A

Reading a Disc Sector

Mainmemory

ALU

Register file

Processor chip

Disk controller

Graphicsadapter

USBcontroller

mouse Keyboard Monitor

Disk

I/O bus

Bus interface

Prog. Counter

Instr. Register

g. babic

• Disk controller reads the sector and performs a direct memory access (DMA) transfer into main memory.

• Note that CPU has to execute some (any) instructions, while disc controller is reading

23Presentation A

Mainmemory

ALU

Register file

Processor chip

Disk controller

Graphicsadapter

USBcontroller


Disk

I/O bus

Bus interface

Prog. Counter

Instr. Register

Reading a Disc Sector (cont.)

g. babic

• When the DMA transfer completes, the disk controller notifies the CPU with an interrupt,asserting a special “interrupt” pin on the CPU

• An interrupt normally causes that CPU ceases executing its current code, and starts executing some other code. But how is that done????

24Presentation A

Mainmemory

ALU

Register file

Processor chip

Disk controller

Graphicsadapter

USBcontroller


Disk

I/O bus

Bus interface

Prog. Counter

Instr. Register

Reading a Disc Sector (cont.)

g. babic

7


• Operating system is a program that acts as an intermediary between a user of a computer and the computer hardware.

• Operating system goals:– make solving user problems easier, i.e. make the computer

system convenient to use– use of the computer hardware in an efficient manner.

• O.S. implements a set of system calls that provide a convenient mean for requesting operating system services.– Example: file system & its system calls and disk structure.

• Operating system manages the hardware resources such as:– processor (CPU),– main memory (RAM),– I/O controllers,– disk storage,– other devices (terminals, networks, tape drives, etc.).

What is an Operating System?


• There are two modes of CPU operations:

– kernel mode and

– user mode.

• Privileged instructions can be executed only in the kernel mode. Examples of privileged instructions: I/O instructions, instructions that access system registers such as memory mapping registers, etc.

• In principle, computer systems function such that the operating system is executed with CPU in a kernel mode, while user programs execute with CPU in user mode.

– Why?

– How?

Modes of CPU Operation


Layered Approach

Hardware

Operating System

User Programs(CPU in user mode)

(CPU in kernel mode)

Privileged instructions

Non-privileged

instructions

Systemcalls

System calls (or monitor calls) are means by which user programsrequire services of operating system.


• CPU mode bit added to computer hardware to indicate the current CPU mode: 0 (=kernel) or 1 (=user).

• When an interrupt occurs, CPU hardware switches to the kernel mode.

• Switching to user mode (from kernel mode) done by setting CPU mode bit (by an instruction).

Privileged instructions can be executed only in kernel mode.

kernel user

Exception/Interrupt/Fault

Set user mode

Dual-Mode of CPU Operation

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• Hardware Interrupts: Interrupt requests made via asserting signal on any of special external pins.

• Interrupt request lines – IRQ’s.• Usually used by I/O controllers to signal normal I/O completion

or a variety of error conditions. These interrupts also called I/Ointerrupts.

• Hardware interrupts can be masked by setting appropriate bits in some system register;

Interrupts Classes

2. Interrupts caused by external signals:• Reset: A signal asserted on the appropriate pin;

There are three classes of causes for an interrupt.

• Power failure• Memory parity error

1. Interrupts caused by hardware failure:


Interrupts by External Signals

Reset

IRQ 0

Timer

IRQ 1


3. Interrupts as result of instruction execution (these are also called

exceptions); There are two types of those interrupts:

Type A caused by problems during instruction execution:

– Address Error: a reference to a nonexistent or illegal memory

address;

– Reserved Instruction: An instruction with undefined opcode field or

a privileged instruction in User mode;

– Integer Overflow: An integer instruction results in a 2’s

complement overflow;

– Floating Point Error: e.g. divide by zero, overflow, and underflow;

Type B caused by special instructions (software interrupts):

– MIPS processors: Syscall instruction executed;

– Intel processors: INT n instruction executed;

Note: These instructions are used to implement system calls.

Interrupts Classes (continued)


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R eg is te rs

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A r ithm e t ic M ult ip lyd iv ide

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C op ro ce ss o r 1 (FP U )

R eg is ters

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R eg iste rs

Bad V A d d r

C op ro cess o r 0 ( tra ps a n d m e m ory)

S ta tu s

C a use

E P C

M em ory

Program Counter

Logic unit

Control

MIPS Processor

• MIPS processor will be used as an example to illustrate some hardware features relevant to (and required by) an operating system.

• MIPS processor is of RISC architecture.

9


MIPS CPU Modes and Address Spaces

The processor is in Kernel Mode when CPU mode bit in Status register is set to zero. The processor enters Kernel Mode at power-up, or as result of an interrupt. The processor leaves Kernel Mode and enters User Mode when CPU mode bit is set to one (by some instruction).

MIPS has two processor modes of operation:• Kernel Mode and• User Mode

Memory (logical) address space is divided in two ranges:• User address space

– addresses in the range [0 – 7FFFFFFF16]

• Kernel address space– addresses in the range [8000000016 – FFFFFFFF16]


With CPU in User Mode, the program in execution has access

only to the CPU and FPU registers, while when CPU operates

in Kernel Mode, the program has access to the full capabilities

of processor including CP0 registers.

MIPS Privilege Instructions

Examples of MIPS privileged instructions:• any instruction that accesses Kernel address space • all instructions that access any of CP0 registers, e.g. move

word from CPU register to CP0 register• any instruction that accesses registers (a port) of I/O

controllers (i.e. I/O instruction).

Again, privileged instructions can not be executed when the

processor is in User mode, i.e. they can be executed only when

the processor is in Kernel mode.


• When any of the interrupts previously listed occurs, hardware

should perform some predefined (by its ISA) tasks.

• Here we describe in some level of details how MIPS processor

processes interrupts.

• MIPS does hardware interrupt processing in three steps.

MIPS Interrupt Processing

Step 1. (Saving content of PC)

• EPC register gets a value equal to either:– the address of a faulty instruction if the instruction itself

caused problems (e.g. address error, reserved instruction) or

hardware malfunctioning detected (e.g. memory parity error), – the address of the next instructions which would have been

executed in all other cases, i.e. for interrupts caused by external signals or by those interrupt causing instructions.


MIPS Interrupt Processing (continued)

Step 2. (PC gets new value and interrupt cause code is saved)

Step 3. (Mode of CPU operation set to kernel mode)

• PC 8000018016

• CPU mode bit 0;

Thus, the next instruction is fetched from location 8000018016

• Cause register a code of the exception

Each interrup has its code, e.g.:– hardware interrupt = 0– illegal memory address (load/fatch or store) = 4 or 5– bus error (fetch or load/store)= 6 or 7 – syscall instruction execution = 8– illegal op-code, i.e. reserved or undefined op-code= 10– integer overflow = 12– any floating point exception = 15

10


• Hardware interrupt processing first saves the address of the

interrupted instruction. Many architectures use a system stack

(in memory) to save the address, while in MIPS architecture,

EPC register is used.

• Hardware interrupt processing then loads PC with the new

address. In many architectures, new content of PC comes from

one of special memory locations (interrupt vectors). In MIPS

architecture, PC always gets the value 8000018016.

• Finally, hardware interrupt processing sets CPU into kernel

mode.

Hardware Interrupt Processing in General


• During booting of operating system, interrupt handling routines

are loaded starting at the some memory locations. It is

responsibility of the operating system to also load interrupt

vectors with addresses of the interrupt handling routines.

• In MIPS architecture, the operating system code must starts at

memory address 8000018016, and then based on the content of

Cause register appropriate processing is performed.

• Hardware interrupt processing saves the address of the

interrupted instruction so the interrupted program (if needed)

may be later restarted at the point of interruption.

O.S. and Hardware Interrupt Processing


• Using system calls, a user program requests services of an operating system.

• Operating system also takes over if a user program encounters problems during instruction execution, e.g. illegal instruction.

• A hardware interrupt also causes that an appropriate operating system routine starts executing.

Transition from User Process to O.S. Code


• Must provide memory protection at least for the interrupt vector and the interrupt service routines. E.g. for this purpose, MIPS processor provides kernel and user memory address space, and operating system code is loaded in kernel address space, while user programs are loaded in user address space.

• But, it must also provide memory protection between user programs.

• In order to have that memory protection, one approach is to add two registers that determine the range of legal addresses a program may access:Base register – holds the smallest legal physical memory

address.Limit register – contains the size of the range

• Memory outside the defined range is protected.

Memory Protection

11


Instructions for loading into base and limit registers are privileged instructions.

Use of Base and Limit Registers


Hardware for Address Protection

This is one of the simplest methods used for memory protection.


• Timer has the following hardware characteristics:– Content of timer register is decremented every clock tick,– When timer reaches zero, a hardware interrupt occurs,– Load into the timer register is a privileged instruction.

• Operating system sets the appropriate value in the timer (clock) register before CPU starts execution of any user program. The value set should correspond to the maximum time the program can use CPU. This assures that the program can not monopolize CPU for infinite time, since a hardware interrupt from the timer (clock) is certain after the set time. When a hardware interrupt happens, CPU will cease execution of the program and start execution of the appropriate routine in the code of operating system.

CPU Protection and Timer


• Process Management:

– process creation and deletion,

– process suspension and resumption,

– provision of mechanisms for:

a. process synchronization,

b. process communication,

c. deadlock handling.

• Main Memory Management:

– keeping track of which parts of memory are currently being used and by whom,

– allocate and deallocate memory space as needed,

– deciding which processes to load when memory space becomes available.

Main Components of Operating System

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• File Management:– file creation and deletion,– directory creation and deletion,– support of primitives for manipulating files and directories,– mapping files onto secondary storage,– file backup on stable (nonvolatile) storage media.

• I/O System Management:– a buffer-caching system, – a general device-driver interface,– drivers for specific hardware devices.

• Mass-Storage (Secondary) Management:– free space management– storage allocation– disk (head) scheduling

Main Components of Operating System (cont.)


• Protection and Security System:

– Protection: a mechanism for controlling access by

programs, processes, or users to both system and user

resources; protection mechanisms must distinguish between

authorized and unauthorized usage, specify the controls to

be imposed and provide a means of enforcement.

– Security: defense of the system against internal and external

attacks; It includes: denial-of-service, worms, viruses,

identity theft, theft of services.

• Networking support

Main Components of Operating System (cont.)

introduction and basic hardware supportweb.cse.ohio-state.edu/~babic.1/a.4s.pdf · introduction and...

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