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INTRO TO VHDLAppendix A: page 779 - page 831

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VHDL is an IEEE and ANSI standard.

• VHDL stands for Very High Speed IC hardware description language.

• VHDL supports– A wide range of abstraction levels ranging from

abstract behavioral descriptions to very precise gate-level descriptions.

– Synchronous and asynchronous timing models.– Three different description styles: structural,

data-flow, and behavioral.

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• Documentation in VHDL Code– Two characters – denote the beginning of the comments– VHDL ignore any text on the line after –

• Data Objects– Names, values and numbers, Signal – SINGAL signal_name : type_name;

• Operators : Precedence• Design entity• Package• Using sub-circuits• Current assignments• Sequential assignments

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Three Basic Data objects in VHDL

• SIGNAL – the most important data objects, which represent

the logic signals (wires) in the circuit.

• CONSTANT• VARIABLE

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A.2 SIGNAL is the most important data object in VHDL

• A signal must be declared with a type as SIGNAL signal_name : type_name;

• 10 signal types:BIT, BIT_VECTOR,

STD_LOGIC, STD_LOGIC_VECTOR, STD_ULOGIC, SIGNED, UNSIGNED,

INTEGER,

ENUMERATION,

BOOLEAN.

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BIT and BIT_VECTOR

• Objects of BIT type can only have the values ‘0’ or ‘1’.

• An object of BIT_VECTOR type is a linear array of BIT objects.SIGNAL x1 : BIT;

SIGNAL C : BIT_VECTOR (1 TO 4);

SIGNAL Byte: BIT_VECTOR (7 DOWNTO 0);

C <= “1010”;

-- results in C(1) = 1, C(2) = 0, C(3) = 1, C(4) = 0

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STD_LOGIC and STD_LOGIC_VECTOR

• STD_LOGIC provides more flexibility than the BIT type. To use this type, must includeLIBRARY ieee;

USE ieee.std_logic_1164.all;

Legal values for a STD_LOGIC data objects:

0, 1, Z , -

Z – high impedance

‘-’ – ‘don’t care’

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A.3 VHDL Operators

• VHDL standard groups all operators into formal classes.– Operators in a given class have the same

precedence.– Operators of the same class are evaluated from left

to right.– Parenthesis should be used to ensure the correct

interpretation of the expression.– x1 AND x2 OR x3 AND x4

=

– (x1 AND x2) OR (x3 AND x4)

Table A.1. The VHDL operators.

10Figure A.1. The general structure of a VHDL design entity.

A.4 VHDL Design entity

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Figure 2.30. A simple logic function.

f

x3

x1x2

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Figure 2.31. VHDL entity declaration for the circuit in Figure 2.30.

ENTITY example1 IS PORT ( x1, x2, x3 : IN BIT ;

f : OUT BIT ) ; END example1;

/* declare signals In an entity declaration */

A4.1 Entity declaration describes the external view of the entity.

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A4.2 Architecture body contains the internal description of the entity.

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Figure 2.32. VHDL architecture for the entity in Figure 2.31.

ARCHITECTURE LogicFunc OF example1 IS BEGIN

f <= (x1 AND x2) OR (NOT x2 AND x3) ; END LogicFunc ;

/* A set of concurrent or sequential statements that represents the behavior of the entity. */

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Figure 2.33. Complete VHDL code for the circuit in Figure 2.30.

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ENTITY example2 IS

PORT(x1, x2, x3, x4 : IN BIT;

f, g : OUT BIT);

END example2;

ARCHITECTURE LogicFunc OF example2 IS

BEGIN

f <= (x1 AND x2) OR (x2 AND x4);

g <= (x1 OR (NOT x3)) AND ((NOT x2) OR x4);

END LogicFunc;

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ENTITY example2 IS

PORT(x1, x2, x3, x4 : IN BIT;

f, g : OUT BIT);

END example2;

ARCHITECTURE LogicFunc OF example2 IS

BEGIN

f <= (x1 AND x2) OR (x2 AND x4);

g <= (x1 OR (NOT x3)) AND ((NOT x2) OR x4);

END LogicFunc;

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ENTITY example2 IS

PORT(x1, x2, x3, x4 : IN BIT;

f, g : OUT BIT);

END example2;

ARCHITECTURE LogicFunc OF example2 IS

BEGIN

f <= (x1 AND x2) OR (x2 AND x4);

g <= (x1 OR (NOT x3)) AND ((NOT x2) OR x4);

END LogicFunc;

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A.6 Using sub-circuits

• An entity X, when used in another entity Y, is called component X.- A component is also an entity.

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w1

w2

w3

w4

g

h

B

x1

x2

x3

f

A

in1

in2

in3

in4

in5

out

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ENTITY part3 IS

PORT(in1, in2, in3, in4, in5 : IN BIT;

out : OUT BIT);

END part3;

ARCHITECTURE Structure OF part3 IS

COMPONENT A

PORT(x1, x2, x3 : IN BIT;

f : OUT BIT);

END COMPONENT;

COMPONENT B

PORT(w1, w2, w3, w4 : IN BIT;

g, h : OUT BIT);

END COMPONENT;

SINGAL g, h : BIT;

BEGIN

instB : B PORT MAP (in1, in2, in3, in4, g, h);

instA: A PORT MAP (g, in5, h, out);

END Structure;

Architecture body consists of a set of interconnected components that represents the structure of the entity.