international technology roadmap for...
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ITRS 2008 Update Preparation – July, San Francisco, USAWork in Progress – Do Not Publish
International Technology Roadmap for Semiconductors
2008 ITRS ORTC[7/14-16 ITRS Meetings San Francisco]
A.Allan, Rev 1 (for 7/16 Public Conference Prep)
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ITRS 2008 Update Preparation – July, San Francisco, USAWork in Progress – Do Not Publish
Agenda• Moore’s Law and More• Technology Pacing Trends Update
– Physical and Printed GL Focus• Summary
• Backup– Function Size, Moore’s Law on Track– Design On-Chip Frequency– SICAS Technology, Wafer Generation Demand Update– Definitions
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ITRS 2008 Update Preparation – July, San Francisco, USAWork in Progress – Do Not Publish
Moore’s Law & MoreMore than Moore: Diversification
Mor
e M
oore
: M
inia
turiz
atio
nM
ore
Moo
re:
Min
iatu
rizat
ion
Combining SoC and SiP: Higher Value SystemsBas
elin
e C
MO
S: C
PU, M
emor
y, L
ogic
BiochipsSensorsActuators
HVPowerAnalog/RF Passives
130nm
90nm
65nm
45nm
32nm
22nm...V
130nm
90nm
65nm
45nm
32nm
22nm...V
Information Processing
Digital contentSystem-on-chip
(SoC)
Interacting with people and environment
Non-digital contentSystem-in-package
(SiP)
Beyond CMOS
2008 ITRS Executive Summary Fig 5[updated for 2007]
Traditional ORTC Models
[Geo
met
rical
& E
quiv
alen
t sca
ling]
Scal
ing
(Mor
e M
oore
)Functional Diversification (More than Moore)
Continuing SoC and SiP: Higher Value Systems
HVPower Passives
[2008 –Update Definitions]
Facilitator:Mart Graef
Facilitator:Jim Hutchby
Facilitator:Alan Allan
SIP “White Paper”A&P TWG
Chair: Bill Bottomswww.itrs.net/papers.html
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ITRS 2008 Update Preparation – July, San Francisco, USAWork in Progress – Do Not Publish
2007 ITRS “Moore’s Law and More” Alternative Definition Graphic
Computing &Data Storage
Heterogeneous IntegrationSystem on Chip (SOC) and System In Package (SIP)
Sense, interact, Empower
BaselineCMOS Memory RF HV
PowerPassives Sensors,
ActuatorsBio-chips,Fluidics
“More Moore”
“More than Moore”
Source: ITRS, European Nanoelectronics Initiative Advisory Council (ENIAC)
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2008 ITRS “Beyond CMOS”
Computing and Data Storage Beyond CMOS
Source: Emerging Research Device Working Group
“More Moore” “Beyond CMOS”
22nm 16nm 11nm 8nm
BaselineCMOS
Ultimately Scaled CMOS
FunctionallyEnhanced CMOS
Spin LogicDevices
NanowireElectronics
FerromagneticLogic Devices
32nm
Channel Replacement Materials Low Dimensional Materials Channels
Multiple gate MOSFETs New State Variable
New Data RepresentationNew Devices
New Data ProcessingAlgorithms
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ITRS 2008 Update Preparation – July, San Francisco, USAWork in Progress – Do Not Publish
2007 - PIDS/FEP - Simplified Transistor Roadmap [Examples of “Equivalent Scaling” from ITRS PIDS/FEP TWGs] – Update in 2009
65nm 45nm 32nm 22nm
PDSOI FDSOI
bulk
stressors + substrateengineering
+ high µ materials
MuGFETMuCFET
elec
tros
tatic
con
trol
SiON
poly
high k
metal
gate stack
planar 3D
Source: ITRS, European Nanoelectronics Initiative Advisory Council (ENIAC)[ ITRS DRAM/MPU Timing: 2007[7.5] 2010 2013 2016 ]
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ITRS 2008 Update Preparation – July, San Francisco, USAWork in Progress – Do Not Publish
2007 Definition of the Half Pitch – 2008 unchanged[No single-product “node” designation; DRAM half-pitch still litho driver; however,
other product technology trends may be drivers on individual TWG tables]
Poly Pitch
Typical flash Un-contacted Poly
FLASH Poly Silicon ½ Pitch = Flash Poly Pitch/2
8-16 Lines
Metal Pitch
Typical DRAM/MPU/ASIC Metal Bit Line
DRAM ½ Pitch = DRAM Metal Pitch/2
MPU/ASIC M1 ½ Pitch = MPU/ASIC M1 Pitch/2
Source: 2005 ITRS - Exec. Summary Fig 2
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ITRS 2008 Update Preparation – July, San Francisco, USAWork in Progress – Do Not Publish
Production Ramp-up Model and Technology Cycle TimingVo
lum
e (P
arts
/Mon
th)
1K
10K
100K
Months0-24
1M
10M
100M
AlphaTool
12 24-12
Development Production
BetaTool
ProductionTool
First Conf.
Papers
First Two CompaniesReaching
Production Volu
me
(Waf
ers/
Mon
th)
2
20
200
2K
20K
200K
Source: 2005 ITRS - Exec. Summary Fig 3
Fig 3 2008 - Unchanged
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ITRS 2008 Update Preparation – July, San Francisco, USAWork in Progress – Do Not Publish
2007 ITRS Product Technology Trends - Half-Pitch, Gate-Length
1.0
10.0
100.0
1000.0
1995 2000 2005 2010 2015 2020 2025
Year of Production
Prod
uct H
alf-P
itch,
Gat
e-Le
ngth
(nm
)
DRAM M1 1/2 Pitch
MPU M1 1/2 Pitch(2.5-year cycle)
Flash Poly 1/2 Pitch
MPU Gate Length -Printed
MPUGate Length -Physical
MPU M1.71X/2.5YR
Nanotechnology (<100nm) Era Begins -1999
GLpr IS =1.6818 x GLph
2007 - 2022 ITRS Range
MPU & DRAM M1& Flash Poly
.71X/3YR
Flash Poly.71X/2YR
Gate Length.71X/3YR
Before 1998.71X/3YR
After 1998.71X/2YR
[WAS]
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ITRS 2008 Update Preparation – July, San Francisco, USAWork in Progress – Do Not Publish
2008 ITRS Update - Technology Trends vs Actuals and Survey
10
100
1000
2000 2005 2010 2015 2020 2025
Year
nano
met
ers
(1e-
9)Jeff Butterbaugh/FEPGLphys Actuals(leading):
Kwok Ng/PIDSGLphys Survey(leading):
Glpr(nm) MPU (ITRS05-07)
Glph(nm) MPU (ITRS05-07)
M1 Half Pitch(nm)MPU (ITRS 05-07)
M1 Half Pitch(nm)DRAM (ITRS 05-07)
Poly Half Pitch(nm)Flash (ITRS 07)
GLph Proposal 2008Update
Work in Progress - Do Not Publish!
Work in Progress - Do Not Publish!
[also DRAM M1 in2008 Update]
2007/08 ITRS: 2007-2022
GLprinted =[decreasingEtch ratio]
GLphysical =~0.71x/ 3.8yrs
3-yearCycle
[.5^(1/6yrs)]
2.5-yearCycle
[.5^(1/5yrs)]
"More Moore"Functional
DensityComplemente
dby "Equivalent
Scaling"Performance/
Power Mgt[Copper IC;Strain Si;
Metal Gate/Hi-K;
UTB/FDSOI;MUG; etc.]
[Litho Driver after2007 ]
Printed GL =Physical GLAfter 2019
2008Update
2008Update
“10nm” 5yrGLph delay
“20nm” 3yrGLph delay
“32nm” 2yrGLph delay
“45nm” 1yrGLph delay
• GLphysical 2008 Update IS: 3.8yr cycle after 2007; enabled by “Equiv. Scaling”• FEP and PIDS have proposed shifted/interpolated tables; full model redo in ‘09• GLprinted parallel to MPU/DRAM M1 Half-Pitch; shrinking etch ratio to GLphy
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ITRS 2008 Update Preparation – July, San Francisco, USAWork in Progress – Do Not Publish
ORTC Summary – 2008 Update Status• Flash Model un-contacted poly half-pitch trend
– Unchanged 2-year cycle* through 2008/45nm, then 3-year cycle* (2014/22.5; 2020/11.25); ;– Unchanged: Cell Design Factor; Array Efficiency; Bits/Chip– PIDS Flash Survey Team to report status of survey data update and proposals in July meetings.
• DRAM Model stagger-contacted M1 half-pitch updated to the MPU 2.5-year cycle* through 2010/45nm [affects 2007, 2008, 2009], then
– Unchanged 3-year cycle* beginning 2010/45nm (2016/22.5; 2022/11.25); – Unchanged: Cell Design Factor; Array Efficiency; Bits/Chip
• DRAM function size, function density, and chip size models have been updated to latest Product 2.5-year cycle scaling rate;
– Only 2007-2009 years affected in 2008 Table Update. – Unchanged 2010-2022
• MPU Model M1 stagger-contact half-pitch unchanged from 2007– 2.5-year cycle* through 2010/45nm, then 3-year cycle* (2016/22.5; 2022/11.25).
• MPU/ASIC Printed Gate Length Updated– 1.6818 Etch Ratio in 2007;– Then variable Gpr/Gphy Etch Ratio (parallel to DRAM/MPU M1 Contacted Half Pitch) ‘07-’22.
• MPU/ASIC High-Performance Physical Gate Length– 3.8-year cycle* beginning 2007 Performance and Power needs manage. – FEP and Litho TWGs have agreed on new annual variable GLprinted/GLphysical ratio targets– Slower On-Chip Frequency trend (8% trend) was set by Design TWG in 2007 ITRS ORTC) - need
updated transistor and design model alignment by PIDS, FEP, and Design – 2009 Renewal.– New drivers will be Ion/Width, CV/I – possibly add to ORTC - 2009 Renewal ORTC line items.
* ITRS Cycle definition = time to .5x linear scaling every two cycle periods]
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ITRS 2008 Update Preparation – July, San Francisco, USAWork in Progress – Do Not Publish
ORTC Summary – 2008 Update Status (cont.)• MPU/ASIC Low Operating Power Printed Gate Length
– TBD• MPU/ASIC Low Standby Power Physical Gate Length [add to ORTC 1a,b]
– No Change 2007, 2008; two-year delay 2009-2011 from High Performance; one-year delay in 2012; and no delay 2013-2022.
• New 2008 “Moore’s Law and More” Working Groups and Definitions Work : – “More Moore” (“Moore’s Law;” typically digital computing) Functional and Performance scaling is
enabled by both “Geometrical” and also “Equivalent” scaling technologies; Design “Equivalent Scaling” to be added in 2008
– More than Moore “Functional diversification” text will be impacted (typically non-digital sensing, interacting) system board-level migration/miniaturization is enabled by system-in-package and system-on-chip
– “Beyond CMOS” definition will be added, focused on the Computing and Storage Logic Switch transition and consensus options at “Ultimately Scaled CMOS”
• The average of the industry product “Moore’s Law” (2x functions/chip per 2 years) rate forecast to continue throughout the latest 2007-2022 ITRS timeframe
• Total MOS Capacity (SICAS) growing at >16% CAGR (SICAS); new “<80nm” data split out; and 300mm Capacity Demand has ramped to over 40% of Total MOS
• Industry Technology Capacity Demand (SICAS) – 1Q08 published status] continues on a on 2-year cycle* rate at the leading edge.
* ITRS Cycle definition = time to .5x linear scaling every two cycle periods]
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ITRS 2008 Update Preparation – July, San Francisco, USAWork in Progress – Do Not Publish
Backup
• Function Size; Moore’s Law on track• Design Frequency (2007)• SICAS Update (1Q08 data)• Definitions
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ITRS 2008 Update Preparation – July, San Francisco, USAWork in Progress – Do Not Publish
2007 ITRS Product Function Size Trends - Cell Size, Logic Gate(4t) Size
1.E-04
1.E-03
1.E-02
1.E-01
1.E+00
1.E+01
2000 2005 2010 2015 2020 2025
Year of Production
Cel
l, Lo
gic
Gat
e Si
ze(u
m2
)
DRAM Cell Size (u2)
MPU SRAM Cell Size(6t)(u2)
MPU Gate Size(4t)(u2)
Flash Cell Size (u2)SLC
Flash Eqv.bit Size(u2)2bit MLC
Flash Eqv.bit Size(u2)4bit MLC - New
Figure 9[’07] ITRS Product Function Size 2008 Update:[NO CHANGE to MPU and Flash;Small change ’07-’09 to DRAM]
Flash: 4f2 LastDesign Physical AreaFactor Improvement
DRAM: 6f2 is lastDesign Area
Factor Improvement
Logic Gate: NODesign Area
Factor Improvement(Only Scaling)
SRAM: gradualDesign Area
Factor Improvement
Flash: (MLC @ 2 bits/cell =2f2 Equivalent Area Factor)
Flash 4 bits/cell1f2 Beginning 2010
(@ 2 MLC bits/physical cell area)
(@ 4 MLC bits/physical cell area)
DRAM 6f2Pull-in to ‘06
Flash cell areaReduced due to
2YR cycleExtension
2007 - 2022 ITRS Range
Past Future
DRAM - SmallAdjustments
In 2008
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ITRS 2008 Update Preparation – July, San Francisco, USAWork in Progress – Do Not Publish
Figure 10 ITRS Product Functions per Chip
Average Industry"Moores Law“ :
2x Functions/chip Per 2 Years
2007 ITRS Product Technology Trends - Functions per Chip
1.E-02
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
1995 2000 2005 2010 2015 2020 2025
Year of Production
Prod
uct F
unct
ions
/Chi
p[ G
iga
(10^
9) -
bits
, tra
nsis
tors
]
Flash Bits/Chip (Gbits)Multi-Level-Cell (4bitMLC)
Flash Bits/Chip (Gbits)Multi-Level-Cell (2bitMLC)
Flash Bits/Chip (Gbits)Single-Level-Cell (SLC )
DRAM Bits/Chip (Gbits)
MPU GTransistors/Chip- high-performance (hp)
MPU GTransistors/Chip- cost-performanc (cp)
2007 - 2022 ITRS Range
Past Future
DRAM Bits/chip
1-yearDelay;
Flash MLC 4 bits/chip
Added
Flash SLCBits/chip
for 1-year Pull-in
[Unchanged for 2008]
Moore’s LawOn
Track!
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ITRS 2008 Update Preparation – July, San Francisco, USAWork in Progress – Do Not Publish
Past Future
2007 - 2022 ITRS Range
Actual History vs ITRS
On-Chip?
2022~14.3Ghz
2007~4.7Ghz
~ 8%CAGR
~ 21%CAGR
New Design TWG2007 ITRS Final “IS”
Ave 8% CAGR
New Design TWG2007 ITRS Frequency
Historical Data vs 2005 ITRSAnd Proposed* Trend Ave ~8% CAGR
* Source: Various, per ITRS Design TWG ca August 2007
2005/06 ITRS
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D esign M ax O n-C hip C lock Frequency
1.0
10.0
100.0
1995 2000 2005 2010 2015 2020 2025
Year
(Ghz
)
D esignM ax.Freq.2001 ITR S
D esignM ax.Freq.2003ITR S
Extrapo la tion /In terpo la tion o f2005W A SITR SProposa l
F ina l M axO n-C hipLoca l C lockFreq(Aug'07)
Including 2005 ITR S and F inal (Aug'07) 2007 D esign TW G
1.17x/year (2x/4 .5yrs)
1 .29x/year (2x/2 .5yrs)
"G ap" D e layed by 3 years
in 2005 ITR S
1.41x/year (2x/2yrs)
IS : Design/A rchitecture: reduction of m axim um # 0f inverter de lays to fla t a t 12 beg inning 2007 W AS: (2001 ITR S: fla t a t 16 a fter 2006)
W AS/IS
P ast <-----> Future
2007 Des TWG Actual History of Average On-Chip
~ 21% CAGR
Gamers“Clock-Doubling?”
New Design TWG2007 ITRS Final “IS”
Ave 8% CAGR
2005/06ITRS
“WAS”
2007 - 2022 ITRS Range
Performance and Power ManagementEnabled by “Equivalent Scaling”
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2007 “Fig 4” Technology Cycle Timing Compared to Actual Wafer Production Technology Capacity Distribution
2010
W.P.C.= Total Worldwide Wafer Production Capacity* Sources:SICAS
0.01
0.1
1
10
200420032002
W.P.C
1997
W.P.C
1998
W.P.C
1999
W.P.C
2000
W.P.C
2001
W.P.C W.P.C
2005 2006 2007
W.P.C W.P.C W.P.C W.P.C
>0.7μm
0.7-0.4μm
0.4-0.3μm
0.3- 0.2μm
0.2- 0.16μm
<0.12μm
0.16-.12μm
Feat
ure
Siz
e (H
alf P
itch)
(μm
)
Year1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007
W.P.C = Total Worldwide Wafer Production Capacity; Source: SICAS*
- - - -
2-Year Cycle 3-Yr Cycle3-Year Cycle
= 2005/06 ITRS DRAM Contacted M1 Half-Pitch Actual= 2007 ITRS DRAM Contacted M1 Half-Pitch Target= 2007 ITRS Flash Uncontacted Poly Half Pitch Target
2007 ITRSMPU/ASIC
(2.5-yr Cycle)
SIA/SICAS Data**: 1-yr
delay from ITRS Cycle
Timingto >20% of MOS IC Capacity
[UpdatedThrough
2Q07]
** Source: The data for the graphical analysis were supplied by the Semiconductor Industry Association (SIA) from their Semiconductor Industry Capacity Statistics (SICAS). The SICAS data is collected from worldwide semiconductor manufacturers (estimated >90% of Total MOS Capacity) and published by the Semiconductor Industry Association (SIA), as of August, 2007. The detailed data are available to the public online at the SIA website, http://www.sia- online.org/pre_stat.cfm .
Note: The wafer production capacity data are plotted from the Semiconductor Industry Association (SIA) Semiconductor Industry CapacityStatistics (SICAS) 4Q data for each year, except 2Q data for 2007.The width of each of the production capacity bar corresponds to the MOS IC production start silicon area for that rangeof the feature size (y-axis). Data are based upon capacity if fully utilized.
127nm
180nm
255nm
360nm
510nm
720nm
90nm
ITRSTechnology
Cycle
Note: Includes<80nm split-out (ITRS 65nm) to be addedIn the 2008ITRS Upcate
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ITRS 2008 Update Preparation – July, San Francisco, USAWork in Progress – Do Not Publish
MOS Capacity by Dimensions
0%10%20%30%40%50%60%70%80%90%
100%
2Q05
3Q05
4Q05
1Q06
2Q06
3Q06
4Q06
1Q07
2Q07
3Q07
4Q07
1Q08
WSp
W x
1000
>=0.7µ
<0.7µ >=0.4µ
<0.4µ >=0.3µ
<0.3µ >=0.2µ
<0.2µ >=0.16µ
<0.16µ >=0.12µ
<0.12µ
<0.12µ >=0.08µ
<0.08µ
~33% ~33%
~0.7x2yr Cycle
SICAS 1Q08 Update (www.sia-online.org )
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ITRS 2008 Update Preparation – July, San Francisco, USAWork in Progress – Do Not Publish
SICAS 1Q08 Update (www.sia-online.org )MOS Capacity by Wafer-size
0%10%20%30%40%50%60%70%80%90%
100%
2Q05
3Q05
4Q05
1Q06
2Q06
3Q06
4Q06
1Q07
2Q07
3Q07
4Q07
1Q08
WS
pW x
1000
(8 in
ch e
quiv
alen
ts)
< 200m
200mm
300mm
~16Bcm2/41%
~39Bcm2
~18Bcm2/46%
~5Bcm2/14%
~6Bcm2/22%
~27Bcm2
~17Bcm2/62%
~4Bcm2/16%
>16% CAGR
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ITRS 2008 Update Preparation – July, San Francisco, USAWork in Progress – Do Not Publish
1. Scaling (“More Moore”)a. Geometrical (constant field) Scaling refers to the continued shrinking of
horizontal and vertical physical feature sizes of the on-chip logic and memory storage functions in order to improve density (cost per function reduction) and performance (speed, power) and reliability values to the applications and end customers.
b. Equivalent Scaling which occurs in conjunction with, and also enables, continued Geometrical Scaling, refers to 3-dimensional device structure (“Design Factor”) Improvements plus other non-geometrical process techniques and new materials that affect the electrical performance of the chip.
2. Functional Diversification (“More than Moore”)Functional Diversification refers to the incorporation into devices of functionalities that do not necessarily scale according to "Moore's Law," but provide additional value to the end customer in different ways. The "More- than-Moore" approach typically allows for the non-digital functionalities (e.g. RF communication, power control, passive components, sensors, actuators) to migrate from the system board-level into a particular package-level (SiP) or chip-level (SoC) potential solution.
2007 ITRS Definitions: “More Moore” and “More than Moore”
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Design TWG Proposed “More Moore” and “MtM” Text, 3 Apr 2008 Plenary v2a [discussion leader – Andrew Kahng] – Proposal accepted at Koenigswinter.• 1 = More Moore
– 1a = geometric scaling– 1b = equivalent scaling– 1c = Design equivalent scaling– NEED: quantifiable, specific Design Technologies that deal with More Moore– “Design equivalent scaling occurs in conjunction with Equivalent Scaling and continued
Geometric Scaling, and refers to design technologies that enable high performance, low power, high reliability, low cost, and high design productivity.”
– “Examples (not exhaustive) are: Design for variability; low power design (sleep modes, hibernation, clock gating, multi-VDD, ...); and homogeneous and heterogeneous multicore SOC architectures.”
– Request: Please remove “b) Multi-core MPU architecture” from 2 (MTM Functional Diversification)
• 2 = More than Moore– NEED: Design technologies to enable functional diversification– “Design technologies enable new functionality that takes advantage of More than Moore
technologies.”– “Examples (not exhaustive) are: Heterogeneous system partitioning and simulation; software;
analog and mixed signal design technologies for sensors and actuators; and new methods and tools for co-design and co-simulation of SIP, MEMS, and biotechnology.”
More than Moore Study Group 4/3/08
ORTC Summary – 2008 Update Status
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“Beyond CMOS” Definition
“Beyond CMOS” refers to emerging research devices, focused on a “new switch*” used to process information, typically exploiting a new state variable to provide functional scaling substantially beyond that attainable by ultimately scaled CMOS. Substantial scaling beyond CMOS is defined in terms of functional density, increased performance, dramatically reduced power, etc.
*The “New Switch” refers to an “information processing element or technology”, which is associated with compatible storage or memory and interconnect functions.
Examples of Beyond CMOS include: carbon-based nano- electronics, spin-based devices, ferromagnetic logic, atomic switch, NEMS switches, etc.