Intermolecular High-Productivity CombinatorialR&D Pl tf M t i l I t f & D iIntermolecular High-Productivity CombinatorialR&D Pl tf M t i l I t f & D i

Intermolecular Confidential

R&D Platform – Materials, Interfaces & Devices May 2014

R&D Platform – Materials, Interfaces & Devices May 2014

Intermolecular Corporate Overview

$80 Silicon Valley, CA-based R&D

company with ~200 employeesAnnual Revenue in $MM

$60

$70

y y

High Productivity Combinatorial (HPC™) platforms to accelerate R&D much faster for materials co

nduc

tor

ners

hips

$40

$50

R&D – much faster for materials and integrated devices

Collaborative development

Sem

icPa

rtn

play

SSBattery

$20

$30

pprograms in semiconductor, clean energy, and display applications

IP generation with preferred rights

DISPLAY

Ener

gy &

Dis

Part

ners

hips

$0

$10

2004 2005 2006 2007 2008 2009 2010 2011 2012 2013

IP generation with preferred rights for our customers

1230+ US patents and applications

Cle

an P

2

2004 2005 2006 2007 2008 2009 2010 2011 2012 2013p pp

Publicly disclosed customers only shown

Addressing Large and Growing Markets

Clean Energy

2013+ Battery$26B

SAM of combined Semiconductor and Clean Energy markets has thepotential to grow at a 20%-plus CAGR

Solar PV$78B

LED$17B

Display$124B$811B Many of these segments are

highly concentrated, with the top 5 comprising >80%

Solar PV$78B $349BSemiconductor

Adv Glass, Solar PV LED, TFT DisplayAdv Battery

Other Semi

$141B

Flat Glass$76B

Flat Glass$76B

NAND$26B

$78B $349B2013+

NAND$38B

MCU$20B

NOR$4B

Logic $141B

DRAM$28B

2012 2016 Logic DRAM NVM

MCU, NOR, eNVM, Image Sensor MEMS

Logic $172B

DRAM$35B

$38B

3

Logic, DRAM, NVM Image Sensor, MEMS

Source: IHS iSuppli, Freedonia, Frost, Wall Street Research, SanDisk Investor Day 2013

Increasing Semiconductor Device Complexity

New Materials and Device Architectures…

1

H2

He1980s

… Drive Performance Improvements

P t f P f I11 elementsH

19

K

3

Li

11

Na

He

4

Be5

B7

N6

C8

O9

F10

Ne

20

C21

S22

Ti23

V25

M24

C27

C26

F28

Ni29

C31

G30

Z33

A32

G34

S35

B36

K

12

Mg13

Al15

P14

Si16

S17

Cl18

Ar

1980s

1990s

2000s Gain by Materials & Device Architecture Innovation

Gain by Traditional Scaling

Percentage of Performance Increase11 elements

15 elements

61 elements

111

37

Rb

K

55

Cs

87

Ca Sc Ti V MnCr CoFe Ni Cu GaZn AsGe Se Br Kr

38

Sr39

Y40

Zr41

Nb43

Tc42

Mo45

Rh44

Ru46

Pd47

Ag49

In48

Cd51

Sb50

Sn52

Te53

I54

Xe

88 89

56

Ba57

La72

Hf73

Ta75

Re74

W77

Ir76

Os78

Pt79

Au81

Tl80

Hg83

Bi82

Pb84

Po85

At

104 105 106 107 108 109 110

86

Rn

RgFr Ra Ac

58

Ce59

Pr61

Pm60

Nd63

Eu62

Sm64

Gd65

Tb67

Ho66

Dy69

Tm68

Er70

Yb71

Lu

90

Th91

Pa93

Np92

U95

Am94

Pu96

Cm97

Bk99

Es98

Cf101

Md100

Fm102

No103

Lr

Rf Db Sg Bh Hs Mt Ds

Pre 2000sPlanar

Post 2000s3D

180nm 130nm 90nm 65nm 45nm 32nm 22nm

1999 2003 2005 2007 20092001 2011

4

Source: Intel, SanDisk, Intermolecular Source: IBM Microelectronics, Intel, IC Insights

New Materials Drive Semi Innovation / R&D Cost

Process R&D Costs* Semiconductor R&D Spending

$B % of rev 25%$100 $1.4 $B$B % of rev

20%

25%

$80

$100

$1 0

$1.2

3-yr CAGR48%

$B

15%$60

R&D$0.8

$1.0 48%

5%

10%

$20

$40

$0.4

$0.6 3-yr CAGR34%

0%$0

1978

1980

1982

1984

1986

1988

1990

1992

1994

1996

1998

2000

2002

2004

2006

2008

2010

2012

2014

2016 $0.0

$0.2

m m m m m m

5

Note: % of revenue represents the aggregate R&D spend as a % of aggregate semiconductor industry revenueSource: Gartner, IC Insights, IHS iSuppli

1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2

130n

m

90nm

65nm

45nm

32nm

22nm

* GLOBALFOUNDRIES, Common Platform Conference 2012

Accelerating Innovation and Time-To-Market

Purpose-Built for Manufacturing

Conventional

Purpose-Built for R&D (PME)

One 10 to 100Processes per Wafer

~15-20

2-5+ years

1000s

6-12 months

Learning Cycles per Year

Time to Solution

Higher

Higher

Sl

Lower

Lower

F t

R&D Costs

Technology Risk

Ti t M k t

6

Slower FasterTime to Market

Our Proprietary Platform For Innovation

*HPC™ A t t dA t t d

Experimentation =Process + Characterization + Analysis

*HPC™Processing

AutomatedAnalysis

Automated Characterization

ApplicationsOptimized Production S l tiSolutions

IntellectualProperty

GenerationGeneration

Intermolecular Informatics InfrastructureData Management & Analysis

Rapid Integrated andHigh Speed and

7

Rapid and Parallel

Integrated and Automated

High-Speed and Site Isolated

* High Productivity Combinatorial

R&D 100 Award

HPC™ Workflows for Accelerated Materials Innovation and Device Optimization

Wet Processing 18-192 Processes / waferTempus F20/F30

Workflow MgrDOE / Recipe Mgr

Informatics

rms

teriz

atio

n

enin

g

>>4 Processes / waferTempus CVD Collaboration MgrReporting EngineAnalysis Engine

Co-location Mgr

Data Load / Archive

PCTM

) Pla

tfor

hput

Cha

ract

ytic

s, &

Scr

e

~100 Processes /waferTempus PVDbina

toria

l (H

P

Hig

h Th

roug

gem

ent,

Ana

l

p

uctiv

ity C

omb

Proc

essi

ng &

Dat

a M

anag

>>4 Processes /waferTempus ALD

Hig

h P

rod

PC

Dev

ice

P

Info

rmat

ics:

Optimized

8

Dry Processing: PVD, ALD, CVD, Surface TreatmentH

Optimized Device Solutions

HPC™ Dry R&D Platform: ALD / CVD / PVD / ST*

Tempus™ AP-30

Intermolecular Tempus AP-30 300mm HPC platform for

advanced materials engineering, ad a ced a e a s e g ee g,process development, device

integration & scale-up

Tempus P-30 Tempus A-30

* Surface Treatment (remote and direct plasma )

Intermolecular Informatics: Tempus S80

Analysis and ReportingIntegration Screening and 300mm Scale-up

Materials and Process Screening

DOEs and Test Chips Metrology and E-Test

WCu

WDE

WCuWCu

WDEWDE

Intermolecular Informatics InfrastructureTempus S-80 and Data Warehouse

Automated HVM process HPC process Process and Test recipe file analysis

Reporting

Data archiving

Collaboration

equipment

DOE integration recipe manager

Process data

equipment OS

DOE - library generation

Process data

integration DOEs

Chemical library design

Test chip config.

manager

E-test algorithm generator

Collaboration managerlogginglogging

p gand wafer tracking

Data loaders

World Class Technical Team

Ph.DsComposition of R&D Team

Chemistry

Materials Science Defect DetectionProcess Technologies

Process Equipment41%

29%30%

Physics EngineeringProcess, Equipment,

Integration

Wet ProcessingDesign, Qualification,

Manufacturing Systems Engineering

Deposition

L A liAdvanced Interconnect Test Structures

29%30%

MastersBachelors

Laser Annealing Solar Cells Electrical Test

Equipment Development LED Statistical Methods

Advanced Packaging Yield Management

Modeling / TCADModeling / TCAD

70% of total employees dedicated to R&D Multi-disciplinary expertise**

~150 IMI Engineers

11

** Former employers of certain members of Intermolecular’s technical team

Intermolecular ALD/PVD/CVD/Surface TreatmentDevelopment Program Applications

Surface Treatment

HPC ALD –Oxides

Degas

Applications: Non-Volatile Memory

— ReRAM / 3D ReRAM / Select Device

Applications: Non-Volatile Memory

— ReRAM / 3D ReRAM / Select Device

P1

P2P3

P4

P5

Degas ReRAM / 3D ReRAM / Select Device— 3D NAND— Phase Change Memory; SSTRAM

DRAM Capacitor (High-k / Low Leakage)

ReRAM / 3D ReRAM / Select Device— 3D NAND— Phase Change Memory; SSTRAM

DRAM Capacitor (High-k / Low Leakage)P1 P5

HPC ALD-Metals

HPC PVD

— High-k Dielectrics & Non-noble Electrodes

Advanced Logic— Advanced Transistor (HKMG / FinFET / III-V)

ALD Conformal Doping

— High-k Dielectrics & Non-noble Electrodes

Advanced Logic— Advanced Transistor (HKMG / FinFET / III-V)

ALD Conformal Doping

Tempus AP-30

TertiaryPrimary (PVD) Secondary (ALD/PVD)

— ALD Conformal Doping — Advanced Contact— High-Reliability, Low RC Product Interconnect

— ALD Conformal Doping — Advanced Contact— High-Reliability, Low RC Product Interconnect

TertiaryPrimary (PVD)

Pad oxide

mm to u Scale

Secondary (ALD/PVD)

Padoxide Diode

R/W Cell

nm Scale

oxideInterconnect oxideInterconnect

DRAM Capacitor Collaboration Example

High K Dielectric OptimizationDopant MaterialDoping Concentration

Top Electrode EngineeringWork-functionCompositionStability, Resistivity, PhaseIntegration

Electrode

p gDoping schemeAnneal treatmentAnneal ambient

Current Blocking Layer

Integration

ElectrodeI t f E i i

High K Dielectric 1

High K Dielectric 2

Materials, Process & Film integration for:• High K Optimization• Leakage Optimization

1e-3

1e-2

1e-1

1e+0

1e+1

0255075100125

Temperature(C)

1e-3

1e-2

1e-1

1e+0

1e+1

0255075100125

Temperature(C)

ElectrodeInterface EngineeringIn-situ annealPlasma treatmentHigh WF interlayer

1e-9

1e-8

1e-7

1e-6

1e-5

1e-4

-2 -1 0 1 2Voltage (V)

125

1e-9

1e-8

1e-7

1e-6

1e-5

1e-4

-2 -1 0 1 2Voltage (V)

125

Bottom Electrode EngineeringWork-functionCompositionStability, Resistivity, PhaseIntegration Mechanism Understanding:

Temperature dependent leakageDefect modeling, Reliability

Workflows for Primary, Secondary & Tertiary Screening of DRAM Capacitor Stacks using HPC

Screening/Development Stages:Primary screening using 2D MIM Cap:

Experiments/ month

2D MIM Cap:

Primary screening using 2D MIM Cap:• (ALD) Unit Process Development, I-V/C-V

• Advanced Characterization (Vbd, CVS)• I-V (Temp), Dielectric Relaxation

Secondary screening using 3D:

300-400

IMI O l C it 3D TEG

SiO2

Si Substrate

BECHigh-K

Secondary screening using 3D:• Overlap Capacitor (for ALD TEC)

• 3D Step Coverage, TEG

Tertiary screening: DRAM f ll l

> 100

> 1 – 2 lots/mo

IMI Overlap Capacitor, 3D TEG:

DRAM full-loop

ProductQual & HVM

Ramp

> 1 – 2 lots/mo

DRAM Full loop:

Ramp

HPC workflows have enabled rapid qualification of new DRAM capacitors for Elpida/ Micron with unprecedented efficiency

IMI Physical Characterization Resources

NVM StackCharacterization

Unit film characterization

XPSChemical

Composition

XRD

SEMFailure

Analysis

TEM*XRDCrystallinityand Phase

XRRDensity,

Thickness

Stack/interface imaging

EELS*Composition nanoprobe

*Available in collaboration with external vendors

Materials Characterization

Thickness

XRFElemental

identification

EDS/A

nanoprobe

SIMS*Stack/interface depth profiling

Deep UVOptical constants

EDS/AugerElemental identification

SEM/OpticalImaging for BS

l

Reinsertion

AFMSurface

Roughness

(n&k)

SP1Particle Maps

clean

Intermolecular Confidential 1515

e se oMetrologyConductive AFM*

Localized conduction map

ICPMSMetal

Contamination

*New in 2014

DRAM Capacitor Development & Characterization Stages

Method Description Output

Materials screening ALD unit process optimization and integration Saturation and growth curves, physical and electrical characterization

Level

I-V, C-V Measure I-V and C-V at room temperature Leakage density, EOT; J vs EOT trend

I-V (T) Measure I-V at different temperatures Activation Energy (current conduction mechanism)

V IV sweep (until breakdown occurs) Break down voltage

1Level

2

VBD IV sweep (until breakdown occurs) Break down voltage

Vstress Apply constant voltage stress, monitor current till breakdown, record breakdown time (TBD)

Type of breakdown (hard, soft, progressive…),

Vstress vs. TBD

Vstress + IVCurrent with stress voltage

and stress timeLevel

Relaxation current I = I0*tn

l 3

ImpedanceSpectroscopy

Frequency domain dielectric characteristics

DRAM Capacitor Development MethodologyEnabling Disruptive Time-to-Market Advantage

HPC MIM Capacitor R&D Workflow (High-k & Electrode)Objective: Cap Materials, Processes, Integration, StructureLearning Cycles: ~ 4 Hours

Intermolecular Informatics InfrastructureData Management & Analysis

HPC Processing

AutomatedAnalysis

Automated Characterization

Learning Cycles: ~ 4 Hours

HPC Full Wafer Short Loops (Fab IMI Fab)

Objecti e 3D Cap Integration Optimi ation Man fact rabilit Yield

feedback300-400 COL / Monthg y

Objective: 3D Cap Integration, Optimization, Manufacturability, YieldLearning Cycles: Short Cycle ≤ 3x nm 3D TEG: ~ 2-3 weeks

HVM T l S l (Hi h k & El t d )

feedback

HVM Tool Scale-up – (High-k & Electrode)

Objective: HVM Batch Tool Qual, Manufacturability, Productivity & COOLearning Cycles: Parallelization of HVM Tool Configuration,

Process Optimization and Unit Process Qualification feedback

HVM Fab Process Qualification

Objective: Process Integration Optimization, DRAM Product Qualificationj g p ,Learning Cycles: Parallelization of HPC DRAM Capacitor Development

with HVM Fab DRAM Product Integration and Yield Ramp

HPC Test Vehicle Correlation to 3D TEG Results- Capacitor High-k Dielectric Stack and Electrode Scaling

HPC Test Vehicle (2D MIM Cap) Micron/Elpida 3D Test Chip (HPC & HVM)

IMI HPC Planar MIM Capacitor (A30) IMI 3D (A30 single wafer ALD in Full Wafer Re insertion mode) IMI 3D (A30 single wafer ALD in Full Wafer Re-insertion mode) Micron/Elpida 3D Test Chip (Volume manufacturing ALD tool)

HPC Pl t Si l W f 3D t HVM 3D TEG C l tiHPC Planar to Single Wafer 3D to HVM 3D TEG Correlation

Integrating Computational Modeling & Experimentation

Identified Candidates

Production Solution

Ab-initio;

Simulation• Band structure/offsets• Defects• Electronic transport• Interfaces

HPC Workflow ProductionProduction

Electrical, DeviceParameters

Collaborative Development

• Process modulesIntegration

ModelingPh

HVM Process

High VolumeManufacturing

• Integration• Characterization• E-test data• Automated Analysis

• Phases• Phase equilibrium• Diffusion• Transformations

Experimental Data

HVM Process & Device

Information

Phenomenological Modeling Based Upon Experimental Data & Simulation

Micron / IMI DRAM Collaboration

Value of Accelerating Time-to-Market

(30nm DRAM Example)

Node (nm)

50 >18 Months>18 Months

x

1,135 additional chips/wafer

93% yield

/Engage

40 66MonthsMonths

x

y

205K wafers/month55

MonthsMonths30

x

=

$2/chip25A

25B

$433M/month

Potential to Create $100s of Potential to Create $100s of 20*

millions of incremental revenue millions of incremental revenue per product generationper product generation

1x

IMI Collaboration Benefits

Increased R&D Productivity for Materials, Interfaces & Devices─ High-Value Semiconductor, Display and Clean Energy Applicationsg p y gy pp─ HPC Platform & Methods Increase Learning Cycles 10-100X

Accelerated TTM, TTY and Reduce Technical Risk

Technology Differentiation & Leadership

Collaborative R&D Model─ HPC Workflows Customized for Product Applications─ IP Rights Enable Sustainable Competitive Advantage

Increased R&D Return on Investment Increased R&D Return on Investment

High-Productivity Combinatorial R&D Platform and Methods

Intermolecular Confidential21

High-Productivity Combinatorial R&D Platform and Methods

Materials and Interface Engineering Platform Addressing Broad Range of Applications in Semi, Energy & Display

Solar

C lli ili

Initial Engagements Recent Engagements

Crystalline silicon

Thin film PVLighting

LED

Display / Sensors

OLEDEnergy Efficiency

Low-emissivity glass

Anti-reflective coatings

Logic

Memory

Semiconductors Display TFTs

Touch Screens

Memory

Energy Storage

Advanced Batteries

Super-capacitors

22

A l ti I ti

Intermolecular Confidential

Accelerating Innovation

The U.S. has Recognized the Critical Nature of High-Throughput Experimentation for the MGI

Public-Private Collaboration to Move Materials to Market Faster: Lawrence Berkeley National Laboratory (LBNL), Massachusetts Institute of Technology, and Intermolecular, Inc., are working together to more accurately predict material behavior with software tools made openly available by LBNL Building on dataopenly available by LBNL. Building on data from existing high-throughput combinatorial experimentation and simulation, researchers anticipate a set of tools that could increase the speed of new

t i l d l t t f ld

24

materials development ten-fold or more over conventional approaches.

High-Productivity Combinatorial R&D Methods

AdvantageConventional HPC

100x

100

Materials Discovery

Materials and Process 100x

10x

Materials and Process Development

Process Integration

1-10xDevice Qualification

Volume Manufacturing

25

Faster to Optimized Solutions

IMI P-30 HPCTM PVD Chamber

Core Attributes Multiple-Mode Combinatorial PVD

─ Isolation between spots ─ Gradient mode across large area─ Uniform mode across large area

Rapid Development Pace─ Mature process and hardware; high reliability, uptime & yieldMature process and hardware; high reliability, uptime & yield─ Multiple target combination for materials development

Modular and Versatile for Many Applications─ Robust hardware and process for wide range of materials

Process Transparency & Transferability to HVM─ Transparent process between co-sputtering and alloys─ Process matching between HPC and full wafer processes─ Demonstrated process correlation to HVM toolsDemonstrated process correlation to HVM tools

Intermolecular Confidential26

High-Productivity-Combinatorial PVD platform for rapid materials and process development

300mm HPC PVD Chamber Tempus P-30

UpperChamber

Up to 4 sputter sources─ OEM or IMI sputter source (rotating

magnetron)─ 2” or 3” targetsChamber

ShieldMultiple Panels

PVD SourceRetracted

ApertureShutterLi k

Middle

2 or 3 targets─ Direct or indirect cooled─ Adjustable throw (Z) and angle (Ө)

Textured process kit V i bl t i

PVD SourceDown

Linkage

S

LowerChamberShield

ChamberShield

Variable aperture sizes─ 25 and 60mm standard─ Custom sizes based on application

and wafer type (e.g. customer die specific)

SourceShutter

Shieldw/ApertureControls Aperture-to-Wafer Spacing

El t Aperture

p )

ElectroStaticChuck (ESC)

ApertureShutter

Wafer Lift

HPC (Single Source, Co-Sputtering, Stacks)and Full Wafer Processing Capability Four 2” or 3” PVD Sources

IMI A-30 HPCTM ALD / CVD Chamber

Core Attributes Multi-Mode Combinatorial & Full Wafer ALD/CVD

─ Complete isolation between process regions─ Uniform mode across full substrate (300mm wafer)

Rapid Development Pace─ Mature process and hardware; high reliability, uptime & yield

Flexible precursor & gas delivery for materials development─ Flexible precursor & gas delivery for materials development ─ In-depth know-how of Atomic Layer Deposition (ALD) and

Chemical Vapor Deposition (CVD) processing

Modular and Versatile for Many ApplicationsHPC Scale up

Tempus A-30

─ Robust hardware and process for wide range of applications

Process Transparency & Transferability to HVM─ Transparent process between HPC and full wafer processes─ Demonstrated process correlation to HVM tools

HPC(site-isolated)

Scale-up (full wafer)

─ Demonstrated process correlation to HVM tools

Hi h P d ti it C bi t i l ALD / CVD l tf f id

Intermolecular Confidential28

High-Productivity-Combinatorial ALD / CVD platform for rapid precursor and process development, with proven scalability

A-30/C-30 Product Configuration – HPC ALD/CVD

A‐30Thermal A‐30Plasma A‐30Spatial C‐30

4 precursors sources- ampoule, bubbler, DLI Purge

p , ,

- solid, liquid sources

- Ar, N2, He carrier gases

4 process gases e.g. O3, NH3, NF3, SiH4

Purge

Remote plasma

Precursor

Reactant

Purge

Continuous or Synchronous Rotation

Application Thermal ALDParallel Combi

(PE)ALDParallel Combi

(PE)ALDSpatial Combi

CVD, (PE)CVDParallel Combi

Hi h k MN

g 3 3 3 4

Precursor Type High-k, M High-k, M High-k, MN, Si High-k, MNSilane

PrecursorTemperature RT – 200°C RT – 200°C RT – 200°C RT – 200°C

Plasma - DirectCCP

Indirect ICP

DirectCCP

SubstrateTemperature

RT – 400°C RT – 400°C RT – 400°C RT – 650°C

ST-30 Surface Treatment Chamber Overview & Applications

Gas feed

Plasma

Dry cleans, surface treatment, defect passivation

Plasma source

Pedestal

reactive species *Interface layer

High-k

F*• Oxidation treatments (O2, O3)• Nitridation (N2, NH3)

H*, O*N*

species

Plasma source 2 MHz, ICP*

Substrate (Me, Si, SiGe, Ge, III-V)

Interface layer• Fluorination (NF3, CF4)• Atomic H clean (H*)

Gas compatibility Ar, O2, O3, N2,NF3, NH3, H2, He

Pressure range 0.05 – 1.5 TorrN doping

F doping

Pedestal Temp 400°C max.* Inductively coupled plasma

N doping

O doping

Intermolecular Confidential30

Bulk/ Interface treatment

TempusTM Wet Workflow Systems

Tempus F-10Library Design &

P ti

Tempus F-20Materials Screening & P D l t

Tempus F-30Integration / Scale-Up

Preparation Process Development

Library design & formulation Library design & Full wafer processingLibrary design & formulation including powders, viscous liquids & pH measurement

Dispenses by volume or

Library design & formulation of liquids

Simultaneously processes coupons with multiple

Full wafer processing with 28 site isolated cells

Customer product demonstration and

Intermolecular Confidential31

p yweight

p pformulations integration optimization

Intermolecular Tempus F-20High Productivity Combinatorial Wet Processing

Massively parallel formulation creation & testing─ Automated formulation library creation─ 40 chemical source vials

Preparation for up to 384 active formulations─ Preparation for up to 384 active formulations

Configurable reactor for testing flexibility─ Site isolated cells on wafer coupon─ Immersion or stir reaction modesImmersion or stir reaction modes─ Temperature controlled chuck

Up to 192 reaction tests per 300mm wafer6 300 f

Informatics integration for efficient data analysis

─ 6 coupons per 300mm wafer─ 18 or 32 parallel tests per coupon

Intermolecular Confidential32

Intermolecular Tempus F-30 HPC Wet Processing System

HPC Wet Process Development System─ Integrated HPC / Full-wafer processing─ 28X screening module

Applications: Fast loop reliability workflow Up stream and down stream28X screening module

─ 200mm/300mm single-wafer wet processing moduleUp stream and down stream process optimization.

Surface prep, clean, strip

E test

Full-Wafer Processing

E-test

Sit I l ti P i 28 Sit /300 f

Intermolecular Confidential33

Site-Isolation Processing – 28 Sites/300mm wafer

Tempus F-30 HPC Wet Clean/Wet Etch Processing

Parallel Processing─ Up to 28 site-isolated reactor cells─ Up to 18 chemical inputs

T t t ll d h k & h i l─ Temperature controlled chuck & chemical mixing vessel

Enhanced Development─ Capability to explore wider solution spaceCapability to explore wider solution space ─ More splits per wafer: accelerated learning─ Well-characterized material & process

Process Flexibility─ Control of multi-step sequencing─ Immersion & stir modes─ Configurable cell spacing to match die

pitchp

Clean Room Compatible─ Integrated FOUP Loader─ Notch alignment

Intermolecular Confidential34

─ Sequential dry in / dry out wafer processing

HPC Workflow Applications/CapabilitiesExample Semiconductor Customer Development Applications

Memory• DRAM capacitor (high-k dielectrics,

high WF non-noble electrodes)

Logic• High k – Metal Gates• EWF and multi-Vt tuning high WF non noble electrodes)

• ReRAM • eNVM (e-ReRAM)• Multi-component metal oxides

• EWF and multi Vt tuning• HKMG etch rate & selectivity• Reliability (BTI, Vbd, HCI...) • Rco, MIS and SBH modulation

• Workfunction tuned electrodes• Reliability (TDDB, Vbd, RTN, DR...) • Embedded R - Current compliance

Current steering element

• Conformal doping for Fin/HAR devices• Low k spacers in FEOL• Post CMP/implant/etch cleans

Sili id ( l /d / l) • Current steering element• Low Temp processing• Oxides/nitrides barriers/liners• Interface/band engineering

• Silicide process (cleans/dep/anneal)• Contact cleans• Post-etch low k passivation• Cu BEOL scaling & replacement e ace/ba d e g ee gCu BEOL scaling & replacement• GeMOS & III-V

OtherL T ALD f tt i • Low loss waveguides • 3D Packaging• Low T ALD for patterning

• ALD precursor screening• Power electronics

Low loss waveguides• STT RAM• Passivation studies

3D Packaging• 10nm Pattern collapse • RF MIM/Decoupling Caps