Department of Microelectronics and Nanoelectronics

Interfacing a PS-2 Keyboard and VGA Monitor toXilinx XC3S200 FPGA

Hardware Description Languages - MNE 2102Project

Department of Microelectronics and Nanoelectronics

VGA Port

Department of Microelectronics and Nanoelectronics

VGA Port

Department of Microelectronics and Nanoelectronics

640 x 480 Mode VGA Timing

25 MHz

Department of Microelectronics and Nanoelectronics

PS-2 Keyboard Port

Department of Microelectronics and Nanoelectronics

PS/2 Timing

Department of Microelectronics and Nanoelectronics

Keyboard to FPGA Communication

• The Data and Clock lines are both open collector. A resistor is connected between each line and +5V, so the idle state of the bus is high.

• When the keyboard wants to send information, it first checks the Clock line to make sure it's at a high logic level. If it's not, the FPGA is inhibiting communication and the device must buffer any to-be-sent data until the host releases Clock.

• The Clock line must be continuously high for at least 50 µs before the device can begin to transmit its data.

Department of Microelectronics and Nanoelectronics

Keyboard to FPGA Communication

• The keyboard use a serial protocol with 11-bit frames.

• These bits are: – 1 start bit. This is always 0. – 8 data bits, least significant bit first. – 1 parity bit (odd parity). – 1 stop bit. This is always 1.

Department of Microelectronics and Nanoelectronics

Keyboard to FPGA Communication

• The keyboard writes a bit on the Data line when Clock is high, and it is read by the host when Clock is low.

Department of Microelectronics and Nanoelectronics

PS/2 Keyboard Scan Codes

Department of Microelectronics and Nanoelectronics

Example: 1D => W

star

t

1 1 11 0 0 0 0 1 stop

parity bitscan code

Department of Microelectronics and Nanoelectronics

Proposed Architecture

CLK_in red_outscan_code green_out

blue_ouths_out vs_out

CLK_in scan_errreset scan_arvPS2_CLK scan_codePS2_DATAread

50 MHzcrystal

CLK_in red_outscan_code green_out

blue_ouths_out vs_out

CLK_in scan_errreset scan_arvPS2_CLK scan_codePS2_DATAread

50 MHzcrystal

Department of Microelectronics and Nanoelectronics

PS-Keyboard Controller

• reset Asynchronous reset• CLK_in Main synchronization clock signal• PS2_CLK Clock signal generated by the keyboard• PS2_DATA Signal on which serial data from the keyboard

is transmitted to the FPGA• read This is an input which must be pulsed when

the scan_code is read.• scan_arv This flag goes to 1 when a word has been

received. Remains there until read is asserted and then goes low at the next clock cycle.

• scan_err This flag is set when the data received is incorrect (parity, stop…) or when there is an overflow. This flag is automatically cleared when the reception of a new character begins.

• scan_code (8 bits) is the data word received from the keyboard

Department of Microelectronics and Nanoelectronics

VGA Display Controller

• CLK_in Main synchronization clock signal• scan_code (8 bits) is the data word received from

the keyboard• red_out Red Colour Enable• green_out Green Colour Enable• blue_out Blue Colour Enable• hs_out Horizontal sync signal• vs_out Vertical sync signal