interconnect verification for soc -...

------ EE NCTU EE NCTU EE NCTU ------

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Interconnect Verification for SOC

Jing-Yang JouDepartment of Electronics Engineering

National Chiao Tung UniversityHsinchu, Taiwan

E-mail: [email protected]: http://eda.ee.nctu.edu.tw/jyjou



Outlines

• Interconnect verification– Motivation– The port order fault (POF) model– The integration verification – Automatic verification pattern generation

(AVPG)



Verification Throughput

• The factors that govern simulation-based verification throughput:– The speed of the simulator– The complexity of the design– The size of the test (verification) bench



System Design Verification• SOB verification

– Components are designed, verified, manufactured, and tested (fault free building blocks )

– Limit to detecting faults in the interconnection among the components

• SOC verification– Components are design error free building blocks– Limit to detecting the misplacements of the

interconnection among the components• Reduce the verification complexity

– Port Order Fault (POF) model



Outlines

• Interconnect verification– Motivation– The port order fault (POF) model– The integration verification – Automatic verification pattern generation

(AVPG)



Basic Assumptions of the POF Model

• A faulty component has at least two I/O ports misplaced in the integrated design

• Components (IPs) are fault free • Only the interconnection among the

components could be faulty



POF Variety (1/3)

• Type-I POF

4-bit Adder

B3A3 B2A2 B1A1

B0

A0

S3 S2 S1

S0

CINCOUT



4-bit Adder

B3A3 B2A2 B1A1 B0A0

S3 S2 S1 S0

CINCOUT

• Type-II POF

POF Variety (2/3)



POF Variety (3/3)

4-bit Adder

B3A3 B2A2 B1A1 B0A0

S3S2S1S0

CINCOUT

• Type-III POF



Typical Errors in the Integrated SOC Design

• VCs are connected with wrong port orders

• VCs with incompatible communication protocols are directly connected– PCI vs. AMBA

• Interface parameters are not properly configured– Baud rate 2400 vs. baud rate 9600

TXRX

TXRX

TXRX

TXRX



Outlines

• Interconnect verification– Motivation– The port order fault (POF) model– The integration verification– Automatic verification pattern generation

(AVPG)



Interconnect Testing

IP2IP1

wrapperwrapper

Applypatterns

Observeresponses



Interconnect Verification

IP2IP1

wrapperwrapper

Applypatterns

Observeresponses



Integration Verification

BLK1

BLK2

BLK4

Apply patternsT to PIs

Interconnect A

VerificationPatterns

Generation

BLK3

BLK5

Interconnect B

Observeresponses R

from POs

Output

Analyzer

BLK6

Interconnect C



• Verifying the interconnect A, B, and C– Apply patterns T to PIs and observe responses R from POs

• The generation of T depends on the functionalities of BLK1 ~BLK6

• Complexity of cores increases and more cores are involved– T becomes harder to generate

• Solution ?




System Chip with P1500 Cores



• IEEE P1500 – Establishes the mechanism that test patterns of any

CUT can be applied to PIs of the system chip and test results can be propagated to POs of the system chip via user defined TAMs

– Pre-defined operations: core-internal test, core-external test, bypass, isolation, and normal modes




Interconnect Verification

IP2IP1

wrapperwrapper

Applypatterns

Observeresponses



Integration VerificationApply patterns

T to PIs

Interconnect A

Observeresponses R

from POs


Generation

BLK3

OutputAnalyzer

BLK1

core1

wrapper

core2

wrapperBLK2

normal mode

core4

wrapper

BLK4

external test mode

external test mode



Integration VerificationApply patterns

T to PIs

Interconnect C

Observeresponses R

from POs


Generation

BLK3

OutputAnalyzer

bypass modeBLK1

core1

wrapper

core2

wrapperBLK2

external test modeBLK4

bypass mode

SoSi

Si So

BLK5

normal mode

core6

wrapper

BLK6

core4

wrapper

VerifiedInterconnect B



Verification Features• Reduce the complexity of POF verification

– Focus on the functionality of the added block solely when generating the verification patterns

• Exercise the core via the normal operation path to verify the interconnect– Consistency check of simulation results and

expected ones• Reuse the hardware overhead incurred in the

testing phase



Outlines

• Interconnect verification– Motivation– The port order fault (POF) model– The integration verification– Automatic verification pattern generation

(AVPG)



Automatic Verification Pattern Generation (AVPG)

• Fault Activation– All N!-1 POFs have to be activated

• Fault Propagation– Determined by simulation outputs

• Undetected Port Sequences (UPSs) Calculation– Outputs analysis



b e n c h |P I | |P O | l i t s p a t s . F .C . t i m e ( s e c )c 1 7 5 2 1 2 5 1 1

c 8 8 0 6 0 2 6 7 0 3 2 4 3 0 .9 9 9 9 9 9 9 9 7 0 c 1 3 5 5 4 1 3 2 1 0 3 2 6 4 1 1 3 c 1 9 0 8 3 3 2 5 1 4 9 7 5 1 1 4 2 c 4 3 2 3 6 7 3 7 2 3 8 1 5 c 4 9 9 4 1 3 2 6 1 6 3 3 1 8

c 3 5 4 0 5 0 2 2 2 9 3 4 1 4 5 1 7 2 7 c 5 3 1 5 1 7 8 1 2 3 4 3 6 9 3 7 1 1 9 3 1 c 2 6 7 0 2 3 3 1 4 0 2 0 4 3 5 2 1 0 .9 9 9 9 9 9 9 9 7 2 1 c 7 5 5 2 2 0 7 1 0 8 6 0 9 8 1 6 2 7 0 .9 9 9 9 9 9 9 9 1 8 2 6 c 6 2 8 8 3 2 3 2 4 8 0 0 3 0 0 .9 9 9 9 9 9 9 9 1 7 5

d e s 2 5 6 2 4 5 7 4 1 2 4 2 8 1 1 5 9 a l u 4 1 4 8 1 2 7 8 2 2 1 3

a p e x 6 1 3 5 9 9 9 0 4 2 3 4 0 .9 9 9 9 9 9 9 9 4 0 6 i 9 8 8 6 3 1 4 5 3 1 3 9 1 2 5 i 8 1 3 3 8 1 4 6 2 6 2 6 6 1 4 1 5 i 7 1 9 9 6 7 1 3 1 1 2 9 2 1 1 0 3 i 6 1 3 8 6 7 1 0 3 7 1 6 5 1 7 7 i 5 1 3 3 6 6 5 5 6 1 5 5 1 6 3

d u k e 2 2 2 2 9 1 7 4 6 7 4 1 8 3 r o t 1 3 5 1 0 7 1 4 2 4 5 2 4 0 .9 9 9 9 9 9 9 9 2 4 6 x 1 5 1 3 5 2 1 4 1 2 7 5 0 .9 9 9 9 9 9 9 9 3 4 x 3 1 3 5 9 9 1 8 1 6 2 4 9 0 .9 9 9 9 9 9 9 9 1 7 1 x 4 9 4 7 1 1 0 4 0 3 5 2 0 .9 9 9 9 9 9 9 9 6 9

p a i r 1 7 3 1 3 7 2 6 6 7 2 1 7 1 4 4 3

Experimental Results



• Interconnect verification provides a sufficient high level of confidence on verifying the correctness of the core-based system (SOC) design

• Proposed AVPG can generate efficient verification patterns with high POF coverage

Conclusions

interconnect verification for soc -...

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