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SAP 1 and SAP 2 MD.AL AMIN aminspicse@gmail.com13-Dec-16

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MD.AL AMIN aminspicse@gmail.com13-Dec-16

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MD.AL AMIN aminspicse@gmail.com13-Dec-16

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MD.AL AMIN aminspicse@gmail.com13-Dec-16

Intel 8085 Microprocessor

Accumulator (8)Temp. Reg. (8)InstructionResister (8)Multiplexer

Flag (5)Flip-Flops

Arithmetic Logic Unit (ALU) (8)

Timing and Control

Instruction Decoder and Machine Cycle Encoding

W (8) TempReg.Z (8)TempReg.B (8)Reg.C (8)Reg.D (8)Reg.E (8)Reg.H (8)Reg.L (8)Reg.16Stack Pointer16Program Counter Increment/DecreetAddress Latch (16)

Resister Array(8) Address Buffer

(8)Data/Address BufferResister

AD7-AD0 Address/Data BusA15 A8 Data BusCLK OUTRDWRALES0S1IO/MHOLDHLDARESET INRESET OUTREADYInterrupt Control

8 bit Internal Data BusSerial I/o Control

INTRINTARST 5.5RST 6.5RST 7.5TRAPSIDSODControlStatusDMA

ResetX1X2+5 VoltGNDPower supplyMD.AL AMIN aminspicse@gmail.com13-Dec-16

) MUP ) ) ) ) A0 A15 16 , MPU MPU MD.AL AMIN aminspicse@gmail.com13-Dec-16

)

B,C,D,E,H L BC,DE HL

- / A MD.AL AMIN aminspicse@gmail.com13-Dec-16

ALU -

,

R/D MD.AL AMIN aminspicse@gmail.com13-Dec-16

) - RD WR -

ALU ,

W Z MD.AL AMIN aminspicse@gmail.com13-Dec-16

ALU ; , ,

INTR RST 5.5,RST 6.5,RST 7.5 TRAP

I/O SOD SID SIM RIM SIM RIM I/O

MD.AL AMIN aminspicse@gmail.com13-Dec-16

13-Dec-16MD.AL AMIN aminspicse@gmail.com

142356789101112131415161718192o31302928272625242322214039383736353433328085 ARESETOUTINTAINTRRST 5.5RST 6.5RST 7.5TRAPSIDSODHOLDALEREADYCLK(OUT)HLDA8085 Pinout 8085

RESET OUTCLK OUT

SIDSODTRAPRST 7.5RST 6.5RST 5.5INTRREADYHOLDHLDA 547689103539361138Serial I/OPortsExternallyInitiatedSignalsExternal SignalAcknowledgment12402033728313234332930121921ALE Multiplexed Address/Data BusHigh-Order Address/Data BusControl and Status Signals 8085 8085 A+ 5 VGNDMD.AL AMIN aminspicse@gmail.com13-Dec-16

Address bus : A8-A15

Multiplexed address /data bus : AD0-AD7 , ,

Control and status signals : , MD.AL AMIN aminspicse@gmail.com13-Dec-16

a) ALE ; AD0-AD7 A7-A0 b) RD c) WR

d) Io/m I/O I/O ; I/O MD.AL AMIN aminspicse@gmail.com13-Dec-16

e) S1 and S2 I/O

i/om s1 s0OpcodeFetch0 1 1RD =0Memory read0 1 0WR =0Memory write0 0 1RD =0I/O read1 1 0RD =0I/O write1 0 1WR =0Interrupt acknowledge1 1 1INTA=0HaltHoldresetZ 0 0Z x xZ x xRD,WR=Z ANDINTA =1

MD.AL AMIN aminspicse@gmail.com13-Dec-16

Power supply and clock frequency : a) vss: +5v b) vcc: c) x1,x2: d) CLK(OUT): External initiated signals:a) Inturrupt request : b) Inturrupt acknowledge: c) Restart interrupt: RST6.5 RST5.5 INTR MD.AL AMIN aminspicse@gmail.com13-Dec-16

d) TRAP:

e) HOLD:

f) HLDA: HOLD

g) READY: MD.AL AMIN aminspicse@gmail.com13-Dec-16

h) RESET IN: , - MPU

I) RESET OUT: MPU

Serial i/o ports : - SID SOD MD.AL AMIN aminspicse@gmail.com13-Dec-16

ENDENDTHETHEMD.AL AMIN aminspicse@gmail.com13-Dec-16