instructor : po-yu kuo 教師:郭柏佑 ch. 3 digital logic structures el 1009 計算機概論 (...
TRANSCRIPT
![Page 1: Instructor : Po-Yu Kuo 教師:郭柏佑 Ch. 3 Digital Logic Structures EL 1009 計算機概論 ( 電子一 B) Introduction to Computer Science](https://reader031.vdocuments.mx/reader031/viewer/2022012312/56649ca65503460f94968bae/html5/thumbnails/1.jpg)
Instructor : Po-Yu Kuo
教師:郭柏佑
Ch. 3 Digital Logic Structures
EL 1009 計算機概論 ( 電子一 B)
Introduction to Computer Science
![Page 2: Instructor : Po-Yu Kuo 教師:郭柏佑 Ch. 3 Digital Logic Structures EL 1009 計算機概論 ( 電子一 B) Introduction to Computer Science](https://reader031.vdocuments.mx/reader031/viewer/2022012312/56649ca65503460f94968bae/html5/thumbnails/2.jpg)
2
The Transistor
![Page 3: Instructor : Po-Yu Kuo 教師:郭柏佑 Ch. 3 Digital Logic Structures EL 1009 計算機概論 ( 電子一 B) Introduction to Computer Science](https://reader031.vdocuments.mx/reader031/viewer/2022012312/56649ca65503460f94968bae/html5/thumbnails/3.jpg)
3
Transistor: Building Block of ComputersMicroprocessors contain millions of transistors
Intel Pentium 4 (2000): 48 million IBM PowerPC 750FX (2002): 38 million IBM/Apple PowerPC G5 (2003): 58 million
Logically, each each transistor acts as a switch
Combined to implement logic functions AND, OR, NOT
Combined to build higher-level structures Adder, multiplexer, decoder, register, …
Combined to build processor LC-3
![Page 4: Instructor : Po-Yu Kuo 教師:郭柏佑 Ch. 3 Digital Logic Structures EL 1009 計算機概論 ( 電子一 B) Introduction to Computer Science](https://reader031.vdocuments.mx/reader031/viewer/2022012312/56649ca65503460f94968bae/html5/thumbnails/4.jpg)
4
Simple Switch CircuitSwitch open:
No current through circuit Light is off Vout is +2.9V
Switch closed: Short circuit across switch Current flows Light is on Vout is 0V
Switch-based circuits can easily represent two states: on/off, open/closed, voltage/no voltage
![Page 5: Instructor : Po-Yu Kuo 教師:郭柏佑 Ch. 3 Digital Logic Structures EL 1009 計算機概論 ( 電子一 B) Introduction to Computer Science](https://reader031.vdocuments.mx/reader031/viewer/2022012312/56649ca65503460f94968bae/html5/thumbnails/5.jpg)
5
n-type MOS Transistor
MOS = Metal Oxide Semiconductor two types: n-type and p-type
n-type when Gate has positive voltage,
short circuit between #1 and #2(switch closed)
when Gate has zero voltage,open circuit between #1 and #2(switch open)
Gate = 1
Gate = 0Terminal #2 must beconnected to GND (0V).
![Page 6: Instructor : Po-Yu Kuo 教師:郭柏佑 Ch. 3 Digital Logic Structures EL 1009 計算機概論 ( 電子一 B) Introduction to Computer Science](https://reader031.vdocuments.mx/reader031/viewer/2022012312/56649ca65503460f94968bae/html5/thumbnails/6.jpg)
6
p-type MOS Transistor
p-type is complementary to n-type when Gate has zero voltage,
short circuit between #1 and #2(switch closed)
when Gate has postive voltage,open circuit between #1 and #2(switch open)
Gate = 1
Gate = 0Terminal #1 must beconnected to +2.9V.
![Page 7: Instructor : Po-Yu Kuo 教師:郭柏佑 Ch. 3 Digital Logic Structures EL 1009 計算機概論 ( 電子一 B) Introduction to Computer Science](https://reader031.vdocuments.mx/reader031/viewer/2022012312/56649ca65503460f94968bae/html5/thumbnails/7.jpg)
7
Logic Gates
![Page 8: Instructor : Po-Yu Kuo 教師:郭柏佑 Ch. 3 Digital Logic Structures EL 1009 計算機概論 ( 電子一 B) Introduction to Computer Science](https://reader031.vdocuments.mx/reader031/viewer/2022012312/56649ca65503460f94968bae/html5/thumbnails/8.jpg)
8
Logic GatesUse switch behavior of MOS transistors to implement
logical functions: AND, OR, NOT.
Digital symbols: recall that we assign a range of analog voltages to each
digital (logic) symbol
assignment of voltage ranges depends on electrical properties of transistors being used Typical values for "1": +5V, +3.3V, +2.9V from now on we'll use +2.9V
![Page 9: Instructor : Po-Yu Kuo 教師:郭柏佑 Ch. 3 Digital Logic Structures EL 1009 計算機概論 ( 電子一 B) Introduction to Computer Science](https://reader031.vdocuments.mx/reader031/viewer/2022012312/56649ca65503460f94968bae/html5/thumbnails/9.jpg)
9
CMOS Circuit
Complementary MOS
Use both n-type and p-type MOS transistors p-type
Attached to + voltage Pulls output voltage UP when input is zero
n-type Attached to GND Pulls output voltage DOWN when input is one
For all inputs, make sure that output is either connected to GND or to +, but not both!!
![Page 10: Instructor : Po-Yu Kuo 教師:郭柏佑 Ch. 3 Digital Logic Structures EL 1009 計算機概論 ( 電子一 B) Introduction to Computer Science](https://reader031.vdocuments.mx/reader031/viewer/2022012312/56649ca65503460f94968bae/html5/thumbnails/10.jpg)
10
Inverter (NOT Gate)
In Out
0 V 2.9 V
2.9 V 0 V
In Out
0 1
1 0
Truth table
![Page 11: Instructor : Po-Yu Kuo 教師:郭柏佑 Ch. 3 Digital Logic Structures EL 1009 計算機概論 ( 電子一 B) Introduction to Computer Science](https://reader031.vdocuments.mx/reader031/viewer/2022012312/56649ca65503460f94968bae/html5/thumbnails/11.jpg)
11
NOR Gate
A B C
0 0 1
0 1 0
1 0 0
1 1 0Note: Serial structure on top, parallel on bottom.
![Page 12: Instructor : Po-Yu Kuo 教師:郭柏佑 Ch. 3 Digital Logic Structures EL 1009 計算機概論 ( 電子一 B) Introduction to Computer Science](https://reader031.vdocuments.mx/reader031/viewer/2022012312/56649ca65503460f94968bae/html5/thumbnails/12.jpg)
12
OR Gate
A B C
0 0 0
0 1 1
1 0 1
1 1 1
Add inverter to NOR.
![Page 13: Instructor : Po-Yu Kuo 教師:郭柏佑 Ch. 3 Digital Logic Structures EL 1009 計算機概論 ( 電子一 B) Introduction to Computer Science](https://reader031.vdocuments.mx/reader031/viewer/2022012312/56649ca65503460f94968bae/html5/thumbnails/13.jpg)
13
NAND Gate (AND-NOT)
A B C
0 0 1
0 1 1
1 0 1
1 1 0Note: Parallel structure on top, serial on bottom.
![Page 14: Instructor : Po-Yu Kuo 教師:郭柏佑 Ch. 3 Digital Logic Structures EL 1009 計算機概論 ( 電子一 B) Introduction to Computer Science](https://reader031.vdocuments.mx/reader031/viewer/2022012312/56649ca65503460f94968bae/html5/thumbnails/14.jpg)
14
AND Gate
A B C
0 0 0
0 1 0
1 0 0
1 1 1
Add inverter to NAND.
![Page 15: Instructor : Po-Yu Kuo 教師:郭柏佑 Ch. 3 Digital Logic Structures EL 1009 計算機概論 ( 電子一 B) Introduction to Computer Science](https://reader031.vdocuments.mx/reader031/viewer/2022012312/56649ca65503460f94968bae/html5/thumbnails/15.jpg)
15
Basic Logic Gates
![Page 16: Instructor : Po-Yu Kuo 教師:郭柏佑 Ch. 3 Digital Logic Structures EL 1009 計算機概論 ( 電子一 B) Introduction to Computer Science](https://reader031.vdocuments.mx/reader031/viewer/2022012312/56649ca65503460f94968bae/html5/thumbnails/16.jpg)
16
DeMorgan's Law
Converting AND to OR (with some help from NOT)
Consider the following gates
A AND B = A OR B
Same as A+B !
A B
0 0 1 1 1 0
0 1 1 0 0 1
1 0 0 1 0 1
1 1 0 0 0 1
BA BA BA To convert AND to OR (or vice versa),invert inputs and output.
![Page 17: Instructor : Po-Yu Kuo 教師:郭柏佑 Ch. 3 Digital Logic Structures EL 1009 計算機概論 ( 電子一 B) Introduction to Computer Science](https://reader031.vdocuments.mx/reader031/viewer/2022012312/56649ca65503460f94968bae/html5/thumbnails/17.jpg)
17
More than 2 Inputs?
AND/OR can take any number of inputs. AND = 1 if all inputs are 1. OR = 1 if any input is 1. Similar for NAND/NOR.
Can implement with multiple two-input gates, or with single CMOS circuit.
Cost problem!!
![Page 18: Instructor : Po-Yu Kuo 教師:郭柏佑 Ch. 3 Digital Logic Structures EL 1009 計算機概論 ( 電子一 B) Introduction to Computer Science](https://reader031.vdocuments.mx/reader031/viewer/2022012312/56649ca65503460f94968bae/html5/thumbnails/18.jpg)
18
Combinational Logic Circuit
![Page 19: Instructor : Po-Yu Kuo 教師:郭柏佑 Ch. 3 Digital Logic Structures EL 1009 計算機概論 ( 電子一 B) Introduction to Computer Science](https://reader031.vdocuments.mx/reader031/viewer/2022012312/56649ca65503460f94968bae/html5/thumbnails/19.jpg)
19
Building Fucnctions from Logic GatesCombinational Logic Circuit
output depends only on the current inputs stateless
Sequential Logic Circuit output depends on the sequence of inputs (past and
present) stores information (state) from past inputs
We'll first look at some useful combinational circuits, then
show how to use sequential circuits to store information.
![Page 20: Instructor : Po-Yu Kuo 教師:郭柏佑 Ch. 3 Digital Logic Structures EL 1009 計算機概論 ( 電子一 B) Introduction to Computer Science](https://reader031.vdocuments.mx/reader031/viewer/2022012312/56649ca65503460f94968bae/html5/thumbnails/20.jpg)
20
Decoder
n inputs, 2n outputs exactly one output is 1 for each possible input pattern
2-bitdecoder
![Page 21: Instructor : Po-Yu Kuo 教師:郭柏佑 Ch. 3 Digital Logic Structures EL 1009 計算機概論 ( 電子一 B) Introduction to Computer Science](https://reader031.vdocuments.mx/reader031/viewer/2022012312/56649ca65503460f94968bae/html5/thumbnails/21.jpg)
21
Multiplexer (MUX)
n-bit selector and 2n inputs, one output output equals one of the inputs, depending on
selector
4-to-1 MUX
![Page 22: Instructor : Po-Yu Kuo 教師:郭柏佑 Ch. 3 Digital Logic Structures EL 1009 計算機概論 ( 電子一 B) Introduction to Computer Science](https://reader031.vdocuments.mx/reader031/viewer/2022012312/56649ca65503460f94968bae/html5/thumbnails/22.jpg)
22
Full Adder Add two bits and carry-in, produce one-bit sum and
carry-out.A B Cin S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
![Page 23: Instructor : Po-Yu Kuo 教師:郭柏佑 Ch. 3 Digital Logic Structures EL 1009 計算機概論 ( 電子一 B) Introduction to Computer Science](https://reader031.vdocuments.mx/reader031/viewer/2022012312/56649ca65503460f94968bae/html5/thumbnails/23.jpg)
23
Four-bit Adder
![Page 24: Instructor : Po-Yu Kuo 教師:郭柏佑 Ch. 3 Digital Logic Structures EL 1009 計算機概論 ( 電子一 B) Introduction to Computer Science](https://reader031.vdocuments.mx/reader031/viewer/2022012312/56649ca65503460f94968bae/html5/thumbnails/24.jpg)
24
Logical Completeness
A B C D
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 0
1. AND combinations that yield a "1" in the truth table.
2. OR the resultsof the AND gates.
Can implement ANY truth table with AND, OR, NOT.
![Page 25: Instructor : Po-Yu Kuo 教師:郭柏佑 Ch. 3 Digital Logic Structures EL 1009 計算機概論 ( 電子一 B) Introduction to Computer Science](https://reader031.vdocuments.mx/reader031/viewer/2022012312/56649ca65503460f94968bae/html5/thumbnails/25.jpg)
25
Basic Storage Elements
![Page 26: Instructor : Po-Yu Kuo 教師:郭柏佑 Ch. 3 Digital Logic Structures EL 1009 計算機概論 ( 電子一 B) Introduction to Computer Science](https://reader031.vdocuments.mx/reader031/viewer/2022012312/56649ca65503460f94968bae/html5/thumbnails/26.jpg)
26
Combinational vs. SequentialCombinational Circuit always gives the same output for a given set of inputs
ex: adder always generates sum and carry,regardless of previous inputs
Sequential Circuit stores information output depends on stored information (state) plus input
so a given input might produce different outputs,depending on the stored information
example: ticket counter advances when you push the button output depends on previous state
useful for building “memory” elements and “state machines”
![Page 27: Instructor : Po-Yu Kuo 教師:郭柏佑 Ch. 3 Digital Logic Structures EL 1009 計算機概論 ( 電子一 B) Introduction to Computer Science](https://reader031.vdocuments.mx/reader031/viewer/2022012312/56649ca65503460f94968bae/html5/thumbnails/27.jpg)
27
R-S Latch: Simple Storage Element R is used to “reset” or “clear” the element – set it to zero. S is used to “set” the element – set it to one.
If both R and S are one, out could be either zero or one. “quiescent” state -- holds its previous value note: if a is 1, b is 0, and vice versa
1
1
1
1
0
0
1
1
0
0
1
1
![Page 28: Instructor : Po-Yu Kuo 教師:郭柏佑 Ch. 3 Digital Logic Structures EL 1009 計算機概論 ( 電子一 B) Introduction to Computer Science](https://reader031.vdocuments.mx/reader031/viewer/2022012312/56649ca65503460f94968bae/html5/thumbnails/28.jpg)
28
Clearing the R-S latch Suppose we start with output = 1, then change R to zero.
Then set R=1 to “store” value in quiescent state.
1
1
1
1
0
0
0
0
0
1
1
Output changes to zero.1
![Page 29: Instructor : Po-Yu Kuo 教師:郭柏佑 Ch. 3 Digital Logic Structures EL 1009 計算機概論 ( 電子一 B) Introduction to Computer Science](https://reader031.vdocuments.mx/reader031/viewer/2022012312/56649ca65503460f94968bae/html5/thumbnails/29.jpg)
29
Setting the R-S Latch Suppose we start with output = 0, then change S to zero.
Then set S=1 to “store” value in quiescent state.
Output changes to one.
1
1
0
0
1
1
0
1
1
1
0
0
![Page 30: Instructor : Po-Yu Kuo 教師:郭柏佑 Ch. 3 Digital Logic Structures EL 1009 計算機概論 ( 電子一 B) Introduction to Computer Science](https://reader031.vdocuments.mx/reader031/viewer/2022012312/56649ca65503460f94968bae/html5/thumbnails/30.jpg)
30
R-S Latch Summary R = S = 1
hold current value in latch S = 0, R=1
set value to 1 R = 0, S = 1
set value to 0 R = S = 0
both outputs equal one final state determined by
electrical properties of gates Don’t do it!
![Page 31: Instructor : Po-Yu Kuo 教師:郭柏佑 Ch. 3 Digital Logic Structures EL 1009 計算機概論 ( 電子一 B) Introduction to Computer Science](https://reader031.vdocuments.mx/reader031/viewer/2022012312/56649ca65503460f94968bae/html5/thumbnails/31.jpg)
31
Homework#2
1. 習題 3.1, 3.2, 3.5, 3.6, 3.7, 3.9, 3.10, 3.12, 3.16, 3.22.
繳交期限 : 2013/10/31 。