Introduction

Chapter 2 Sections 2.1 2.10

Based on slides fromDr. Iyad F. JafarInstructions: Language of the ComputerOutlineThe Von Neumann Architecture Busses & Memory Program ExecutionThe Computer LanguageInstruction Set Architecture The MIPS ISAMIPS Design PrinciplesFallacies and Pitfalls Further Reading More Examples

22The Von Neumann Architecture 3John Von Neumann,1945 A computer consists of ProcessorMemory Input and Output Stored-program concept as opposed to program-controlled computers !Programs and data are loaded into memory prior to executionDifferent components are connected via set of shared wires called Busses for information exchangeCompare to Harvard Architecture! ProcessorMemoryDevicesDatapathControlInputOutputStored-program computers were an advancement over the program-controlled computers of the 1940s, such as the Colossus and the ENIAC, which were programmed by setting switches and inserting patch leads to route data and to control signals between various functional units. In the vast majority of modern computers, the same memory is used for both data and program instructions.3BussesIn any computer, there is usually three types of bussesDataUsed to exchange data between componentsBidirectional Typical size 8, 16, 32, and 64 bits

AddressUsed to specify the source/destination Unidirectional The size of the bus specifies the number of entities (memory locations,I/O) that can be addressed

Control Used to specify the operation requested by the CPU (READ, WRITE, and other handshaking operations)

440Memory5Bn-1B10B0Bn-1B11B0Bn-1B12B0Bn-1B1M-1B0n bits(Memory Width)Address(Log2 M bits)ControlData(n bits)5Program ExecutionProgram = Instructions + Data Programs are loaded into memory prior to executionIn order to execute the instructions, the CPU Fetches the instructionRead the instruction from memory (Control Unit) Decodes the instruction Understand what should be done (Control Unit)Executes the instruction Perform the required task (Datapath)This is done repeatedly until the end of program !6FetchDecodeExecute 6The Computer LanguageCommanding computers requires speaking their language; Binary electric signals at the hardware level (Machine Language) Tedious, time consuming, error-prone, knowledge about processor architectureMake it easier! Represent binary instruction by words (Assembly Language). Convert words to binary manually or using AssemblersTedious, time consuming, error-prone, knowledge about processor architecture One line corresponds to one instruction!!Make it even easier! Make expressing instructions closer to the way humans express operations (High-level Languages)Conversion to machine language is done automatically using Compilers

7Suppose we want to perform two operations Add two numbers X and Y and store the result in ZAssign element 5 from array ARR to W00001 0011 0001 001000101 0010 0000 0111ADD Z, X, YREADW, ARR[5]Z = X + Y W = ARR[5]7Instruction Set Architecture Designing processors requires specifying the type and number of instructions the processor is supposed to support and how a programmer can use it

This is specified by the instruction set architecture (ISA) of the processor which includes Instructions (type, encoding, operation )Memory and I/O access Registers (Why do we need registers !)

Different processors have different ISAIA-32, MIPS, SPARC, ARM, DEC, HP, IBM,

The same ISA can be implemented in different ways to achieve different goals Single-cycle, multi-cycle, pipelining,

88Instruction Set Architecture Generally, the design of ISA could follow one of two schoolsCISC - Complex Instruction Set Computers RISC - Reduced Instruction Set Computers (~1980s )

9CISCRISCMany instructions and addressing modes Few instructions and addressing modes Instructions have different levels of complexity (different size and execution time)Simple instructions of fixed sizeShorter programs Longer programs Relatively slow Relatively fast Expensive !!! (not really)Cheaper !! (not really)Intel, AMD, Cyrix MIPS, Sun SPARC, HP PA-RISC, IBM PowerPCRISCThe concept was developed by John Cocke of IBM Research during 1974. His argument was based upon the notion that a computer uses only 20% of the instructions, making the other 80% superfluous to requirement. A processor based upon this concept would use few instructions, which would require fewer transistors, and make them cheaper to manufacture. By reducing the number of transistors and instructions to only those most frequently used, the computer would get more done in a shorter amount of time. The term 'RISC' (short for Reduced Instruction Set Computer) was later coined by David Patterson, a teacher at the University of California in Berkeley. The RISC concept was used to simplify the design of the IBM PC/XT, and was later used in the IBM RISC System/6000 and Sun Microsystems' SPARC microprocessors. The latter CPU led to the founding of MIPS Technologies, who developed the M.I.P.S. RISC microprocessor (Microprocessor without Interlocked Pipe Stages). Many of the MIPS architects also played an instrumental role in the creation of the Motorola 68000, as used in the first Amigas (MIPS Technologies were later bought by Silicon Graphics).. The MIPS processor has continued development, remaining a popular choice in embedded and low-end market. At one time, it was suspected the Amiga MCC would use this CPU to reduce the cost of manufacture. However, the consumer desktop market is limited, only the PowerPC processor remains popular in the choice of RISC alternatives. This is mainly due to Apple's continuous use of the series for its PowerMac range.

CISCCISC (Complex Instruction Set Computer) is a retroactive definition that was introduced to distinguish the design from RISC microprocessors. In contrast to RISC, CISC chips have a large amount of different and complex instruction. The argument for its continued use indicates that the chip designers should make life easier for the programmer by reducing the amount of instructions required to program the CPU. Due to the high cost of memory and storage CISC microprocessors were considered superior due to the requirements for small, fast code. In an age of dwindling memory hard disk prices, code size has become a non-issue (MS Windows, hello?). However, CISC-based systems still cover the vast majority of the consumer desktop market. The majority of these systems are based upon the x86 architecture or a variant. The Amiga, Atari, and pre-1994 Macintosh systems also use a CISC microprocessor. RISC Vs. CISCThe argument over which concept is better has been repeated over the past few years. Macintosh owners have elevated the argument to a pseudo religious level in support of their RISC-based God (the PowerPC sits next to the Steve Jobs statue on every Mac altar). Both positions have been blurred by the argument that we have entered a Post-RISC stage.

RISC: For and AgainstRISC supporters argue that it the way of the future, producing faster and cheaper processors - an Apple Mac G3 offers a significant performance advantage over its Intel equivalent. Instructions are executed over 4x faster providing a significant performance boost! However, RISC chips require more lines of code to produce the same results and are increasingly complex. This will increase the size of the application and the amount of overhead required. RISC developers have also failed to remain in competition with CISC alternatives. The Macintosh market has been damaged by several problems that have affected the availability of 500MHz+ PowerPC chips. In contrast, the PC compatible market has stormed ahead and has broken the 1GHz barrier. Despite the speed advantages of the RISC processor, it cannot compete with a CISC CPU that boasts twice the number of clock cycles. CISC: For and AgainstAs discussed above, CISC microprocessors are more expensive to make than their RISC cousins. However, the average Macintosh is more expensive than the WIntel PC. This is caused by one factor that the RISC manufacturers have no influence over - market factors. In particular, the Intel market has become the definition of personal computing, creating a demand from people who have not used a computer previous. The x86 market has been opened by the development of several competing processors, from the likes of AMD, Cyrix, and Intel. This has continually reduced the price of a CPU of many months. In contrast, the PowerPC Macintosh market is dictated by Apple. This reduces the cost of x86 - based microprocessors, while the PowerPC market remains stagnant.Post-RISCAs the world enters the 21st century the CISC Vs. RISC arguments have been swept aside by the recognition that neither terms are accurate in their description. The definition of 'Reduced' and 'Complex' instructions has begun to blur, RISC chips have increased in their complexity (compare the PPC 601 to the G4 as an example) and CISC chips have become more efficient. The result are processors that are defined as RISC or CISC only by their ancestry. The PowerPC 601, for example, supports more instructions than the Pentium. Yet the Pentium is a CISC chip, while the 601 is considered to be RISC. CISC chips have also gained techniques associated with RISC processors. Intel describe the Pentium II as a CRISC processor, while AMD use a RISC architecture but remain compatible with the dominant x86 CISC processors. Thus it is no longer important which camp the processor comes from, the emphasis has once-again been placed upon the operating system and the speed that it can execute instructions. EPICIn the aftermath of the CISC-RISC conflict, a new enemy has appeared to threaten the peace. EPIC (Explicitly Parallel Instruction Computing) was developed by Intel for the server market, thought it will undoubtedly appear in desktops over the next few years. The first EPIC processor will be the 64-bit Merced, due for release sometime during 2001 (or 2002, 2003, etc.). The market may be divided between combined CISC-RISC systems in the low-end and EPIC in the high-end. Famous RISC microprocessors801To prove that his RISC concept was sound, John Cocke created the 801 prototype microprocessor (1975). It was never marketed but plays a pivotal role in computer history, becoming the first RISC microprocessor. RISC 1 and 2The first "proper" RISC chips were created at Berkeley University in 1985.ARMOne of the most well known RISC developers is Cambridge based Advanced Research Machines (originally Acorn Research Machines). Their ARM and StrongARM chips power the old Acorn Archimedes and the Apple Newton handwriting recognition systems. Since the unbundling of ARM from Acorn, Intel have invested a considerable amount of money in the company and have utilized the technology in their processor design. One of the main advantages for the ARM is the price- it costs less than 10.If Samsung had bought the Amiga in 1994, they would possibly have used the chip to power the low-end Amigas

9The MIPS ISAHistorical Facts Microprocessor without Interlocked Pipeline StagesFirst MIPS processor by John Hennessey in 1981 at Stanford UniversityMIPS Technologies, Inc. 1984 First commercial model R2000 1985

General Features RISC 32-bit and 64-bit Register-Register Architecture (Load-Store)ISA revisions MIPS I, MIPS II, MIPS III, MIPS IV, MIPS V, MIPS32, and MIPS64Different processor models R2000, R3000, R4000, R100001010The MIPS ISA Register File110012B31B131B032 bitsB31B1B0B31B1B0B31B1B0Read Addr 1Read Addr 2Write AddrWrite DataRead/WriteRead Data 1Read Data 2 Inside the CPU SRAM !! Hold data temporarily Some sort of caching of data Why two read ports ? 553253232Two read ports for faster access of two operands Can read while writing , dedicated write port

11#NamePurpose$0$zeroConstant zero$1$atReserved for assembler$2$v0Function return value$3$v1$4$a0Function parameter$5$a1$6$a2$7$a3$8$t0Temporary Caller-saved$9$t1$10$t2$11$t3$12$t4$13$t5$14$t6$15$t7#NamePurpose$16$s0Temporary Callee-saved$17$s1$18$s2$19$s3$20$s4$21$s5$22$s6$23$s7$24$t8Temporary Caller-saved$25$t9$26$k0Reserved for OS$27$k1$28$gpGlobal pointer$29$spStack pointer$30$fpFrame pointer$31$raFunction return addressThe MIPS ISA Register FileWhen writing assembly, these registers can be referenced by their address (number) or name General purpose and special purpose registers

1212The MIPS ISA Register FileThere are other registers !Not directly accessible (no address)PC: Program counter Instruction sequencing LO and HIUsed with multiplication and division instructions 13PCLOHI32 bits13The MIPS ISA - InstructionsDifferent categories Arithmetic, logical, memory, flow controlAll instructions are encoded in binary using 32 bits (Fixed Size!!!) Three different formats depending on the number and type of operands, and operationR-type I-type J-type Instruction encoding Opcode operation code that specifies the operation in binary Operands the ins and outs of the instruction

1414Arithmetic instructions

The MIPS ISA - Instructions15A = B + C F = C - AADDA, B, C SUBF, C, A ADD$s0, $s1, $s2 #$s0 = $s1 + $s2 SUB$t2, $s6, $s4 #$t2 = $s6 - $s4 OperationDestination, Source1, Source2destination source1 op source2 Each arithmetic instruction performs one operation Each instruction has three operands The operands are in the file registers of the datapath The order of operands is fixed15Arithmetic instructions

The MIPS ISA - Instructions16Example 1. Given the following piece of C code, find the equivalent assembly code using the basic MIPS ISA given so far.a = b c d = 3 * a Solution: assume that the variables a, b, c, and d are associated with registers $s0, $s1, $s2, and $s3, respectively, by the compiler.

sub $s0, $s1, $s2 # $s0 contains b c add $s3, $s0 ,$s0 # $s3 contains 2*aadd $s3, $s3, $s0 # $s3 contains 3*a

16Arithmetic instructions

The MIPS ISA - Instructions17Example 2. Given the following piece of C code, find the equivalent assembly code using the basic MIPS ISA given so far.

f = (g + h) (i + j)

Solution: assume that the variables f, g, h, i, and j are associated with registers $s0, $s1, $s2, $s3, and $s4, respectively, by the compiler.

add $t0, $s1, $s2 # $t0 contains g + h add $t1, $s3 ,$s4 # $t1 contains i + j sub $s0, $t0, $t1 # $s0 contains (g+h) (i+j)

More efficient translation!???17The MIPS ISA - InstructionsArithmetic Instructions Machine LanguageAny instruction has to be encoded using 32 bits including the operation and its operands

18ADD $t0, $s1, $s4oprsrtrdshamtfunct655556op6-bitsopcode that specifies the operationrs5-bitsregister file address of the first source operandrt5-bitsregister file address of the second source operandrd5-bitsregister file address of the results destinationshamt5-bitsshift amount (for shift instructions)funct6-bitsfunction code augmenting the opcodeR-type18The MIPS ISA - InstructionsArithmetic Instructions Machine LanguageExample 3. What is the machine code for ADD $s0, $t0, $s419ADD $s0, $t0, $s400000001000101001000000000100000s6555560000 0001 0001 0100 1000 0000 0010 0000 B 0 1 1 4 8 0 2 0 H 19The MIPS ISA - InstructionsArithmetic Instructions Machine LanguageExample 4. What is the machine code for SUB $s1, $s2, $s320SUB $s1, $s2, $s300000010010100111000100000100010s6555560000 0010 0101 0011 1000 1000 0010 0010 B 0 2 5 3 8 8 2 2 H 20The MIPS ISA - InstructionsLogical Instructions AND, OR, NOROperation is performed between corresponding bits (bitwise)R-type instruction format

Example 5. What is the machine code for AND $s1, $t2, $s2op = 0x0 rs = $t2 = 0x0A rt = $s2= 0x12 rd = $s1 = 0x11 shamt = 0x00 funct = 0x24

21AND $s4, $s3, $t4 # $s4 = $s3 & $t4OR $s0, $t7, $s3 # $s0 = $t7 | $s3NOR $s2, $t6, $s3 # $s2 = ~($t6 | $s3)oprsrtrdshamtfunc0000000101010010100010000010010021The MIPS ISA - Instructions22Arithmetic and Logic Instructions with ImmediateIn many occasions, we encounter high-level statements such as X = Y + 5 Z = W 4 F = 514 x RIf (C>-3)

This implies that the operation is between a register and some constant !Can we do this with ADD and SUB instructions? Where do these constants come from?

MIPS ISA specifies a new set of instructions that deal with immediate data ADDI, ORI, ANDI, XORI,

22The MIPS ISA - Instructions23Arithmetic and Logic Instructions with Immediate

ADDI $t5, $s3, 130ADDIU$s1,$s2, 15oprsrtImmediate65516I-typeInstructionRegister FileSign Extension+1632Reg[rs]Immediate Addressing!23The MIPS ISA - Instructions24Arithmetic and Logic Instructions with Immediate

ANDI $t1, $t3, 12ORI$s3,$a0, 123oprsrtImmediate65516I-typeInstructionRegister FileZero Extension&1632Reg[rs]Immediate Addressing!24The MIPS ISA - Instructions25Arithmetic and Logic Instructions with ImmediateWhat if the immediate is greater than 16 bits?In MIPS, this is achieved in two steps using the Load Upper Immediate (LUI) and ORI instructions

Suppose we want to add the constant (0000 0010 0100 0010 0001 0011 1100 1100)2 to $s0

LUI$t0, 1000 1111 0001 0010 # loads the upper 16 bits of $t0 and sets the lower 16 bits to 0LUI$t0, (0000 0010 0100 0010)2 ORI$at, $t0, (0001 0011 1100 1100)225Memory instructionsMIPS ISA address bus is 32 bits, i.e. it can address up to 232 (4 G) locationsMemory width is usually 8 bits (byte) The MIPS ISA - Instructions268 bits0x00 00 00 000x00 00 00 010x00 00 00 020xFF FF FF FFMIPS CPU32-bitAddress Bus (32 bits)Data Bus (32 bits)ReadWrite26Memory instructionsMost memories are byte addressable !Every four consecutive locations (8 bits each) form a word (32 bits) !In other words, the addresses of two consecutive locations differ by 4 The MIPS ISA - Instructions278 bits0x00 00 00 000x00 00 00 010x00 00 00 020x00 00 00 030x00 00 00 040x00 00 00 050x00 00 00 060x00 00 00 070x00 00 00 080x00 00 00 090x00 00 00 0A0x00 00 00 0B0x00 00 00 0C0x00 00 00 0D0x00 00 00 0E32 bits0x00 00 00 000x00 00 00 040x00 00 00 080x00 00 00 0C0x00 00 00 100x00 00 00 140x00 00 00 180x00 00 00 1C0x00 00 00 2027Memory instructionsReading from memory requires specifying the address to read from and a register to store the read data Writing to memory requires specifying an address to write to and a register whose content will be written to memorySimple ! However, addressing a memory location requires 32 bits Where do these bits come from ?! Are they stored in memory?! Are they part of the instruction ?!

Displacement AddressingIn MIPS the address is formed by adding the content of some register (the base register) to 16-bit signed constant (offset or displacement) that is part of the instruction itself. The offset is sign-extended to 32 bits to match the size of the register. The MIPS ISA - Instructions28 A 16-bit field meaning access is limited to memory locations within a region of 213 or 8,192 words (215 or 32,768 bytes) of the address in the base register Note that the offset can be positive or negative

28Memory instructionsThe Load instruction reads 32 bit value (A word) into a register

The MIPS ISA - Instructions29lw $t0 , 4 ($s4)OperationDestinationBase RegisterOffsetReg[$t0] = MEM[Reg[$s4]+sign_extend(4)]Register File+InstructionMemorySign Extension1632323232offsetMemory DataRegister ContentAddress29Memory instructionsThe Store instruction writes the 32 bits (A word) found in a register into a memory location The MIPS ISA - Instructions30sw $t5 , -12 ($t1)NemunicDestinationBase RegisterOffsetMEM[Reg[$t1]+sign_extend(-12)] = Reg[$t5]Register File+InstructionMemorySign Extension1632323232offsetRegister ContentRegister ContentAddress30Memory instructionsThe memory is byte-addressable. However, the load and store instructions deal with words (4 bytes)!Reading from memory is effectively reading four bytes! How these bytes are ordered in the 32 bit register ?Storing to memory is storing 32 bits in four consecutive locations. What is the order by which these bits are stored in 4 different locations? Two approaches Little endian: the least significant byte is associated with the location of lowest address (Intel)Big endian: the most significant byte is associated with the lowest address (MIPS)The MIPS ISA - Instructions3131Reading a word from memoryThe MIPS ISA - Instructions320x100x330x430xFD0x00 00 00 F20x00 00 00 F30x00 00 00 F40x00 00 00 F58 bitsMemory0x100x330x430xFDRegisterLittle Endian32 bits0x100x330x430xFDRegisterBig Endian32 bitsByte 0Byte 1Byte 2Byte 3Byte 0Byte 1Byte 2Byte 332Memory InstructionsExample 7. Convert the following high-level statements to MIPS assembly languageG = 2 * FA[17] = A[16] + G

Solution assume that the variables F and G are associated with registers $s4 and $s5, respectively, and the base address of the array A is in $s0. All values are 32-bit integers.

add $s5, $s4, $s4 # $s5 contains 2*F lw $t0, 64($s0) # $t0 contains A[16] (note the offset is 64)add $t0, $t0, $s5 # $t0 contains A[16] + Gsw $t0, 68($s0) # store $t0 in A[17] (note the offset is 68)

The MIPS ISA - Instructions3333The MIPS ISA - InstructionsMemory Instructions - Machine Language

34lw $t0, 4 ($s4)sw $t2, -6 ($at)oprsrtOffset (displacement)65516op6-bitsopcode that specifies the operationrs5-bitsregister file address containing the base addressrt5-bitsregister file address of destination register (LW) or the source register (SW)Offset 16-bitsdisplacement or offset (number of bytes to move, positive or negative)I-typeHow far can we move in memory when using LW and SW?The offset is +2^15 -1 or -2^1534Memory Instructions

Example 6The MIPS ISA - Instructions35Machine code for lw $s5, 4($s1) in hexadecimalop = 0x23 rs = $s1 = 0x11 rt = $s5 = 0x15 offset = 0x0004

Machine code for sw $s0, 16($s4) in hexadecimalop = 0x2b rs = $s4 = 0x14 rt = $s0 = 0x10 offset = 0x00106 bits5 bits5 bits16 bitsOpcodersrtOffset10001110001101010000 0000 0000 010010101110100100000000 0000 0001 000035Memory InstructionsMIPS ISA defines memory instructions that can load/store bytes (8 bits) and half words (16 bits)

lb $t0, 1($s3) #load byte from memory (sign extention)lbu $t0, 1($s3) #load byte from memory (zeros extension)sb $t0, 6($s3) #store byte to memory

lh $t0, 1($s3) #load half word from memory (sign extension)lhu $t0, 1($s3) #load half word from memory (sign extension)sh $t0, 6($s3) #store half word to memory

When loading a byte into 32-bit register, where is it stored?Lower 8 bits of the register ! What about remaining bits?When loading a half word into 32-bit register, where is it stored? Lower 16 bits of the register ! What about remaining bits?How about sb and sh instructions?

The MIPS ISA - Instructions3636Memory Instructions

The MIPS ISA - Instructions370xD00xC30x430xFD0x00 00 00 F20x00 00 00 F30x00 00 00 F40x00 00 00 F58 bitsMemory0x000x000x000xD0$s032 bitsByte 0Byte 1Byte 2Byte 3LBU$s0, 2 ($s4) # assume Reg[$s4] = 0x00 00 00 F00xFF0xFF0xFF0xD0$s032 bitsByte 0Byte 1Byte 2Byte 3LB$s0, 2 ($s4) # assume Reg[$s4] = 0x00 00 00 F00x300x040x00 00 00 F00x00 00 00 F1What if the instructions are LH and LHU?LHU $s0 = 0x 00 00 D0 C3LH $s0 = 0x FF FF D0 C337Flow Control InstructionsInstructions are loaded in memory!The normal execution of programs is sequential; one instruction after another! Keeping track of execution is done through a special register called the Program Counter (PC)32 bits (Why???) It is incremented automatically by 4 (why!) after an instruction is fetchedThus, its contents always holds the address of the next instruction! It is not directly accessible !!! (Why)However, in our programs, we often write statements that skip some parts of the program, conditionally or unconditionally !! (IF, SWITCH, WHILE, GOTO )How is this implemented in the hardware !?The MIPS ISA - Instructions381) The address bus is 32 bits 2) MIPS instructions are 32bits; each instruction takes four bytes !3) The program counter register has no register address!

38Flow Control InstructionsHow to skip instructions in memory to execute others? Basically, this requires using instructions that change the contents of the PC to point to the address where the target instructions are loaded (branch/jump address)!In MIPS, there are no instructions that can modify the PC directly! Alternatively, we have two conditional and three unconditional flow control instructions!These instructions can change the contents of the PC indirectly!The MIPS ISA - Instructions3939Conditional Flow Control InstructionsBranch If Equal Instruction (BEQ) Checks if two registers are equal! If true, then the PC (containing the address of next instruction) is incremented or decremented by adding a signed 16-bit offset (that is part of the instruction) after it is multiplied by 4 (WHY?). If false, program execution continues normally from the address in PC. This is called PC-relative addressing!The MIPS ISA - Instructions40BEQ $t0 , $t1, 15OperationTested RegistersOffsetWhy the offset specifies the number of instructions instead of bytes although the memory is byte addressable? In this way we can skip more instructions (2^15 -1 or -2^15)40Conditional Flow Control InstructionsBranch If Equal Instruction (BEQ)

The MIPS ISA - Instructions41PCReg1Reg2Instruction=?x4MUXSign Extension+Address of instruction following BEQBranch AddressBEQ.MEM.16 bit offset32 bit instruction from branch address (two registers are equal)32 bit instruction next to BEQ (Two registers are not equal)41Conditional Flow Control InstructionsBranch If Not Equal Instruction (BNE) Checks if two registers are not equal! If true, then the PC (containing the address of next instruction) is incremented or decremented by adding a signed 16-bit offset (that is part of the instruction) after it is multiplied by 4 (WHY?)). If false, program execution continues normally from the address in PC. This is called PC-relative addressing!The MIPS ISA - Instructions42BNE $t0 , $t1, -23OperationTested RegistersOffset42Flow Control Instructions (Conditional)Branch If Not Equal Instruction (BNE) The MIPS ISA - Instructions43PCReg1Reg2Instruction=?x4MUXSign Extension+Address of instruction following BNE Branch AddressBNE.MEM.16 bit offset32 bit instruction from branch address (Two registers are not equal)32 bit instruction next to BNE (Two registers are equal)43Flow Control InstructionsExample 8. Convert the following high-level statements to MIPS assembly languageif (x == y) x = x + y end

The MIPS ISA - Instructions44Solution assume that the variables x and y are associated with registers $s4 and $s5, respectively.

BNE$s4, $s5, 1# if $s5 ~= $s4, skip one instruction ADD$s4, $s4, $s5 # add x and y if they are equal

OR, we can use labels instead of counting how many instructions to skip!

BNE$s4, $s5, SKIP# if $s5 ~= $s4, skip one instruction ADD$s4, $s4, $s5 # add x and y if they are equalSKIP:.44The MIPS ISA - InstructionsFlow Control Instructions -Machine Language

45BEQ $t0, $t1 , 4 BNE $t2, $v1, -214oprsrtOffset (displacement)65516op6-bitsopcode that specifies the operationrs5-bitsfirst register file address to be comparedrt5-bitssecond register file address to be comparedOffset 16-bitsdisplacement or offset (number of instructions to skip, positive or negative!)I-typeHow many instructions can we skip when using BNE and BEQ? We can skip 2^15-1 or -2^15 instructions 2^17-1 or -2^17 bytes 45Conditional Flow Control InstructionsExample 9.Machine code for BEQ $s5, $s1, 20 in hexadecimal. op = 0x04 rs = $s5 = 0x15 rt = $s1 = 0x11 offset = 0x0014

Machine code for BNE $s0, $s1, -13 in hexadecimal op = 0x05 rs = $s0 = 0x10 rt = $s1 = 0x11 offset = 0xFFFD

The MIPS ISA - Instructions4600010010101100010000 0000 0001 010000010110000100011111 1111 1111 001146Conditional Flow Control InstructionsBEQ and BNE instructions can check for equality only? How about > , < , = ???There are no instructions such bgt, bls, bge, ble!!In MIPS ISA, this can be done with the aid of The Set On Less than Instructions (SLT and SLTU)Compares if one register is less than another one If so, a third register is loaded with 1 Otherwise, the third register is loaded with 0The $Zero register Register number zero Hardwired to zero Can be read only!

The MIPS ISA - Instructions4747Conditional Flow Control InstructionsSLT InstructionThe MIPS ISA - Instructions48SLT$s1, $s2, $s3#set $s1 if $s2 < $s3, else clear $s1$S2$S3-$s2-$s3