Akhila P Das

Asst. Professor

Department of Electronics & Communication

Aryanet Institute of Technology

Most instructions have 2 operands-

destination & source

eg: MOV AX,BX

Both cannot be memory operands

Certain instructions have only 1 operand

eg: DIV BX

Instructions with no operands

eg: CLC

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Data transfer instructions

Arithmetic instructions

Logical instructions

String manipulating instructions

Control transfer instructions

Processor control instructions

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Transfer data/address into registers, memory

locations and I/O ports

Generally involve 2 operands: source &

destination, both of which should be of same

size

MOV AX, 1504h

MOV [1504], AX

MOV AX, [1504]

Both source and destination cannot be

memory locations

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Used to perform addition, subtraction,

multiplication & division.

The source and destination operand should

be of same size except for division.

Performing arithmetic operation directly on 2

memory data is not possible.

Arithmetic instructions alter the flags of

8086.

Flags reflect the status of result.

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Result is stored in destination register or memory except in case of CMP (compare) instruction

CMP AX,BX: AX-BX is performed and used to alter the CF. Result is then discarded.

If AX>BX, CF=0 else CF=1

ADD AX,BX

ADC CX,[1500]

SUB CX,0145h

MUL BX

DIV [1600]

NEG AX: replaces AX with 2’s complement

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Used for performing AND, OR, XOR,

complement, shift and rotate operations.

Alters flags.

AND AX,BX

OR CX,[1290]

XOR [1300],DX

TEST CX,DX: contents are ANDed and result is

used to modify flags, but register contents

remain unaltered.

NOT AX: I’s complement

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SHL/SAL AX, 1 SHR AX,1

SHL/SAL AX, CL SHR AX,CL

SAR AX, 1: MSB is retained

CF contains last bit shifted out

ROR AX, 1: LSB is moved to both CF and MSB

RCR AX,1: LSB moved to CF and CF moved to

MSB

Similarly ROL & RCL

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A string is a sequence of bytes or words

Instructions end with SB or SW

Alters flags

All instructions have implied source and destination operand

MOVS & CMPS : source is in data segment memory & destination is in extra segment memory

STOS & SCAS: source is AX and destination is in extra segment memory

LODS: source is in data segment memory and destination is AX

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Offset of source operand is stored in SI and that of destination is stored in DI.

On execution of string instructions SI & DI are automatically updated to point to next word or byte, based on DF

If DF=0, incremented by 1 for byte and incremented by 2 for word(16 bits)

If DF=1, decremented by 1 for byte and decremented by 2 for word

Eg: MOVSB : 1 byte of data in data segment (address in SI) is copied to extra segment (address in DI). SI & DI are incremented/ decremented by 1 depending on DF

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Consists of call, jump, loop and software

interrupt instructions.

Normally a program is executed sequentially.

When a branch instruction is encountered

the program execution control is transferred

to target instruction.

If IP alone is modified, target instruction is in

same segment

If IP & CS are modified, target instruction is

in another segment

Do not affect flags.

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Eg: CALL BX

SP decremented by 2

IP pushed to stack

Content of BX is loaded in IP

RET

Content of top of stack is transferred to IP

SP is incremented by 2

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Includes instructions to set or clear CF, DF

and IF.

It also includes HLT, NOP, LOCK and ESC

instructions which controls the processor

operation

CLC: clears CF

STC: sets CF

HLT: terminate a program

WAIT: enters idle state until 𝑇𝐸𝑆𝑇 pin goes

low

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