inria, evaluation of theme tem · 2013-06-10 · rabie ben atitallah, external collaborator,...

INRIA Evaluation of Theme TEM

Project-team DaRT

March 2012

Project-team title DaRT

Scientic leader Jean-Luc Dekeyser

Research center Lille - Nord Europe

Common project-team with LIFL (UMR 8022 Universiteacute Lille 1CNRS Universiteacute Lille 3)

1 Personnel

Personnel (April 2007)

Misc INRIA CNRS University Total

DR (1) Professors 2 2

CR (2) Assistant Professors 1 3 4

Permanent Engineers (3)Temporary Engineers (4) 2 2

PhD Students 7 2 1 10

Post-Doc 2 2

Total 7 6 1 6 20

External Collaborators 1 1

Visitors (gt 1 month) 1 1 2

(1) Senior Research Scientist (Directeur de Recherche)(2) Junior Research Scientist (Chargeacute de Recherche)(3) Civil servant (CNRS INRIA )(4) Associated with a contract (Ingeacutenieur Expert or Ingeacutenieur Associeacute)

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Personnel (March 2012)


DR Professors 1 1

CR Assistant Professor 1 3 4

Permanent EngineerTemporary Engineer

PhD Students 8 1 9

Post-Doc 1 1

Total 8 3 4 15


Visitors (gt 1 month)

Changes in sta

DR Professors Misc INRIA CNRS University totalCR Assistant Professors

Arrival 1 4 5Leaving

Comments The changes concern the period until December 2011 University ofLille 1 enrolled 4 assistant professors Vlad Rusu joined DaRT by moving from InriaRennes The new team DaRT was created in January 2012 for one year and PierreBoulet Abdoulaye Gamatieacute Cedric Dumoulin Anne Etien Julien Forget and LaureGonnord are still members of LIFL

Current composition of the project-team (March 2012)

bull Vlad Rusu CR1 Inria Scientic leader

bull Jean-Luc Dekeyser Professor Lille 1

bull Freacutedeacuteric Guyomarch Associate Professor Lille 1

bull Philippe Marquet Associate Professor Lille 1

bull Samy Meftali Associate Professor HdR Lille 1

bull Rabie Ben Atitallah External Collaborator Associate Professor Universiteacute deValenciennes et du Hainaut Cambreacutesis (UVHC)

bull Christophe Calves Post-Doc Researcher Inria

bull George Afonso PhD Student Lille 1 Cifre EADSEurocopter

bull Sana Cherif PhD Student Lille 1 ANR Famous

bull Majdi Elhaji PhD Student co-advising Lille 1FSM Monastir

bull Hana Krichen PhD Student co-advising Lille 1ENIS Sfax

bull Santhosh-Kumar Rethinagiri PhD Student UVHC ANR OpenPeople

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bull Chiraz Trabelsi PhD Student Lille1 Inria Cordis

bull Venkatasubramanian Viswanathan PhD Student UVHC Cifre Nolam EmbeddedSystems

bull Pamela Wattebled PhD Student co-directed Universiteacute Bretagne SudLille 1ANR Famous

bull Andrei Arusoaie PhD Student co-directed University of Iasi Roumania

Current position of former project-team members (including PhD stu-dents during the (2007-2011) period)

bull Pierre Boulet Professor Lille 1 LIFL

bull Abdoulaye Gamatieacute CR CNRS LIFL

bull Julien Forget Associate Professor Lille 1 LIFL

bull Laure Gonnord Associate Professor Lille 1 LIFL

bull Ceacutedric Dumoulin Associate Professor Lille 1 LIFL

bull Anne Etien Associate Professor Lille 1 LIFL

bull Thomas Legrand INRIA engineer at start-up Axellience

bull Alexis Muller CEO spin o Axellience

bull Rahma Yengui Temporary Engineer Inria Non-A Team

bull Jean-Marie Mottu Post-Doc Associate Professor Nantes

bull Rosilde Corvino Post-doc Eindhoven Technical University The Netherlands

bull Wendell Rodrigues PhD January 2012 Associate Professor Federal Institute ofCearaacute Brazil

bull Vincent Aranega PhD November 2011 ATER Lille 1

bull Hajer Chtioui PhD December 2011 co-advising UVHCENIS Tunis

bull Adolf Abdallah PhD 2011 lecturer at Saint Joseph University in BeyrouthLebanon

bull Yassine Aydi PhD 2011 CROUS Director Sfax Tunisia

bull Mouna Baklouti PhD 2010 Assistant Professor Sfax Tunisia

bull Ali Koudri PhD 2010 Engineer at Thales

bull Imran Raq Quadri PhD 2010 Independent consultant currently working forSofteam

bull Calin Glitia PHD 2009 Engineer at Softeam France

bull Julien Taillard PhD 2009 RampD Responsible for Alicante France

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bull Huafeng Yu PhD 2009 postdoc INRIA Espresso Rennes

bull Ceacutesar Moura Post-Doc 2007-2008 Associate Professor Federal Institute of CearaacuteBrazil

bull Safouan Taha PhD 2008 Associate Professor Supelec Paris

bull Antoine Honoreacute Engineer 2005-07 Vade Retro Technology Hem

bull Eacuteric Piel PhD 2007 Software architect at Delmic Netherlands

bull Seacutebastien Le Beux PhD 2007 Associate Professor Lyon

bull Amine El Kouhen PhD Student University Lille 1 co-advising Lille 1CEA

bull Amen Souissi PhD Student University Lille 1 CIFRE thesis with Ecreall

bull Souha Kamoun PhD student 2007-2010 Engineer at Ansaldo STS

bull Nicolas Wojcik PhD student 2008-2009 CEO of startup 9h37

bull Mohamed Fellahi 6 month Post-doc in 2010-2011 back to Algeria

Last INRIA enlistments

bull Vlad Rusu 2010 CR1 Transfer From Rennes Vertecs Team

Other comments

The new DaRT team was created in January 2012 with a new leader Vlad Rusu CR1Inria This team is composed of a subset of the members of the DaRT team underevaluation The other former members of the DaRT team till 2011 are pursuing theirresearch in the LIFL UMR 8022 of University Lille 1 CNRS and University Lille 3

Thanks to the DaRT project Jean-Luc Dekeyser Samy Metftali and Philippe Mar-quet obtained the PES (prime dexcellence scientique)

2 Work progress

21 Keywords

Embedded Systems Data Parallelism Model Driven Engineering HardwareSoftwareCodesign Dynamic Reconguration

22 Context and overall goal of the project

Since its creation (December 2004) the DaRT project contributes to the eld of soft-ware and hardware co-design for data-intensive embedded systems by focusing on thefollowing three research axes

bull Co-modeling for HPSoC design (High Performance System on Chip)

bull Optimization and compilation techniques

bull HPSoC simulation and synthesis

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Gaspard2 Environment

Design Time

Application ArchitectureAllocation

refactoring

Deployed

Transformation Engine

IP

Transformation Chains

Target P latforms

OpenMP

Pthread

VHDL

OpenCL

Synchro

System C

TRACEABILITYLOGGING

Figure 1 Gaspard2 co-design environment

All our results and developments are integrated in the Gaspard2 framework Fig-ure 1 shows in a synthetic way the architecture of Garspard2 with its three partsdesign compilation based on model transformations and target platforms

These last four years we were going to integrated dynamicity in almost all themetamodels of Gaspard2 Special attention was also devoted to massively parallelsystems mapped on FPGA

23 Objectives for the evaluation period

The following items describe the objectives that were given on the occasion of the lastevaluation of the project

Co-modeling for HPSoC design objectives

Our objective on this theme is to dene metamodels to specify application architectureand (software hardware) association These metamodels present new characteristics ashigh level data parallel constructions iterative dependency expression data ow andcontrol ow mixing hierarchical and repetitive application and architecture modelsAll these metamodels are specied using EMF Some of them are also representedas UML proles This last two years a special eort of standardization was doneAn on going answer to the OMG request for proposal called MARTE is integratingsome results of the DaRT project Arnaud Cuccuru thesis was the rst proposal of therepetitive concepts and Safouan Taha thesis (in collaboration with CEA) is introducingthe hardware concepts Both are today included in the Gaspard Environment

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Optimization and compilation techniques objectives

Here the rst concern is the development of automatic transformations of data parallelconstructions They are used to map and to schedule an application on a particulararchitecture This architecture is by nature heterogeneous and appropriate techniquesused in the high performance computing community can be adapted New heuristicsto minimize the power consumption must be developed This new objective implies tospecify multi criteria optimization techniques to achieve the mapping and the schedul-ing

The second concern is the co-compilation process from high-level models down tosimulation execution or synthesis code The design choice was to use model transfor-mation techniques to achieve this goal

HPSoC simulation and synthesis objectives

In order to validate the architecture model and the mapping of the application onit we propose the usage of the de facto standard SystemC platform to simulate theHPSoC design at dierent abstraction levels This simulation allows us to verify theadequacy of the mapping and the system performances (communication delay loadbalancing memory allocation) We also support IP (Intellectual Property) reuse andintegration at dierent specication levels such as Programmers View (PV) TimedProgrammers View (PVT) and Cycle Accurate Bit Accurate (CABA) levels Theobjective is to oer a multi-level Design Space Exploration (DSE) environment to dealwith the large number of architectural solutions in such systems To do so our proposalis to rene the architectural space from higher to lower level until converging to theadequate solution Furthermore a reliable and a fast DSE of HPSoC needs a set oftools for estimating performance and power in the design ow In order to increasethe design productivity our aim is also to generate automatically the HPSoC SystemCcode from the high level specication (MARTE model) In addition we plan to convertan UML model of an intensive signal processing algorithm into a VHDL representationsuitable for a hardware based implementation via the synthesis process The objectiveis to target heterogeneous HPSoC gathering GPPs (General Purpose Processor) andhardware accelerators to address specic application requirements

Evolution of these objectives during the evaluation period

Technological development chips have opened new research challenges In particularthe recent and future FPGA oer rate of integration which allows to map a large numberof processors on it In addition dynamic and partial recongurations allow on the yto rethink the architecture according to the changing behavior of the application Thesehardware solutions have inuenced our new research axes toward dynamic models atthe application architecture association and deployment levels These consequenceswill be visible in the following result statements We derived four axes which includeour contributions

bull From static to dynamic model for codesign

bull Consolidation of embedded system MDE design

bull Improvement of hardwaresoftware simulation techniques

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bull Dynamic reconguration and massive parallelism

24 From static to dynamic model for codesign Executive summary

241 Personnel

Permanent researchers Pierre Boulet Jean-Luc Dekeyser Julien Forget AbdoulayeGamatieacute Freacutedeacuteric Guyomarch Philippe Marquet and Samy Meftali (defended HDRthesis) Defended PhD theses Adolf Abdallah Seacutebastien Le Beux Imran QuadriWendell Rodrigues Safouan Taha Julien Taillard and Huafeng Yu Ali Koudri On-going DaRT PhD theses Sana Cherif Majdi Elhaji and Chiraz Trabelsi

242 Project-team positioning

There is a large community of people using the Synchronous Data Flow model of compu-tation and its extensions to study the development of data ow embedded applications(the Ptolemy Group of E Lee at UC Berkeley the Daedalus project of A Pimentelat Univ Amsterdam the group of O Dforge and J-F Nezan at IETR Rennes) Aswe have shown in [J18] our approach is better suited in the case of multidimensionalsignal processing applications

The INRIA teams we have relations with are Aoste Cairn Espresso Parkas andSardes We share with them a background and interest in languages for embeddedapplications and more specically synchronous languages Our specicity is once againour focus on multidimensional signal processing applications

The group that shares a lot of our philosophy of language design is the group ofS-B Scholtz at the Univ of Hertfordshire UK but they do not study the hardwareor co-design part of the embedded systems design They focus solely on the languageand its compilation on various platforms

Concerning the modeling community most eorts on the applications we are inter-ested in have happened around the MARTE standard UML prole we were involvedin In this context we have collaborated particularly with the INRIA Aoste team theCEA List and Thales

243 Scientic achievements

Extensions of our MoC for control modeling Adaptivity is an important featureof modern embedded systems such as mobile devices in which quality-of-service iscrucial Such systems must consider various execution modes according to changesin functionality execution resources and environment Describing adaptive embeddedsystems in our codesign framework [J14] requires an extension of the repetitive MoCwith nite state machines We proposed a generic extended model usable at all SoCco-design levels [I5] software application hardware architecture association of bothand nally deployment This model is inspired by mode automata and is one of therst propositions in literature mixing multidimensional dataow with control It hasbeen experimented in discrete control synthesis for multimedia applications [C53] andthe generation of hardware accelerators for dynamic reconguration on FPGAs [J25]In the FAMOUS ANR project it is currently considering as a possible extension of theMARTE prole referred to as Recongurable MARTE (RecoMARTE) [C30]

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Interaction between data dependences and time The data dependencies ex-pressed within the repetitive MoC only dene a partial ordering concerning a systemexecution scheduling In order to describe a complete scheduling involving executionplatform or environment requirements we proposed to rene data dependency speci-cations [J19] with abstract clock constraints expressed with the MARTE Time conceptsand CCSL language [C1] These constraints explicitly capture the suitable informationabout environment and execution platform properties of systems eg inputoutputdata and application components activation rates processor frequencies Then a hard-waresoftware allocation is dened based on a clock projection algorithm The resultis a clock trace reecting simulation scenarios for a system which serve for an easy andrapid design assessment wrt metrics such as execution time or energy consumption[C49] It can also be considered for correctness analysis with the synchronous reactiveapproach [J17]

NoC topologies and video coder modeling and mapping using MARTE Asa continuation of our work on modeling at system level a methodology for modelingconcepts of NoC-based architectures is proposed especially the modeling of all kindsof topologies (regular irregular or hierarchical) and routing algorithms [C44] Thiscontribution includes a VHDL code generation On the other side we proposed aVLSI implementation of a new NoC topology modeling called diagonal mesh that itdesigned to oer a good trade-o between hardware cost and theoretical quality ofservice (QoS) [C68] This NoC is based on a new router architecture called FeRoNoC(Flexible extensible Router NoC) In addition to this an H264 application has beenmodelled and mapped on the proposed NoC

Modeling for Scientic Computing The Gaspard2 framework has many targetlanguages among them OpenMP and OpenCL to generate programs which can be exe-cuted on quite powerful workstations We created then a methodology to design appli-cations for scientic computing and applied it on a software called Code_CARMELused for electromagnetic simulations We modelled the heaviest part of CARMEL interm of computational time and generated an OpenCL code interfaced with the originalsoftware On an industrial case (a car alternator provided by Valeo) we got speed-upbetter than 9 on the full computation (including the sequential part)

244 Collaborations

Extensions of our MoC for control modeling Academic INRIA Sardes (9publications) CEA List

Interaction between data dependences and time Academic INRIA Aoste (1journal publication under submission)

NoC topologies and video coder modeling and mapping using MARTEAcademic Faculteacute des Sciences de Monastir Tunisia

Modeling for Scientic Computing Academic University of Hertfordshire UK(1 publication) L2EP lab Lille (2 publications) Industry Valeo EDF

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245 External support

FAMOUS Open-PEOPLE OpenEmbeDD Nano2012 ID-TLM ARC Triade Euromed3+3

246 Self assessment

Best paper award Adolf Abdallah Abdoulaye Gamatieacute and Jean-Luc Dekeyser Cor-rect and Energy-Ecient Design of SoCs the H264 Encoder Case Study Interna-tional Symposium on System-on-Chip (SoC2010) September 2010 Tampere Finland

There are several embedded applications that process huge multidimensional arraysaccording to more or less complex control ow eg in digital imagevideo processingelectromagnetic waves This naturally calls for a tight mix of suitable MoCs as inPtolemy to describe the whole aspects of systems A strong point is that our extensionsof the repetitive MoC combines the benets of repetitive structure modeling abstractclocks and nite state machines to permit an early design space exploration at a highabstraction level This extension has been studied with the aim to be integrated withinthe MARTE standard of the OMG We also shown that early optimisation could leadto good performances at low cost during the generation phase

The main weakness of our contribution in this research axis is its low impact in termsof usage by others due to the absence of a complete programming model infrastructure(eg including readily usable codelibraries) that facilitates its adoption by developersAnother weak point is the specicity of our metamodel originally designed for signalprocessing applications it lacks exibility to handle easily sparse computations neededin many numerical simulations

Based on our results we will pursue new research directions both in the contextof the DaRT team of Inria and the Eacutemeraude group of LIFL The Eacutemeraude groupwill work towards models of computation for mobile applications on post-Moore ar-chitectures This will include soft real-time and even more dynamic applications thanthose we have studied already DaRT team is now working on lower level of abstractionto specify massively parallel hardware and software VHDL specications machinelanguage and assembly language and DSL (See Section 5)

25 Consolidation of embedded system MDE design Executive sum-mary

251 Personnel

Permanent researchers Pierre Boulet Ceacutedric Dumoulin Anne Etien AbdoulayeGamatieacute Laure Gonnord Freacutedeacuteric Guyomarch Vlad Rusu Defended PhD the-ses Vincent Aranega Calin Glitia Ongoing DaRT PhD theses Andrei Aru-soaie Other ongoing PhD theses Amine El Kouhen Amen Souissi PostdocsChristophe Calves Rosilde Corvino Jean-Marie Mottu Ceacutesar Moura


We include in this section several lines of work dealing with model driven engineering(MDE) methods and tools in general and with their application to the design of em-bedded systems We also include works related to embedded-system design that arebased on models even if they do not necessarily t in the MDE canon

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Regarding MDE tools we have worked on the customization of the UML modelingtools within the Papyrus UML toolset co-developed with the CEA Atos and Airbus andwidely deployed thanks to its inclusion in the Eclipse project The main competitorsare commercial tools with limited customization capabilities

Regarding MDE methods we have focused on model transformations and on oper-ational semantics of Domain-specic Modeling Languages (DSMLs) In [E18] Guerraet al argue that model transformations like other software engineering artefacts mustbe systematically designed and implemented Other research has also argued thatfocusing on the engineering of transformations and improving scalability maintain-ability and reusability of transformations is now essential to improve the uptake ofMDE [E38 E54] and to make transformations practical and capable of being system-atically engineered [E9] Various mechanisms have been proposed to build compositetransformations from reusable transformations [E43 E53 E36 E47] Nevertheless noindication on the characteristics of the transformations or on the way to practicallyreuse transformations are provided

In other works model transformations have been proposed by groups from the uni-versities of Maacutelaga [E44] and Leicester [E4] as means to endow DSMLs with formaloperational semantics The relevance of DSMLs in our setting is that the Gaspard2 ab-straction levels can be seen as DSMLs and providing them with operational semanticsis important for their understanding and opens the way to formal verication

Finally concerning our methodology for embedded system design we have addedsome design space exploration methods at a very high abstraction level A few groupshave studied this problem recently [E35 E42 E3 E49 E29] with a more general focusthan ours Indeed our proposals can uniquely exploit the regularity of the applicationand the hardware but target a more restrictive application domain

Our work on static analysis on sequential programs is in the continuity of [E14] or forsynchronous programs [E48] The originality here is to discover new applications in thecompilation process (code generation) or combining methods (abstract interpretationacceleration and SMT solvers) to improve the precision


All our contributions in this section are intended to improve Gaspard2 starting from theversion that was the result of three theses defended early in the evaluation period [T8T9 T5]

Improvement of MDE methods and tools To help embedded system designerswe have been working on a development environment that automatically adapts itselfto the users domain To this end we are involved in the Papyrus project (httpwwweclipseorgpapyrus see section 32) dedicated to building an open source UMLmodeler Papyrus is partially generated from models describing a users UML diagramsthis distinguishing feature makes it adaptable to the users design and developmentphase

In the previous version of Gaspard2 model transformations were complex andmonolithic We proposed to decompose complex transformations into smaller ones(called localized transformations) jointly working in order to build a single outputmodel [C45] in order to ease reusability and maintainability New transformation chainstowards pThread SystemC and OpenCL have been dened in Gaspard2 using localized

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transformations They share almost 80 percent of the transformations with the oldestchain Traceability based algorithms ease the model transformation debug [C11 C12]

We have also worked on the formalization of operational semantics for DSMLs(Domain-Specic Modeling Languages) Indeed each Gaspard2 abstraction level canbe seen as a DSML In [C93 J10 J28 C94 C95 J27] we have formalized the variousMDE artefacts involved in the denition of DSMLs by mapping them to rewritingsystems which can then be used for verifying (i) that a DSML instance conforms toits metamodel (ii) temporal properties on a DSMLs operational semantics and (iii)operational semantics-preservation by transformations between DSMLs The rst twoanalyses were implemented in a prototype tool [C94] We have also studied the tracingof counterexamples of model checkers to the operational semantics of a DSML in orderto explain them in the domain experts language [C35] Finally we have developed arewriting-based denition of the Kermeta metamodeling language [E34] in order toenable the formal verication of Kermeta programs

Improvement of the methodology for embedded system design In order tooptimize the models and consequently the generated code we oer software executionfeedback to model designers based on models transformation traceability [C10] Thesefeedbacks enable the designers to tune their models in order to improve the softwareperformances even if they do not have in-depth knowledge on the running platform

We also have several contributions towards design space exploration We haveenhanced our refactoring toolkit in order to support the optimization of a larger classof applications including those mixing multidimensional data dependences and controlby the way of uniform inter-repetition dependences [T7 C56] We have given guidelinesfor the usage of this toolkit to support an assisted design space exploration [J19] andwe have used this toolkit to automatically explore the design space for a restrictedclass of architectures [I3 I4] Some advances have also been made on a more generaldesign space exploration algorithm based on a multi-objective genetic algorithm [J6C25 C24]

Finally we have also studied the analysis of C source code which is the rst steptoward the verication of functional properties of the (nal) generated code We havechosen to use static analysis to automatically discover numerical invariants of programs[C71] in order to better understand their behavior and also improve the quality of thegenerated code via dead code elimination [I6]

254 Collaborations

Improvement of MDE methods and tools Academic INRIA Triskell (1 pub-lication) CEA LIST Saclay (1 thesis Papyrus development) University of Bor-deaux 1 (1 publication) University of York York UK (2 publications) Univer-sidad of los Andes Bogota Colombia (2 publications) University of Madrid (2publications) University of Iasup3i Romania (1 publication and a co-supervision ofa PhD student) Industrial Thales RampD ATOS Airbus (Papyrus development)

Improvement of the methodology for embedded system design VerimagGrenoble (1 publication) TU Eindhoven (1 publication) University of OranAlgeria (3 publications)

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OpenEmbeDD TerOps STIC Algeacuterie theses founded by CIFRE (Ecreall) and CEAExplorer Program and support from LIFL (2010) BQR Funding (Univ Lille) (2011)both as emerging activities

256 Self assessment

All the results presented in this section are related to Gaspard2 However some ofthem required exploratory theoretical research with the consequence that at this timethey are not mature enough to be incorporated in the Gaspard2 toolset

One of the main evolutions of our work is that the development of Gaspard2 willstop Indeed we have shown that using MDE techniques to build a co-design envi-ronment was possible but our scientic directions go away from co-modeling and wedont have the resources to maintain Gaspard2 in the long term We were probablytoo ambitious with the Gaspard2 tool too many compilation targets and concurrentdevelopment of metamodels model transformation technologies and compilation tech-niques both producing a very moving code base that lead to integration diculties(and very interesting software engineering problems)

Improvement of MDE methods and tools We have been involved in the de-velopment of Papyrus an open sources customizable design tool The Papyrus projectis a leading UML 2 tool widely spread as Eclipse project This tool relies itself onMDE technology and is automatically generated from models Nevertheless it can benoticed that the project is now very large and requires a time-consuming maintenancein particular to extend the automatic generation from models These works continue inLIFL through Amine El Kouhens thesis co-supervised by Cedric Dumoulin and PierreBoulet

Using localized transformations in the new version of Gaspard2 has increased thereusability testability and maintainability of the existing transformation chain andhas simplied the development of new ones Based on these encouraging results atransfer of the transformation orchestration engine to Axellience an INRIA start-upis in progress Unfortunately this new approach is not currently used outside the teamA large eort of dissemination towards the academic and industrial communities hasbegun Anne Etien will pursue this work within LIFL

The works on the formal semantics of DSMLs have lead to a substantial numberof publications and to a research prototype However at this time they are not ma-ture enough to be included in Gaspard2 They will be continued along two lines Therst one is the PhD thesis of Andrei Arusoaie co-supervised with Dorel Lucanu fromthe University of Iasi and will consist in extending the formal validationvericationpart to semi-guided scenario executions and to the verication of Hoare-style asser-tions The second one is the use of formal rewrite-based semantical frameworks forexecutableveriable denitions of domain-specic languages for dynamically recong-urable massively parallel architectures which is part of our objective for the next fewyears (cf Section 5)

Improvement of the methodology for embedded system design We providein Gaspard2 the rst proling system based on generated code execution feedbacksto the models It relies on traceability mechanisms and an expert system This latter

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takes into account only occupancy It could be relevant to take other non functionalrequirements into account and for example manage multi objectives These worksstopped with the defenses of Vincent Aranega and Wendell Rodriguez

Our work on design space exploration has produced a complete refactoring toolboxfor intensive applications This toolbox has been used successfully for (semi-)automateddesign space exploration taking into account both task and data parallelism The weakpoint of this approach is that it is too limited in its application In complement thegenetic algorithm based approach has proven dicult to adapt to our hierarchical data-parallel model Both approaches suer from the diculty to have accurate estimationsof the performance of the components of the application and due to a lack of resourceswe have not been able to use SystemC simulations as performance evaluation functionsIn the future we will shift our works towards dynamic adaptation at run-time usingdynamic reconguration or middleware techniques

The improvement of static analysis for synchronous languages and sequential lan-guages have shown its relevance in the development of critical embedded systems evenif it has not been integrated in the Gaspard environment In the future the work willcontinue in the LIFL (Eacutemeraude Group) mainly in two directions we will study thecombination of static and dynamic analyses to improve the compilation process andalso take into account more realistic constraints such as real-time constraints

26 Improvement of hardwaresoftware simulation techniques Exec-utive summary

261 Personnel

Permanent researchers Jean-Luc Dekeyser Samy Meftali Philippe Marquet andRabie Ben Atitallah (External collaborator) Defended PhD theses Eacuteric PielSeacutebastien Le Beux Rabie Ben Atitallah and Hajer Chtioui Ongoing DaRT PhDtheses Santhosh-Kumar Rethinagiri


Simulation models and Tools In the past decade commercial tools have succeededto provide conventional RTL and Cycle Accurate simulation environments for low-levelsystem prototype This approaches were very useful allowing engineers to keep theirtraditional view of the system However tools at low-level cannot adequately supportthe complexity of future MPSoC since they are too slow for a meaningful executionof the software In an attempt to reduce simulation time research eorts have beenput to evaluate the system at higher abstraction levels SystemC [E37] and SystemVer-ilog [E22] are examples of hardwaresoftware languages which aim to be used for systemlevel design The last few years Transaction Level Modeling (TLM) [E5] has been em-braced as a primary solution to make the system description easier and the simulationfaster The SoCLib [E51] library provides an MPSoC simulation environment at timedTLM level using Instruction Set Simulator (ISS) In our work while the hardware isalso simulated at the TLM level we introduced the virtual processor concept to executethe application tasks in an abstract way allowing higher simulation speed-ups

System level power estimation Power estimation at the TLM level is still un-der research and is not well established In [E11] and [E27] a methodology is presentedto generate consumption models for peripheral devices at the TLM level The charac-

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terization of the power models is done at the gate level Using this approach for recentprocessors and systems is not realistic Power modeling methodology based on a ne-grain activity characterization at the gate level needs a considerable development timeand leads to a high correlation with data To overcome this drawback Laurent [E26]et al proposed the Functional Level Power Analysis (FLPA) methodology that wassuccessfully applied on building high-level power models for dierent hardware com-ponents Based on this methodology the tool Consumption Analysis Toolbox (CAT)[E12] was developed CAT gives relatively precise power estimation results in a shorttime Indeed only a static analysis of the code or a rapid proling are necessary todetermine the input parameters for the power models In order to rene the valueof sensible parameters in a reasonable delay we proposed to couple SystemCTLMsimulation with functional power modeling


The main challenge for the design of such dedicated tools is to achieve a better trade-obetween accuracy and speed

At the beginning of the evaluation period we developed the rst release of Gas-pard2 with the objectives to be full MARTE compliant and to generate SystemC andVHDL code The three rst contributions represent these eorts and were achievedin 20072008 with the three corresponding thesis Then we decided to enhance ourenvironment with power consumption models for a reliable design space explorationThis is done in accordance to the OpenPeople ANR project

Transactional level MPSoC simulation We have dened rst a generic execu-tion model that supports any type of shared memory MPSoC and a new VirtualProcessor (VP) based simulation technique was proposed for implementing the exe-cution model without using an Instruction Set Simulator (ISS) VP-based simulationwas implemented in SystemC at a timed transactional level allowing a good trade-obetween high simulation speed and performance estimation accuracy [T9 T5] Seconda lower level simulation models were also dened to cover several design steps Theyare mainly based on transactional and cycle accurate ISS and they oer better accuracythan VP-based simulation [C20 T6]

From MARTE to SystemC simulation In order to allow an automatic SystemCcode generation of the simulation model a compilation chain based on a Model DrivenEngineering (MDE) approach was developed and integrated in the Gaspard environ-ment MDE is employed to move from an abstract model to a more detailed modelThose intermediary models respecting a pre-dened metamodel provide strongly doc-umented synchronization points in the compilation ow Consequently each trans-formation is independent from the others (they only depend on the pre-dened meta-model) This organization facilitates the reuse of transformations while compiling to-wards dierent simulation levels [T9 T5]

From MARTE to VHDL synthesis We dened a metamodel which identies theconcepts manipulated at the RTL level These concepts are extracted from customizedhardware implementations of massively parallel applications The metamodel also takeinto account the FPGA characteristics and identify dierent abstraction levels of the

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FPGAs These abstraction levels allow rening the hardware implementations Thena design ow was dened which transform applications modeled at high abstractionlevel model (in UML) into RTL models According to the FPGA resources allocated aprocess optimizes the hardware implementation thanks to loop transformations Froma UML model a VHDL code is automatically generated The code was simulable andsynthetizable on FPGA The design ow has been successfully used in safety transportfor the development of an anti-collision radar system [T8]

System level power modeling We proposed a new hybrid system-level power con-sumption estimation methodology for complex embedded systems [C85] A key wordin our contribution is hybridization between abstraction levels Almost all the previ-ous studies focus on power estimation for a given abstraction level without overcomingthe wall of speedaccuracy trade-o The idea here was to build up a hybrid powerestimation tool that combines Functional Level Power Analysis (FLPA) for hardwarepower modeling and TLM simulation technique for rapid system prototyping and fastpower estimation The functional power estimation part was coupled with a fast Sys-temC simulator in order to obtain the needed micro-architectural activities for powermodels which allows us to reach a superior bargain between accuracy and speed [C88]

A model-driven approach for hybrid power estimation in embedded systemsdesign The originality of this approach is to allow the power estimation for bothwhite-box Intellectual Properties (IPs) using annotated power models and black-boxIPs using standalone power estimators In order to obtain accurate power estimatesour simulations were performed at the cycle accurate level using SystemC To makeour approach fast and not tedious for users the simulated architectures were generatedautomatically using a MDE approach Both annotated power models and standalonepower estimators can be used together to estimate the consumption of the same archi-tecture which makes them complementary The simulation results showed that evenwhen the IP code is not accessible or not modiable our approach [J31] allows toobtain quite accurate power estimates

264 Collaborations

Academic Academic INRIA CAIRN (Open-PEOPLE platform development andtutorials) INRIA TRIO (Open-PEOPLE platform development and tutorials) LEATUniversity of Nice Sophia-Antipolis (PhD and internship student co-advising) LAB-STICC University of Bretagne-Sud (PhD student co-advising and 2 publicationsOpen-PEOPLE platform development and tutorials) SoCLib Consortium IEMNUVHC (1 publication) Industrial Thales Communication (Open-PEOPLE platformtutorials)


Open-PEOPLE Terops ModEasy

266 Self assessment

Best paper award Santhosh Kumar RETHINAGIRI Rabie Ben ATITALLAH SmailNIAR Eric SENN and Jean-Luc DEKEYSER Hybrid System Level Power Con-

15

sumption Estimation for FPGA-Based MPSoC 29th IEEEInternational Conferenceon Computer Design (ICCD) October 2011 Amherst MA USA

Gaspard2 was the rst framework to generate SystemC and VHDL codes from thestandard MARTE prole Our contributions make simulation models faster at severalTLM levels This enables shorter simulating and validating complex embedded systemsThe Gaspard environment has been diused as an open source software tool As samefor the ANR OpenPeople project an open platform for power and energy estimationand optimization is oered for the embedded system community

The current Gaspard2 release does not support mixing abstraction levels and de-scription languages in the same system specication Such functionality will certainlymake our tools more generic and exible

The future works of this axis of research will focus more on the architectural as-pect of HPSoC and the validation using recongurable technologies In fact in ournew research project for the few next years contributions on simulation techniquesand performance estimation will be continued and more investigated (cf Section 5)Concerning the programming model and the code generation our future work will notinclude the MDE framework For system validation using SystemC platform will stopwith the current Gaspard2 release

27 Dynamic reconguration and massive parallelism Executive sum-mary

271 Personnel

Permanent researchers Jean-Luc Dekeyser Philippe Marquet Samy Meftali RabieBen Atitallah Defended PhD theses Imran Quadri Yassine Aydi Mouna BakloutiOngoing DaRT PhD theses Hanna Krichen Chiraz Trabelsi Pamela WattebledVenkatasubramanian Viswanathan George Afonso


Several experiences have been carried out in the domain of recongurable architecturesA new classication is given by [E15] shows the complexity of the new degrees of free-dom in terms of run-time adaptivity and introduces a solution to classify the dierentapproaches provided by academics and industry In the Garp project of the UC Berke-ley the FPGA is recast as a slave computational unit located on the same die as theprocessor [E19] The recongurable hardware is used to speed up what it can while themain processor takes care of all other computations Athanas and Silverman introducethe PRISM (Processor Reconguration through Instruction-Set Metamorphosis) archi-tecture which couples a programmable element with a microprocessor [E2] From eachapplication program new processor instructions are synthesized in the recongurableelements designed to accelerate the application Hubner et al propose a recongurableplatform for automotive control functions on a Xilinx Virtex-II FPGA [E21] The sys-tem contains four recongurable regions of identical size that are connected by a com-mon bus system However the system does not employ bitstream relocation becauseof the irregular location of combined BlockRAM (BRAM) and multiplier columns inthe recongurable regions The MOLEN [E46] recongurable processor uses microcode

16

and custom congured HW to improve performance which allows the programmer tomodify the processor functionality and HW without architectural and design modi-cations However the focus is not at all the design ow but only a specic platformIn this project there are no references to a programming model with standard APIwhich are nevertheless required to transparently use processor HW accelerators or co-processors Moreover there is no solution given for self-adaptivity actually runtimereconguration is possible but no decision algorithm and synchronization techniquesare provided The hArtes Approach [E41] addresses the development of an holistictool-chain for recongurable heterogeneous platforms The entire tool-chain consists ofthree phases Algorithm Exploration and Translation Design Space Exploration andSystem Synthesis The objective of the hArtes design ow is to automate the rapiddesign of heterogeneous embedded systems But focussing only on hardware point ofview

Comparing to existing work our contributions target more general recongurablesystems with less constraints In fact we handle heterogeneous systems with softcoreshardcores and accelerators Somme of our work support also massively parallel systemswith signicant number of processors


Our contributions in low level design are related de dynamic reconguration controlhardware supports for dynamic reconguration and implementation of dynamic NoCsand massively parallel architectures

Hardware distributed control pour dynamic recongurable systems Ourcontribution is to propose a control model for FPGA-based systems This control modelallocates a controller to each Partial Recongurable Region of the system allows it to beself-adaptive through an autonomous controller Each distributed controller managesthree major aspects monitoring reconguration decision-making and recongurationrealization for a region The role of the coordinator in this model is to coordinate thedecisions made by the controllers

Hardware implementation for dynamic recongurable support We deneand implement a hardware support for partial and dynamic reconguration Thissupport should be a support for context switching and storing while reconguring asystem at runtime A context is a set of data used by a given recongurable IP thiscan be either integer or memory addresses The context storing is useful in two majorcases if the IP is dynamically recongurable the context saving permits using an IPthat can understand and use the saved context This IP is not necessarily the samebitstream that was used The second case is when we want to reuse (during runtime)the same IP with a dierent context The proposed model is a exible model modularand generic

MppSoC Massively Parallel Processing System on Chip We designed mpp-Soc a massively parallel SIMD processing System-on-Chip[C69 T4] This system isgeneric parametric and can be adapted to the application requirements We proposea rapid and modular design method based on IP assembling to construct an mppSoCconguration A library of IPs is proposed for communication[T3] and computing A

17

model driven based automated generation chain was nally developed It allows thegeneration of the corresponding mppSoC synthesizable VHDL code to be directly sim-ulated or prototyped on FPGA from an mppSoC modeled at the UML level using theMARTE prole

Massively parallel execution model Synchronous Communication Asyn-chronous computation (SCAC) The SCAC model proposes an execution modeldedicated to the massively parallel architectures This model is composed of large num-ber of complex routers called node elements (the NEs) communicating and working inperfect synchronizations Each NE is potentially connected to its neighbors via a regu-lar connection Furthermore each NE is connected to a heterogeneous set of computinggroups (clusters) allow asynchronous processing Each group includes a combinationof processors programmable and specialized hardware accelerators All the system iscontrolled by a Network Controller Unit the NCU This approach allows overlappingcommunications with computations and increases signicantly the IO throughput

Dynamically recongurable heterogeneous CPUFPGA systems In order tomeet real-time power and exibility goals combination of general CPU and recong-urable fabrics like FPGAs is a promising solution leading to heterogeneous computingIn such systems multi-core CPU provides high computation rates while the recon-gurable logic oers high performance per watt and adaptability to the applicationconstraints With the collaboration avec Eurocopter (an EADS company) heteroge-neous systems are used for new generation of adaptive and generic avionic test benches[C8] [C7]

FPGA with massively parallel dynamic reconguration facilities We pro-posed a multi FPGA architecture on a board dedicated to avionics system This boardshould implement parallel dynamic reconguration We recently started a collabora-tion with Nolam ES in the context of a PhD Thesis (CIFRE PhD) The objective ofthis project is to realize a prototype of this board

274 Collaborations

Academic Universiteacute de Bretagne Sud (Lorient) Co-advising of PhD Famous Uni-versiteacute de Bourgogne (Dijon) Co-advising of PhD Famous ENIS Sfax (Tunisia) Co-advising PhD MppSoc and SCAC Industrial Eurocopter (PhD co-advising 3 publi-cations patent) Nolam ES (multi-FPGA platform development)


FAMOUS Euromed 3+3 STIC INRIA Tunisia

276 Self assessment

Hardware distributed control and hardware implementation of dynamic recongura-tion systems are the main strong points of these works Actually these contributionsare necessary to handle the complexity of real size recongurable systems while keep-ing good performances Moreover with such implementation we anticipate future 3DFPGAs

18

A strong point id the possible denition an architecture specially design for a givenapplication from a generic and parametric architecture such as mppSoC and it sys-tematic implementation on a FPGA

Our contributions on dynamic reconguration and massively parallel systems con-stitute the bases of our new research (cf section 5)

Even our contributions were validated on several implementation examples we stillmissing industrial size applications in order to show more clearly eectiveness of ourapproaches

3 Knowledge dissemination

31 Publications

2007 2008 2009 2010 2011 2012

PhD Thesis 2 2 2 3 4 1HDR () 1Journal 2 3 8 5 10 1Conference proceedings () 18 26 18 19 25 1Book chapter Art in collection 1 2 3 4 1Book (written) 1Book (edited)Patent 1General audience papers 1Technical report 4 5 2 2 5Deliverable

() HDR Habilitation agrave diriger des Recherches() Conference with a program committee

The deliverables in which we took part are not public and are thus not counted inthe publications

Major journals in the eld

bull Journal of Systems Architecture httpwwwelseviercomlocatesysarc (2publications)

bull IEEE Transactions on Parallel and Distributed Systems wwwcomputerorg

tpds (1 publication)

bull ACMTransactions on Embedded Computing Systems (TECS) httpwwwacmorgtecs (1 publication)

bull EURASIP Journal on Embedded Systems (2 publications)

bull Microprocessors and Microsystems Embedded Hardware Design Journal (1 pub-lication

bull Journal of Software and Systems Modeling httpwwwsosymorg (2 publica-tions)

19

bull IEEE Transactions on Computers httpwwwcomputerorgportalwebtc

Major conferences in the eld

bull DAC Design Automation Conference

bull LCTES Languages Compilers and Tools for Embedded Systems (1 publication)

bull Memocode Formal Methods and Models for Codesign (1 publication)

bull ARC Applied Recongurable Computing (1 publication)

bull RTCSA Real-Time Computing Systems and Applications (1 publication)

bull DATE Design Automation and Test in Europe (1 publication)

bull Compumag (3 publications)

bull ECMFA European Conference on Modeling Foundations and Applications (1publication)

bull ESWEEK Embedded Systems Week This includes CASES (Compilers Archi-tecture and Synthesis for Embedded Systems) CODES-ISSS (Hardware-SoftwareCodesign and System Synthesis) and EMSOFT (Embedded Software) (1 publi-cation)

bull ASAP Application-specic Systems Architectures and Processors (1 publication)

bull ICCD International Conference on Computer Design (1 publication)

bull ICSE International Conference on Software Engineering

32 Software

Software are evaluated according to the document Criteria for Software Self-Assessment (httpwwwinriafrcontentdownload11783409665version2fileSoftwareCriteria-CE-08-2011pdf)

Gaspard2 (since 2007) - Gaspard2 is an Integrated Development Environment (IDE)for MPSoC visual co-modeling It allows modeling simulation testing and codegeneration of MPSoC applications and hardware architectures Gaspard2 is themain software contribution of the Team It integrates nearly all developmentsdone in the Team

bull url httpwwwgaspard2org

bull Participants All DaRT team members

bull Inria software evaluation A-2 SO-4 SM-2 EM-1 SDL-2 DA-4 CD-4MS-4 TPM4

bull Version 210

MoMoTE (until 2007) - MoMoTE is a Java Framework that allows us to perform mod-els to model transformations It is composed of an API and an engine MoMoteis no more used in Gaspard2 It has been replaced by QVTo an implementationof the QVT standard

20

bull url httprawebinriafrrapportsactiviteRA2007dartdartpdf

bull Participants Ceacutedric Dumoulin Anne Etien Antoine Honoreacute EmmanuelRenaux


bull Competitors QVT ATL

MoCodE (until 2007) - MoCodE (Models to Code Engine) is an API that enables toperform model to text transformation It takes as input a set of models conformto several metamodels and a set of Java classes Then it produces text lesMoCodE is no more used in Gaspard2 It has been replaced by MOFM2T viathe Acceleo implementation


bull Participants Ceacutedric Dumoulin Anne Etien Antoine Honoreacute


bull Competitors Acceleo

Papyrus (since 2008) - The Papyrus tool is an UML Development Environment fullycompliant with the UML standard and providing all UML diagrams It is anEclipse project (in the incubator state) The Papyrus Tool is developed under anOpen source license in collaboration with CEA Atos Airbus LIFL The MARTEprole is supported

bull url httpwwweclipseorgpapyrus

bull Participants Ceacutedric Dumoulin Amine El Kouhen Rahma Yangui


bull Version 09

bull Competitors RSA All UML tools

MDFactory (since 2010) - MDFactory is a Model Driven Engineering environmentto design develop and run software production chains This tool supports ourapproach based on localized transformation A transfer to Axellience an Inriaspin-o is in progress

bull Participants Alexis Muller Anne Etien Thomas Legrand

bull Inria software evaluation A 4 SO 4 SM 2 EM 3 SDL 3 DA 4 CD 3 MS2 TPM2

bull Version 10

bull Competitors EGF Modeling Workow ant

21

33 Valorization and technology transfert

331 Industrial standard MARTE UML prole

The results of 2 theses of the team (Safouan Taha and Arnaud Curcurru) have beenintegrated in the UML prole for Modeling and Analysis of Real-Time and EmbeddedSystems (httpwwwomgorgspecMARTE) from the Object Management GroupWe have participated to all the published versions of this standard (10 in November2009 and 11 in June 2011) and are currently active members of the revision task forcefor the future 12 version

332 Startup Axellience

Based on the good results of the localized transformations coupled with MDFactoryin Gaspard2 in term of reusability modiability and understandability Alexis Muller(Expert Engineer) studied the opportunity to create a spin o company from theseworks Due to his past experiment in the domain of information system and thematurity of the model usage by the enterprises the idea is to target the automaticgeneration of information system from UML model and no more to address embeddedsystems Joined by Thomas Legrand (Permanent Inria Engineer) they develop newlocalized transformations and new chains The results and the rst feed-backs fromenterprises in the domain of information systems are very encouraging Furthermorethe Axellience project (httpwwwaxelliencecom) won the national competitiveexamination of helping to the creation of innovating enterprises (Oseo) A technologicaltransfer concerning MDFactory is foreseen between the DaRT team and the Axellienceproject in order to create the spin o company in the early beginning of the 2012 year

333 Patent

Martial Rubio (Eurocopter) Nicolas Belanger (Eurocopter) Rabie Ben Atitallah(LAMIH UVHC) and Jean-Luc Dekeyser (LIFL Lille 1) Proceacutedeacute doptimisationdynamique dune architecture doutils de tests systegraveme (Dynamic Optimization Processof a Tool Architecture for System Tests) Patent registered at INPI under the numberFR1100232

34 Teaching

2007-2008 2008-2009 2009-2010 2010-2011

L M O L M O L M O L M O Total

P Boulet 42 133 32 42 130 32 2 54 74 20 561

J-L Dekeyser 96 96 70 70 70 70 472

C Dumoulin 267 262 237 214 980

A Etien 90 38 140 52 140 52 120 72 704

J Forget 80 48 128

L Gonnord 128 162 30 400

F Guyomarch 212 192 248 652

P Marquet 90 110 90 110 90 110 90 110 800

R Ben Atitallah 24 24 100 112 120 180 560

As the DaRT team is mostly composed of professors and associate professors wehave a very large teaching activity The master courses more directly related to theresearch themes of the team are listed below

Embedded Systems

22

bull System-on-Chip Design (Pierre Boulet Jean-Luc Dekeyser Anne EtienAbdoulaye Gamatieacute Samy Meftali Rabie Ben Atitallah)

bull Introduction to Embedded System Design (Rabie Ben Atitallah)

bull Embedded System Design (Pierre Boulet Rosilde Corvino AbdoulayeGamatieacute Anne Etien Thomas Legrand Alexis Muller)

bull HardwareSoftware Co-design for High Performance Embedded Systems(Rabie Ben Atitallah)

bull Simulation of Systems and Architectures (Philippe Marquet and SamyMeftali)

Computer Architecture and Operating Systems

bull Advanced Computer Architecture (Pierre Boulet Jean-Luc DekeyserCalin Glitia)

bull Distributed Systems and Infrastructures (Pierre Boulet)

bull Distributed Systems (Julien Forget)

bull Introduction to Real-Time Operating Systems (Philippe Marquet)

bull Operating Systems (Julien Forget)

Software engineering

bull Model Driven Engineering (Anne Etien)

bull Advanced Object Conception (Ceacutedric Dumoulin)

bull Parallel and Distributed Programming (Philipe Marquet)

bull Compilation Basics and Optimisation (Laure Gonnord)

bull Advanced Concepts in Programming Languages (Pierre Boulet)

bull New Technologies for the Web (Ceacutedric Dumoulin)

Introduction to research and innovation

bull Pierre Boulet and Philippe Marquet

1 Our institutions (both the University Lille 1 and Inria Lille-Nord Europe)are members of the doctoral school ED SPI (Eacutecole doctorale Sciences pourlIngeacutenieur Universiteacute Lille Nord-de-France - 072 httpedspiuniv-lille1fr)

2 Jean-Luc Dekeyser is director of the PhD program in computer science for thisdoctoral school

3 Philippe Marquet is in charge of the Master in Computer Science at the Universityof Lille 1

23

35 General Audience Actions

Pierre Boulet has given several conferences to a general audience twice at the in-ternal Unitheacute ou Cafeacute event and twice to high school students during the fecircte dela science He maintains a blog about all his interests research teaching scienticcommunications and general computer science at httpwwwliflfr~bouletblogHe has also been interviewed in a podcast about scientic communication (httpscientific-presentationscom20110312028-convinced-yes-but-of-what)

Cedric Dumoulin has done general audience conferences on Model Driven Engineer-ing (MDE) at the the INRIA internal Unitheacute ou Cafeacute event and at the INRIA CupOf Science event

36 Visibility

Program Committee

Pierre Boulet was member of the program committees of FDL (from 2007 to 2010each time co-chair of the program committee) M-BED 2008 2010 and 2011 STAN-DRTS 2009 DATE 2010 dMEMS 2010 and 2012 RAPIDO 2011 and 2012 and expertreviewer at DAC 2012 and has reviewed articles for Journal of System ArchitectureParallel Computing Design Automation for Embedded Systems TSI IEEE ComputerArchitecture Letters ACM Transactions on Embedded Computing Systems Algorith-mica Software and System Modeling (SoSyM) and IEEE Transactions on Parallel andDistributed Systems

Jean-Luc Dekeyser was member of several PCs DSD IDT Rapido RecongECMDA Recosoc RSP SOC GTTSE DASIP ICM ICSCS Sympa Renpar ISPANAICCSA

Cedric Dumoulin was member of several PCs and reviewer in various journals andconferences Journeacutees sur lIngeacutenierie Dirigeacutee par les Modegraveles (IDM 10 09 08 07)ACM Computing Surveys (11) MSR 11 SOSYM 11 additional reviewer at Models(07080910) LObjet (07)

Anne Etien has been member of the program committee of ECMFA (since 2010)Inforsid (since 2011) Model and Evolution Workshop (since 2010) GraBats (2011)GTTSE (2011) She was also reviewer for the Sosym Journal (2011) ACM ComputerSurveys (2011) ISI Journal (2010) revue Objet (2009)

Abdoulaye Gamatieacute was PC chair of the French-speaking conference on reac-tive system modeling (MSR11) He iswas TPC member of ESLsyn2012 EM-SOFT2012 CARI2012 ESLsyn2011 ACCA2011 M-BED2011 LCTES2011 andEMSOFT2010 He was editor of the special issue of the European Journal of Automa-tion (JESA) vol 451-3 and is guest editor of Journal of Discrete Event DynamicSystems of Springer Finally he gave an invited talk at LCTES2011 on the Gaspard2framework

Laure Gonnord co-coordinates of the French Compilation Community She was PCchair of the ACCA workshop on Static Analysis and Compilation in 2011

Vlad Rusu has been a PC member in the TESTCOM07 conference in the K 2011workshop and the Workshop on Rewriting Logic and Applications (WRLA 2012)

24

Conference organization

The DaRT team organized the Modeasy07 Workshop which has been held in the CasaConvalescencia UAB building Campus Barcelona Spain in conjunction with FDL 2007

The DaRT team participated to the organization of Euromicro DSD and SEAA2010 These two conferences on respectively embedded system and software engineeringthemes took place from the 1rst to 3rd September in Polytech Lille They gatheredaround 240 participants httpwwwdsdconforg

Pierre Boulet has organized a series of 3 workshops on Model driven Design ofEmbedded Systems M-BED 08 10 and 11 co-located with DATE He was both generalchair and chair of the program committee

Cedric Dumoulin and Anne Etien have participated in 2011 to the organizationof the national Journeacutees sur lIngeacutenierie Dirigeacutee par les Modegraveles (IDM Days) andthe the Journeacutees du GDR Geacutenie de la Programmation et du Logiciel (GDR GPLDays) (httprmodlilleinriafridm-gplpier) and in 2010 to Journeacutees surlIngeacutenierie Dirigeacutee par les Modegraveles of Lille

Laure Gonnord organized the ACCA workshop on Static Analysis and Compilationin 2011(in conjunction with CGO conference)

Abdoulaye Gamatieacute co-organized the MSR11 conference in Lille (around 60 par-ticipants)

Rabie Ben Atitallah co-organized the Workshop RAPIDO 2011 in conjunction withHiPEAC conference in Greece

Jean-Luc Dekeyser co-organized the Hopes Workshop in conjunction with ECMDA-FA in Paris

Vlad Rusu was co-chair of the Algebraic Methods in Model-Based Software Engi-neering (AMMSE 2011) workshop and has organized four editions of the Ecole JeunesChercheurs en Programmation (2008-2011)

25

4 External Funding

(k euros) 2007 2008 2009 2010 2011

INRIA Research InitiativesARC INRIA - Triade Managed by the Espresso IPT

National initiativesOpen-PEOPLE 56 410 56 410 56 410FAMOUS 121 726 24 218OpenEmbeDD 25 545 25 545 8 515Terops 13 390 6 986 33 961 3 161Co-modeling for HPC Managed by the Sage IPT

European projectsModEasy 184 409

Industrial contractsValeo 5 000 10 000Nano2012 ID-TLM 35 140 30 882EADSIW amp Eurocopter 10 000 10 000

ScholarshipsPhD (Cordi) 33 000 33 360 24 336 34 848 38 268PhD (Region) 72 750 35 020 10 000 15 000 15 000PhD (MENRT+Monitor) 41 365 72 455 85 753 54 933 23 645PhD (Valeo) 15 000 10 000 10 000 15 000 15 000PhD (CEA) 35 000 27 000 35 000PhD (CIFREEcreall) 8 000 35 000 35 000ATER 8 351 26 723 38 676Post Doc 37 928 34 704 50 613 54 782 46 956AI+ 43 477ODL 51 147 44 505 57 237

Other fundingExplorer Program 5 000BQR Funding (Univ Lille) 8 500Support from LIFL 5 000Stic Tunisia 7 125 7 500 5 800 6 400Stic Algeacuteria 6 000Euromed 3+3 10 000 5 000 6 000

Total 286 103 436 979 408 026 521 209 462 548

dagger INRIA Cooperative Research InitiativesDagger Large-scale Initiative Actionslowast other than those supported by one of the above projects+ junior engineer supported by INRIA engineer supported by INRIA

ARCs

ARC INRIA - Triade Partners Aoste DaRT Espresso The goal of this projectis to use formal models with structuring programmatic constructs as means to

26

translate programs and descriptions written in formalisms widely used in Em-bedded System and SoC design 1 Triade also aims to provide a seamless ow ofincreasingly time-dened and time-accurate models so as to progressively obtainthe nal mapped implementation through provably correct steps from the earlydescription elements

National initiatives

OpenEmbeDD RNTL Project Partners Airbus Anyware Technologies CEACS SI France Telecom INRIA (AOSTE DaRT ESPRESSO) LAAS (CNRS)Thales Aerospace Thales RampD Verimag The OpenEmbeDD project2 aimed todevelop an engineering model driven open-source platform for real time and em-bedded systems It dealt with (1) UML standard for Real Time and Embeddedsystems (2) innovating technology for interoperability (3) mastering method-ology chain (4) real time models for simulation The tools were evaluated inpractical domains eg the aeronautic sector automobile sector and telecomsector

Terops Systemtic Project Partners THALES (TRT TOSA) Thomson EADS(EADS Astrium MBDA) Dassault Aviation Renault Valeo Freescale (SAS)M2000 ARTERIS Esterel Technologies VirtualLogix CEA-LIST INRIA(Alchemy Caps DaRT) IEF ENSTA PRiSM CRI (ARMINES Eacutecole desMines) Laboratoire ETIS RATP The Terops project of the Systemtic com-petitiveness cluster aimed at developing a hardware platform and the associateddevelopment framework for computation intensive applications

Co-modeling and model engineering for HPC in electromagnetism softwarePEPS Project Partners IRISA INRIA (DaRT) L2EP The goal of this projectwas to use the power of new software engineering tools to design a new versionof the electromagnetism solver CARMEL This project emphasised on the factthat scientist from many dierent elds (physics applied mathematics highperformance computing software engineering) need to collaborate to ensure itssuccess and deliver a model of CARMEL using Gaspard2 metamodel Thenwith the Gaspard2 development environment we can generate a parallel softwareto solve the Maxwell equations

Open-PEOPLE ANR project Partners INRIA (DaRT TRIO CAIRN) LEATLAB-STICC Thales and Inpixal The objective of Open-PEOPLE is to providea platform for estimating and optimizing the power and energy consumptionsUsers will be able to estimate the consumption of an application deployed ona hardware architecture chosen in a set of parametric reference architecturesThe components used in the targeted architecture will be chosen in a library ofhardware and software components Some of these components will be parametricto further enlarge the design space for exploration

FAMOUS ANR project Partners INRIA (DaRT Sardes) Universiteacute de BretagneSud Universiteacute de Bourgogne Sodius FAMOUS will make recongurable sys-tems design easier and faster The obtained tool in this project is expected to be

1httpwwwirisafrespressoTriade2httpwwwopenembeddorg

27

used by both companies designers and academic researchers especially for modernapplications system specic design as smart camera image and video processingetc FAMOUS main objective is to explore novel design methodologies and targetmodern embedded systems architectures

European projects

ModEasy Interreg III A Franco-English Cooperation Partners University ofKent IEMN (Institut Electronique Microelectronique Nanotechnologies) INRIA(DaRT) The ModEasy project3 develops software tools and techniques in orderto facilitate the development of reliable microprocessor-based electronic (embed-ded) systems using advanced development and verication systems The denedtools will be evaluated in practical domains such as automotive In this contextwe have proposed a FPGA prototype that merges a reactive cruise control andan anti-collision radar in a single chip

Associated teams and other international projects

STIC INRIA - Tunisia program Partners This program aims at promoting thedesign of metamodels transformation tools and techniques for the implemen-tation of recongurable systems-on-chip The resulting co-design environmentwas validated on embedded systems dedicated to security in automobile andmore specically in the design of cruise control systems integrating anti-collisionradars This collaboration lead to two PhD students and several Master studentsin collaboration with the team of Pr Mohamed Abid at CES-ENIS in Sfax

Euromed 3+3 INRIA program Partners Univ Monastir A collaboration sup-ported by the Euromed 3+3 program started in 2009 It permits to initiateespecially collaboration with the University of Monastir (Tunisia) with the teamof Pr Rached Torki on network on chip (NoC) modeling evaluation and imple-mentation A co-advised PhD thesis is started on these issues between DaRT andU Monastir

EGIDE Ulysse Dublin program Partners UC Dublin Our collaboration withPr Tahar Kechadi (UC Dublin in Ireland) is supported by the EGIDE Ulysseprogram It concerns mainly distributed systems communication modeling andapplication specic multiprocessor architectures Two master students have beenco-advised on these topics during the period

STIC Algeacuterie INRIA Program Partners Univ Oran Algeria INRIA (DaRT Dol-phin) In this project we have studied multi-objective meta heuristics for thedesign space exploration of multidimensional intensive embedded systems

Industrial contracts

Valeo - CNRT Futurelec Partners Valeo INRIA (DaRT) L2EP The objectiveof this project consists of tting Gaspard2 for high performance computing andmeta-computing This work is done with a PhD student (Valeoregion funding)and is part of the program 1 of MEDEE (Parallelization of CARMEL) The

3httpwwwlifrmodeasy

28

results of this research are to be considered for integration in the Gaspard tool-set at INRIA and has provided models for nite elements simulations for electricalternator simulator developed by Valeo and L2EP

Valeo - GPUTech With the generalization of the GPGPU Computing (General Pur-pose GPU) have added a new target for our Gaspard2 Framework producingoptimized code for GPU This task was nanced by Valeo who plan to runtheir simulations on GPU and by GPUTech who includes their technology in theframework

Thales Partners ENSIETA INRIA DaRT Thales In order to increase productivityand thus decrease time to market we propose to apply Model Driven Engineering(MDE) through the use of process components which encapsulate the main ac-tivities of co-design processes We experiment our approach in a co-design processbased on the use of the new MARTE prole This work is done in the context ofa CIFRE PhD contract co-supervised by Joeumll Champeau from ENSIETA (Brest)and Jean-Luc Dekeyser

CEA List Partners CEA List INRIA DaRT This point to point collaboration withCEA materialized by two PhD funding aims to a UML prole for co-designand the adaptation of UML Tools to the domain and to the design processrespectively The main contribution of the rst PhD consisted in dening ametamodel for hardware architecture for the MARTE standard The results ofthis research has also been integrated in the Gaspard2 tools at INRIA and in theAccordUML environment at CEA The idea of the second thesis is to providecustomers with a UML tool adapted to its work here the design of embeddedsystem The tool customization is done with the help of models or proles

Nano2012 ID-TLM Partners ST Microelectronics and INRIA (Aoste and DaRT)The goal is to explore the contributions of the model driven engineering to themodeling and analysis of transaction level (TLM) models of computation (MoC)This collaboration has started on december 2008 and will last 4 years

EADS IW amp Eurocopter Partners EADS IW Eurocopter INRIA (DaRT) Thesubject deals with dynamic recongurable system design for avionic test applica-tions A complete methodology takes the recongurability of the hardware as anessential design concept and proposes the necessary mechanisms to fully exploitthose capabilities at runtime

Ecreall Partners Ecreall INRIA (DaRT) The transformation chain used in theDaRT Embedded System modeling approach involves several models automati-cally generated This work aims to be able to modify directly ones of the gen-erated model and let the modication be propagated in both direction to othermodels of the chain

Nolam Embedded Systems Evaluation of 3D FPGA for intensive computing andparallel IO (started in February 2012)

Other funding

In 2010 we have obtained nancial support from LIFL (Laboratoire dInformatique Fon-damentale de Lille) to support an emerging activity around Domain-Specic Modelling

29

Languages (DSMLs) In 2011 we have obtained a grant Bonus Qualiteacute Recherche fromthe University Lille 1 on the same topic The results that we have obtained thanks tothis support are discussed in Section 253 in the paragraph on DSMLs (essentially 6published papers)

In 2012 we obtain special support (8K) to develop intelligent camera with recon-gurable FPGA to start a collaboration between DaRT and Fox teams both fromLIFL

5 Objectives for the next four years

We shall continue investigating Dynamic Recongurable Massively Parallel Architec-tures and incorporate in it research on languages for their rigorous safe and ecientprogramming We recall that the main motivation behind this research is that stan-dard Integrated Circuits (ICs) are reaching their limits and need to be extended to meetthe requirements for next-generation computing and that one of the most promisingevolution allowing for ecient use of time space and energy are FPGAs (Field Pro-grammable Gate Arrays) This new paradigm opens many opportunities for researchsince there are no theoretical foundations programming methodologies or tools sup-porting it Therefore we shall address the following topics (i) designing massively par-allel dynamically recongurable architectures (ii) proposing execution models as well asprogramming languages for them and (iii) designing software engineering tools aroundthose languages compilers simulators veriers for enabling their rigorous e-cient and safe programming The programming languages and related software toolsfor the new architectures will be specic to the architectures in question in order forprogrammers to fully benet from them

51 Context

FPGA recongurable circuits have emerged as a privileged target platform to imple-ment intensive signal processing applications [E16] FPGAs oer inexpensive and fastprogrammable silicon on some of the most advanced fabrication processes One of themost promising evolutions are 3D-Stacked Integrated Circuits (3D SICs) which consistof two or more conventional 2D circuits stacked on the top of each other and builtinto the same IC Such a circuit has been released by the leading FPGA manufacturerXilinx (FPGA family Virtex7)

We believe that 3D integration will lead to a signicant shift in the design of FPGAcircuits Indeed by incorporating the conguration andor dataprogram memory onthe top of the FPGA fabric with fast and numerous connections between memoryand elementary logic blocks it will be possible to obtain dynamically recongurablecomputing platforms with a very high reconguration rate which for technical reasonsare not currently possible Finally FPGA technology already allows for massivelyparallel architectures due to the large number of programmable logic fabrics availableon the chip

The ITRS and HiPEAC roadmaps4 promote the idea that parallel heterogeneousand adaptive architectures will dominate next-generation System-on-Chip (SoCs) in-cluding those based on FPGAs We are in line with this vision but have to overcomeseveral obstacles before we can materialize it

4httpwwwitrsnet httpwwwhipeacnetroadmap

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Processor We shall dene a processorcontroller in charge of the dynamic recongu-ration and of managing the parallelism between other processing units

Adequate execution models We need an execution model that can manage the par-allelism intrinsic in applications and the dynamicity of the architecture for acustomized design

Adequate programming languages Massively parallel dynamically recongurablearchitectures need languages for their rigorous safe and ecient programming

Adequate design environment System designers need software tools around thesearchitectures compilers simulators formal veriers

52 State of the art

Currently to our best knowledge there are no background theory programmingmethodology and software tools that can fully take the advantage of this paradigmshift on both the software engineering and physical implementation level The researchthat comes closest to this synthesis which we are aware of within Inria is done inthe CAIRN project-team5 at Inria Rennes who work on FPGA-based recongurablesystems and are interested in compilation techniques for them but without focusing onmassive parallelism or formal verication We therefore present in this section a viewof the separate domains which we shall integrate in our research

521 Dynamically recongurable massively parallel architectures

SIMD (Single Instruction Multiple Data) machines allow for data parallelism Ad-vanced integration technologies with billions of transistors integrated on a single dieenabled Systems-on-Chip parallel machines for which hardwaresoftware co-design en-vironments were developed to handle the silicon complexity Nowadays with the emer-gence of the new 3D-FPGA news methods and new tools have to be invented in orderto handle their hardware complexity and to provide user with software tools allowingthem to fully benet from these promising architecture novelties A rst approach tar-gets systems with statically predetermined special instructions whose time and locationfor reconguration are known before execution

Our project is positioned at the intersection of two directions studied by the com-munity The rst one is ASIP [E17]

ASIP (Application Specic Instruction-set Processors) are mostly used inembedded-systems design They allow some customization of the hardware instructionset extensions instruction parameterization and inclusionexclusion of predened com-ponents (which we call IP for Intellectual Properties) dedicated to specic applicationsHowever with this partial customization a large percent of the CPU core is still staticand even if some solutions integrate multicore aspect exist they remain far from mas-sively parallel processing For example the eMIPS (extensible MIPS) is a dynamicallyextensible processor architecture that achieves the performance of application-specichardware optimizations in a safe general-purpose multi-user system environment Itallows for multiple secure extensions to load dynamically and to plug into the stages ofa pipelined data path thereby extending the core instruction set of the microprocessor

5Computing ArchItectures with embedded RecoNgurable resources towards energy-ecientsystems-on-chip

31

Extensions can also be used to realize on-chip peripherals and if the surface permits iteven multiple cores [E7] However a large part of the Mips core is static and consumeresources (surface static power consumption) even when they are not used This isparticularly costly for massively parallel integration of this eMIPS where the resourcewaste is multiplied by the number of elementary nodes

The second domain is that of dynamic parallel embedded systems With the ad-vance of system-level integration and system-on-chip the high-tech industry is nowmoving toward multiple-core parallel embedded systems and Network on Chip ADRES(architecture for dynamically recongurable embedded systems) is a exible high-performance architecture template for low-power embedded applications It consistsof a tightly coupled very long instruction word (VLIw) processor and a coarse-grainedrecongurable memory array ADRES is a exible template to generate concrete in-stances Together with a simulator and AnSI-C compiler this tool chain allows for ar-chitecture exploration and development of application-domain-specic processors [E23]However the customization allowed by this framework is static (done before executiontime)

Our proposal is to do most of the reconguration dynamically with the smallestpossible statically predened part and to take advantage from the massive parallelismsystems of the 3D-FPGA

522 Formal tools for programming language design and verication

Since the hardware and software will serve mostly to build safety-critical applicationsit is essential to use formal methods to maximize condence in their safe behavior Weneed programming languages to develop such applications which exhibit the featuresof the architecture dynamic reconguration and massive parallelism in order to allowusers to fully benet from them Programming languages with (massively) parallelconstructs are many but we are not aware of many dynamically recongurable ones inwhich in which instructions and their semantics can be added deleted or modied on they (during execution) in the spirit of the forth language6 The closest recent workswe are aware of in this eld are the use of continuations in functional programminglanguages which allow for programs to stop and ask the environment how to continueinterpreting a given instruction (for example a system call) The environment thenprovides the information for continuation on the y This has been used for cleanimplementations of system calls in functional languages [E24]

Hence we shall dene our own languages possibly taking inspiraton from the aboveFor this we shall use state-of-the-art formal language denition frameworks to deneexperiment with compile and verify such languages and application written in themLanguage denition frameworks originate from works on formal semantics [E1 E39E33] For a long time such semantics were dened for toy languages andor withouttool support Mechanized support beneted from the development of mature general-purpose interactive proof assistants The most convincing eort in that direction isCompCert [E28] a compiler for a substantial fragment of C which was proved correctin the Coq proof assistamt with respect to the source C the and target assemblersformal operational semantics More recently language denition frameworks basedon rewriting have been proposed [E30 E10] They allow for the denitions of formalexecutable operational semantics which can directly be used for executing programs

6httpwwwforthorg

32

and verifying them One such framework is K [E45] which has been applied for general-purpose languages including the most complete denotion of C to-date [E13] as wellas for domain-specic ones [C94] Our choice for dening domain-specic languagesfor dynamically recongurable massively parallel architectures is to use K since it iscurrently the most mature language denition framework and we gained experiencewith it by intensely using it and interacting with the team developing it

53 Research Proposal

We shall address the following topics (i) designing massively parallel dynamically re-congurable architectures (ii) proposing execution models as well as (iii) programminglanguages for them and (iv) designing software engineering tools for those languagessuch as compilers simulators and formal veriers

531 Designing massively parallel dynamically recongurable architec-tures

The rst topic consists in designing a processor which we call Homade whose onlyhard-coded instructions are control ones (ie jumps) All the other instructions (SPMDtrigger IP trigger and IP reconguration) reside in dynamic IP units that are instanti-ated executed (sometime in parallel) and replaced on the y The IPs can be arbitrarycomplex including ALU functions loadstore units or even other processors TheHomade core should be the simplest possible and so no instruction (except for thecontrol ones) is predened Then users pre-select on an FPGA a set of IPs accordingto the needs of their application and these IPs are invoked on the y by the HomadeCore at execution time By taking advantage of the dynamic reconguration func-tionality of new FPGAs the set of IPs associated to a Homade core evolve duringexecution some are invoked others are deleted etc Thus Homade becomes a userand application-specic specialized processornode during its execution by exploitingthe new features of hardware technology in order to implement the functional units anapplication actually uses (i) reduced silicon surface - only what is really needed usesspace (ii) a reduced power consumption - only what is really need consumes staticenergy (iii) a reduced data latency by (re)placing the most active IPs closer to theprocessor

532 Dening execution models for the new architectures

The execution model for the new architectures has to incorporate massive parallelismin order to benet from very large size of next-generation FPGAs which currentlycontain several million gates Hence the execution model shall be a blend betweenmassive parallelism and dynamic reconguration The processing element (PE) ofthe FPGA circuits will have to be completed with specic hardware to manage themassively parallel processing (network synchronization barriers communication)and we envisage in the continuity of our works on on mppSoC[C69 T4] that theexecution model of the whole system will be an extension of the old SPMD model(Single Program Multiple Data ie executing the same code in parallel on many PEs)In the new approach the same IP and the same bit-stream skeleton will broadcast tothe PEs We shall investigate a hardware solution provided by 3D-FPGA to implementthis new functionality in a ecient way

33

533 Proposing programming languages implementing the executionmodel

In order to program such architectures according to such execution models one needsprogramming languages that fully exploit the opportunities oered by the architetureWe shall dene (at least) three language a machine code an assembler and a higher-level language We envisage that the lower-level languages will have specic primitivesfor dynamic IP instantiation and deletion whereas the higher-level ones will mirrorthis dynamicity by being self-extensible new instructions and their semantics can beadded on the y thereby implementing the on-the-y management of the IPs Thisallows programmers to directly perform dynamic reconguration and to directly handlemassive parallelism

534 Designing software tools simulators compilers veriers

Programming applications in such languages is a risky task the metaphor is that ofsimultaneously guiding many planes while dynamically changing their routes The needfor strong guarantees of functional correctness is thus crucial especially for applicationsthat are embedded and safety-critical (which are natural targets for our research)Hence we shall provide users with as much guarantee as possible with regards to thecorrectness of their programs This is achieved by formally dening the languagesincluding their operational semantics using the K executable semantical framework

A useful feature of K is that allows us to experiment with a programming languagewhile it is being dened one can execute programs in the (currently dened portion of)a language to symbolically simulate programs with partially dened instructions (thisis very important for us since the IPs that we invoke are typically not fully specied)

In K one can also formally verify assertions about program behaviour Of particularimportance will be assertions related to dynamic reconguration (eg given partialspecication of the IPs potentially invoked by a program is it guaranteed that theprogram never deadlocks) as well as assertions specic to massive parallelism and totheir combination

The correctness of compilers between the high-level assembly and machine-codelanguages must also be proved to ensure that what is veried at the high level stillholds at the lower levels We are designing and implementing in K itself a program-equivalence logic for languages dened inK Thus we shall stay within one environment- K - for all the formal denitions and transformations of programs and the analysesrelated to them This has the advantage of minimizing any semantic gaps that occurwhen one uses several tools but requires us on the other hand to work harder in orderto develop our own theory and tools (eg logics and provers for them) This overheadis acceptable since the theoriestools that we shall develop are specic to languagesthat we design

54 Open Problems

1 For dynamically recongurable massively parallel architectures to implementthem eciently to dene their execution model and to propose a library of IPsimplementing the most common operations (ALUs IO etc) Some wrap-pers have to be specied for dierent standard such as OCP Amba etc Thesewrappers could be produced from IP-Xact standard specications

34

2 For programming languagesverication to dene dynamically recongurablelanguages (with evolving syntax syntax and semantics) in K to verify programsin those languages and to formally verify correct compilation in K

3 For the overall project build tools easy to use by end-users Implement convinc-ing case studies

55 Anticipated Risks

The strongest risk is that of lack of integration between the architecture people andthe `formal methods people in the team due to the scientic distance between us Toavoid this we started working together on our Homade recongurable processor and ona K denition of an assembly language incorporating dynamic-reconguration instruc-tions taking care to dene its operational semantics as the execution of instructionsby the Homade processor

Related to that risk is a possible lack of balance between formal-oriented andarchitectural-oriented parts of the team The solution is to recruit of a permanentresearcher specialized in formal methods and having some knowledge in architecture

The last identied risk concerns the roadmap of the future FPGAs We bet onthe availability of 3D FPGA in the next few years with high-speed recongurationcapabilities To anticipate this risk we have started in collaboration with Nolam ES(a local high-tech company) the design of a multi-FPGA prototype with bitstreambroadcasting capabilities

56 Resources and Sta Requirement

The permanent sta of the current team is composed of one professor three associateprofessors and one full-time researcher together with an external collaborator who isassociate professor in Valenciennes Our rst priority is to recruit a researcher special-ized in formal methods in order to strengthen that part of the team The second oneis to recruit a researcher to work on the architecturehardware layer To help with thetransfer of the research results an engineer should be associated to our developments

6 Bibliography of the project-team

61 Books and Monographs

Books

[B1] Abdoulaye Gamatieacute Designing Embedded Systems with the SIGNAL Program-ming Language Synchronous Reactive Specication New York Springer Ver-lag 2009 isbn 978-1-4419-0940-4

62 Doctoral dissertations and Habilitation theses

Habilitation

[H1] Samy Meftali Vers la reconguration dynamique dans les systegravemes embar-queacutes de la modeacutelisation agrave limpleacutementation HDR Universiteacute des Sciences etTechnologie de Lille - Lille I July 2010

35

PhD Theses

[T1] Adolf Abdallah Conception de SoC agrave Base dHorloges Abstraites Vers lEx-ploration dArchitectures en MARTE PhD thesis Universiteacute des Sciences etTechnologie de Lille - Lille I Mar 2011 url httphalinriafrtel-00597031en

[T2] Vincent Aranega Traccedilabiliteacute pour la mise au point de modegraveles et la correctionde transformations PhD thesis Universiteacute des Sciences et Technologie de Lille- Lille I Nov 2011 url httphalinriafrtel-00597031en

[T3] Yassine Aydi Multiprocesseurs agrave reacuteseau dinterconnexion multi-eacutetages dela veacuterication agrave limpleacutementation sur SoC PhD thesis Ecole Nationaledingeacutenieurs de Sfax Apr 2011

[T4] Mouna Baklouti Meacutethode de conception rapide darchitecture massivementparallegravele sur puce de la modeacutelisation agrave lexpeacuterimentation sur FPGA PhDthesis Universiteacute Lille 1 Sciences et Technologies and Ecole Nationale dIngeacute-nieurs de Sfax Dec 2010

[T5] Rabie Ben Atitallah Modegraveles et simulation des systegravemes sur puce multipro-cesseurs - Estimation des performances et de la consommation deacutenergie infrench Thegravese de doctorat (PhD Thesis) Lille France Laboratoire dinforma-tique fondamentale de Lille Universiteacute des sciences et technologies de LilleMar 2008

[T6] Hajer Chtioui Gestion de la coheacuterence des donneacutees dans les systegravemes multi-processeurs sur puce PhD thesis Universiteacute de Valenciennes et du HainautCambeacutesis Dec 2011

[T7] Calin Glitia Optimisation des applications de traitement systeacutematique inten-sives sur System-on-Chip in french Thegravese de doctorat (PhD Thesis) LilleFrance Laboratoire dinformatique fondamentale de Lille Universiteacute des sci-ences et technologies de Lille Nov 2009

[T8] Seacutebastien Le Beux Un ot de conception pour applications de traitement dusignal systeacutematique impleacutementeacutees sur FPGA agrave base dIngeacutenierie Dirigeacutee par lesModegraveles Thegravese de doctorat (PhD Thesis) France Laboratoire dinformatiquefondamentale de Lille Universiteacute des sciences et technologies de Lille Dec2007

[T9] Eacuteric Piel Ordonnancement de systegravemes parallegraveles temps-reacuteel De la modeacuteli-sation agrave la mise en divideuvre par lingeacutenierie dirigeacutee par les modegraveles Thegravese dedoctorat (PhD Thesis) France Laboratoire dinformatique fondamentale deLille Universiteacute des sciences et technologies de Lille Dec 2007

[T10] Imran Raq Quadri MARTE based model driven design methodology for tar-geting dynamically recongurable FPGA based SoCs PhD thesis Universiteacutedes Sciences et Technologie de Lille - Lille I Apr 2010

[T11] Wendell Rodrigues Une Meacutethodologie pour le Deacuteveloppement dApplicationsHautes Performances sur des Architectures GPGPU Application agrave la Simula-tion des Machines Eacutelectriques PhD thesis Universiteacute des Sciences et Tech-nologie de Lille - Lille I Jan 2012

36

[T12] Julien Taillard Une approche orienteacutee modegravele pour la paralleacutelisation duncode de calcul eacuteleacutements nis in french Thegravese de doctorat (PhD Thesis)Lille France Laboratoire dinformatique fondamentale de Lille Universiteacute dessciences et technologies de Lille Feb 2009

[T13] Huafeng Yu A MARTE-Based Reactive Model for Data-Parallel IntensiveProcessing Transformation Toward the Synchronous Model in french Thegravesede doctorat (PhD Thesis) Lille France Laboratoire dinformatique fonda-mentale de Lille Universiteacute des sciences et technologies de Lille Nov 2008

63 Articles in referred journals and book chapters

Book Chapters

[Ch1] Ouassila Labbani Jean-Luc Dekeyser Pierre Boulet and Eacuteric Rutten UML2prole for modelling controlled data parallel applications In ISBN 978-1-4020-6147-9 Sorin A Huss editor Springer Verlag Sept 2007 Chap 18

[Ch2] Eacuteric Piel Philippe Marquet and Jean-Luc Dekeyser Model Transformationsfor the Compilation of Multi-processor Systems-on-Chip In Springer Verlag2008 Chap 13 pp 459473

[Ch3] Huafeng Yu Abdoulaye Gamatieacute Eacuteric Rutten and Jean-Luc Dekeyser ModelTransformations from a Data Parallel Formalism towards Synchronous Lan-guages In Springer Verlag 2008 Chap 13

Articles in Collections

[I1] Vincent Aranega Jean-Marie Mottu Anne Etien and Jean-Luc Dekeyser Us-ing Trace to Situate Errors in Model Transformations In Software and DataTechnologies Ed by Cordeiro Joseacute Ranchordas AlpeshKumar Shishkovand Boris Vol 50 Communications in Computer and Information ScienceSpringer Berlin Heidelberg Apr 2011 doi 101007978-3-642-20116-5_11 url httphalinriafrinria-00589253en

[I2] Yassine Aydi Mouna Baklouti Philippe Marquet Jean-Luc Dekeyser and Mo-hamed Abid A Design Methodology of MIN-Based Network for MPPSoC onRecongurable Architecture In Recongurable Embedded Control SystemsApplications for Flexibility and Agility Ed by Mohamed Khalgui and Hans-Michael Hanisch IGI-Global 2011 pp 209234 url httphalinriafrinria-00563719en

[I3] Rosilde Corvino Abdoulaye Gamatieacute and Pierre Boulet Architecture Explo-ration for Ecient Data Transfer and Storage in Data-Parallel ApplicationsIn Euro-Par 2010 - Parallel Processing Ed by Pasqua DAmbra Mario Guar-racino and Domenico Talia Vol 6271 Springer Berlin Heidelberg 2010pp 101116

[I4] Rosilde Corvino Abdoulaye Gamatieacute and Pierre Boulet Design Space Explo-ration for Ecient Data Intensive Computing on SoCs In Handbook of DataIntensive Computing Ed by Borko Furht and Armando Escalante Springer2011 url httphalinriafrinria-00637012en

37

[I5] Jean-Luc Dekeyser Abdoulaye Gamatieacute Samy Meftali and Imran RaqQuadri Models for Co-Design of Heterogeneous Dynamically RecongurableSoCs In Heterogeneous Embedded Systems - Design Theory and PracticeEd by Nicolescu Gabriela OConnor Ian Piguet and Christian Springer2012 26 p url httphalinriafrinria-00525023en

[I6] Abdoulaye Gamatieacute Specication of Data Intensive Applications with DataDependency and Abstract Clocks Anglais In Handbook of Data IntensiveComputing Ed by Borko Furht and Armando Escalante Springer 2011 urlhttphalinriafrinria-00637011en

[I7] Seacutebastien Le Beux Laurent Moss Philippe Marquet and Jean-Luc DekeyserA High Level Synthesis Flow Using Model Driven Engineering In Algorithm-Architecture Matching for Signal and Image Processing Ed by A Gogniat GMilojevic D Morawiec and A Erdogan Vol 73 Lecture Notes in ElectricalEngineering Springer Nov 2010 pp 253274

[I8] Imran Raq Quadri Majdi Elhaji Samy Meftali and Jean-Luc DekeyserFrom MARTE to Recongurable NoCs A model driven design methodol-ogy In Dynamic Recongurable Network-on-Chip Design Innovations forComputational Processing and Communication Ed by Jih-Sheng Shen IGIGlobal Sept 2010

Journals

[J1] Adolf Abdallah Abdoulaye Gamatieacute and Jean-Luc Dekeyser ModeacutelisationUML MARTE de SoC et analyse temporelle baseacutee sur lapproche synchroneIn RSTI - TSI - 302011 Architecture des ordinateurs 30 (2011) pp 10891114 url httphalinriafrinria-00637009en

[J2] Yassine Aydi Mouna Baklouti Jean-Luc Dekeyser and Mohamed Abid AMulti-Level Design Methodology of Multistage Interconnection Network forMPSOCs In International Journal of Computer Applications in Technology(IJCAT) 421-2 (2011) url httphalinriafrinria-00563733en

[J3] M Bakhouya S Suboh J Gaber T El-Ghazawi and S Niar Performanceevaluation and design tradeos of on-chip interconnect architectures In Sim-ulation Modelling Practice and Theory 196 (2011) pp 1496 1505 issn1569-190X doi 101016jsimpat201010008 url httpwwwsciencedirectcomsciencearticlepiiS1569190X10002200

[J4] Mouna Baklouti Yassine Aydi Philippe Marquet Jean-Luc Dekeyser andMohamed Abid Scalable mpNoC for massively parallel systems - Design andimplementation on FPGA In Journal of Systems Architecture 567 (2010)pp 278 292

[J5] Rabie Ben Atitallah Eric Piel Smaiumll Niar Philippe Marquet and Jean-LucDekeyser A fast MPSoC virtual prototyping for intensive signal processingapplications In Microprocessors and Microsystems Embedded Hardware De-sign Journal (July 2011)

[J6] Abou El Hassan Benyamina and Pierre Boulet Multi-objective Mapping forNoC Architectures In Journal of Digital Information Management (JDIM)56 (Dec 2007) pp 378384

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[J7] Pierre Boulet Modeacutelisation et analyse de systegravemes embarqueacutes ou temps-reacuteelavec le prol UML MARTE In Techniques de lIngenieur IN120 (Feb 2011)url httphalinriafrinria-00587386en

[J8] Christian Brunette Jean-Pierre Talpin Abdoulaye Gamatieacute and Thierry Gau-tier A Metamodel for the Design of Polychronous Systems In In Journalof Logic and Algebraic Programming - JLAP Special Issue on Applying Con-currency Research to Industry (Jan 2009)

[J9] Ceacutedric Dumoulin and Anne Etien Morphing de meacutetamodegraveles In LObjet134 (2007) pp 3335 url httpobjete-revuescomarticlejsparticleId=11241

[J10] Marina Egea and Vlad Rusu Formal executable semantics for conformancein the MDE framework In Innovations in Software and Systems Engineering(2010)

[J11] Anne Etien Business processinformation system co-evolution In Ingeacutenieriedes Systegravemes dInformation (ISI) Special issue on Evolution des systegravemes din-formation 146 (2009)

[J12] R Gaignaire Freacutedeacuteric Guyomarch O Moreau S Clenet and B SudretSpeeding Up SSFEM Computation Using Kronecker Tensor Products InIEEE TRANSACTIONS ON MAGNETICS 453 (Mar 2009) pp 14321435

[J13] Abdoulaye Gamatieacute and Thierry Gautier The Signal Synchronous Multi-clock Approach to the Design of Distributed Embedded Systems In IEEETransactions on Parallel and Distributed Systems 215 (2010) pp 641657

[J14] Abdoulaye Gamatieacute Seacutebastien Le Beux Eacuteric Piel Rabie Ben Atitallah AnneEtien Philippe Marquet and Jean-Luc Dekeyser A Model Driven DesignFramework for Massively Parallel Embedded Systems In ACM Transactionson Embedded Computing Systems (TECS) 104 (2011) url httphalinriafrinria-00637595en

[J15] Abdoulaye Gamatieacute Eacuteric Rutten Huafeng Yu Pierre Boulet and Jean-LucDekeyser Model-Driven Engineering and Formal Validation of High-Perfor-mance Embedded Systems In Scalable Computing Practice and Experience(SCPE) 102 (2009)

[J16] Abdoulaye Gamatieacute Thierry Gautier Paul Le Guernic and Jean-PierreTalpin Polychronous Design of Embedded Real-Time Applications In ACMTransactions on Software Engineering and Methodology (TOSEM) 162 (Apr2007)

[J17] Abdoulaye Gamatieacute Eacuteric Rutten Huafeng Yu Pierre Boulet and Jean-LucDekeyser Synchronous Modeling and Analysis of Data Intensive Applica-tions In EURASIP Journal on Embedded Systemseurasip 2008 (July 2008)Article ID 561863 doi 1011552008561863

[J18] Calin Glitia Philippe Dumont and Pierre Boulet Array-OL with delays adomain specic specication language for multidimensional intensive signalprocessing In Multidimensional Systems and Signal Processing (2009)

39

[J19] Calin Glitia Pierre Boulet Eric Lenormand and Michel Barreteau Repet-itive model refactoring strategy for the design space exploration of intensivesignal processing applications In Journal of Systems Architecture 579 (Jan2011) pp 815829 doi 101016jsysarc201012002 url httphalinriafrinria-00605069en

[J20] Khaled Ibrahim and Smaiumll Niar Power-aware Bus Coscheduling for Peri-odic Realtime Applications Running on MPSoC In Transactions on High-Performance Embedded Architecture and Compilation HiPeac 2 (Apr 2009)pp 286306

[J21] Jehangir Khan Smaiumll Niar Mazen Saghir Yassin El-Hillali and Atika RivenqTrade-o Exploration for Target Tracking Application in a Customized Mul-tiprocessor Architecture In EURASIP Journal on Embedded Systems 2009(Nov 2009)

[J22] Seacutebastien Le Beux Philippe Marquet and Jean-Luc Dekeyser A ModelDriven Co-Design Approach for High Perforamnce Embedded Systems Ded-icated to Transport In Studies in Informatics and Control Journal 20084(2008)

[J23] Claire Pagetti Julien Forget Freacutedeacuteric Boniol Mikel Cordovilla and DavidLesens Multi-task implementation of multi-periodic synchronous programsAnglais In Discrete Event Dynamic Systems 213 (2011) pp 307338 urlhttphalinriafrinria-00638936en

[J24] Imran Raq Quadri Samy Meftali and Jean-Luc Dekeyser A Model baseddesign ow for Dynamic Recongurable FPGAs In International Journal ofRecongurable Computing (2009)

[J25] Imran Raq Quadri Huafeng Yu Abdoulaye Gamatieacute Samy Meftali Jean-LucDekeyser and Eacuteric Rutten Targeting Recongurable FPGA based SoCs usingthe MARTE UML prole from high abstraction levels to code generationAnglais In International Journal of Embedded Systems (IJES) 434 (Sept2010) 18 p url httphalinriafrinria-00525015

[J26] Louis Rose Esther Guerra De Lara Juan Anne Etien Dimitrios Kolovos Sand Richard F Paige Generic Model Management In Software and SystemsModeling (2011) in press url httphalinriafrinria-00635200en

[J27] Vlad Rusu Embedding domain-specic modeling languages into Maude spec-ications Anglais In Software and Systems Modeling (2012) To appear doi101007s10270-012-0232-5 url httphalinriafrhal-00660104

[J28] Vlad Rusu Embedding Domain-Specic Modelling Languages in MaudeSpecications Anglais In ACM SIGSOFT Software Engineering Notes 361(Jan 2011) Extended version accepted in the Systems and Software Engineer-ing Journal doi 10114519215321921557 url httphalinriafrinria-00527859en

[J29] Amen Souissi Pierre Boulet Ceacutedric Dumoulin and Michael Launay Modeacuteli-sation centreacutee sur les processus meacutetier pour la geacuteneacuteration complegravete de portailscollaboratifs In Technique et Science Informatiques (TSI) (Nov 2011) urlhttphalinriafrinria-00638298en

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[J30] Melhem Tawk Khaled Ibrahim and Smaiumll Niar Parallel Application Sam-pling in MPSoC Simulation In International Journal on Design Automationfor Embedded Systems (Aug 2010) p 1

[J31] Chiraz Trabelsi Rabie Ben Atitallah Samy Meftali Jean-Luc Dekeyser andAbderrazak Jemai AModel-Driven Approach for Hybrid Power Estimation inEmbedded Systems Design In Eurasip Journal on Embedded Systems (Apr2011) url httphalinriafrinria-00584360en

[J32] Huafeng Yu Abdoulaye Gamatieacute Eacuteric Rutten and Jean-Luc Dekeyser SafeDesign of High-Performance Embedded Systems in an MDE framework InInnovations in Systems and Software Engineering (ISSE) 43 (2008) urlhttptinyurlcom3qr8jz

64 Publications in Conferences and Workshops

[C1] Adolf Abdallah Abdoulaye Gamatieacute and Jean-Luc Dekeyser Correct andEnergy-Ecient Design of SoCs the H264 Encoder Case Study In Interna-tional Symposium on System-on-Chip (SoC2010) Finlande Tampere 2010

[C2] Adolf Abdallah Abdoulaye Gamatieacute and Jean-Luc Dekeyser MARTE-basedDesign of a Multimedia Application and Formal Analysis In Forum on spec-ication and design languages (FDL08) Stuttgart Germany

[C3] Adolf Abdallah Abdoulaye Gamatieacute and Jean-Luc Dekeyser Model-DrivenDesign of Embedded Multimedia Applications on SoCs In 12th EuromicroConference on Digital System Design (DSD2009) Patras Greece Aug 2009

[C4] Adolf Abdallah Abdoulaye Gamatieacute and Jean-Luc Dekeyser ModeacutelisationUML MARTE de SoC et analyse temporelle baseacutee sur lapproche synchroneIn SYMPosium en Architecture de machines (SympA13) Toulouse FranceSept 2009

[C5] George Afonso and Nicolas Belanger Making a MARTE In Aerospace Test-ing International Magazine Mar 2011

[C6] George Afonso Rabie Ben Atitallah and Jean-Luc Dekeyser A Design En-vironment for Recongurable Computing Systems In Systems-on-Chip -System-in-Package Lyon France June 2011

[C7] George Afonso Rabie Ben Atitallah Nicolas Belanger Martial Rubio Jean-Luc Dekeyser and Alexandre Loyer A prototyping environment for high per-formance recongurable computing In 6th International Workshop on Recon-gurable Communication-centric Systems-on-Chip Montpellier France June2011

[C8] George Afonso Rabie Ben Atitallah Nicolas Belanger Martial Rubio Jean-Luc Dekeyser and Stephan Stilkerich Toward Generic and Adaptive AvionicTest Systems In NASAESA Conference on Adaptive Hardware and SystemsSan Diego USA June 2011

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[C9] Bijoy Anthony Jose Abdoulaye Gamatieacute Julien Ouy and Sandeep KumarShukla SMT based false causal loop detection during code synthesis fromPolychronous specications In 9th IEEEACM International Conference onFormal Methods and Models for Codesign (MEMOCODE) Cambridge UnitedKingdom 2011 url httphalinriafrinria-00637574en

[C10] Vincent Aranega Anne Etien and Jean-Luc Dekeyser Using an AlternativeTrace for QVT In Workshop on Multi-Paradigm Modeling Norvegravege OlsoOct 2010

[C11] Vincent Aranega Jean-Marie Mottu Anne Etien and Jean-Luc DekeyserTraceability Mechanism for Error Localization in Model TransformationsIn 4th International Conference on Software and Data Technologies (IC-SOFT2009) Soa Bulgaria July 2009

[C12] Vincent Aranega Jean-Marie Mottu Anne Etien and Jean-Luc DekeyserUsing Traceability to Enhance Mutation Analysis Dedicated to Model Trans-formation In Workshop on Model driven Engineering Verication and Vali-dation Norvegravege Olso Oct 2010

[C13] Rabie Ben Atitallah Smaiumll Niar and Jean-Luc Dekeyser MPSoC Power Es-timation Framework at Transaction Level Modeling In 19th InternationalConference on Microelectronics (ICM 2007) Cairo Egypt Dec 2007

[C14] Yassine Aydi Samy Meftali Mohamed Abid and Jean-Luc Dekeyser Dy-namicity Analysis of Delta MINs for MPSoC Architectures In Confeacuterenceinternationale des Sciences et Techniques de lAutomatique (STA07) SousseTunisie Nov 2007

[C15] Mouna Baklouti Philippe Marquet Mohamed Abid and Jean-Luc DekeyserA Design and an implementation of a parallel based SIMD architecture forSoC on FPGA In Conference on Design and Architectures for Signal andImage Processing (DASIP 2008) Bruxelles Belgium Nov 2008

[C16] Mouna Baklouti Seacutebastien Le Beux Philippe Marquet Mohamed Abid andJean-Luc Dekeyser Implementation of a Simple Massively Parallel ProcessorSystem on FPGA Case Study In First International Conference on Em-bedded Systems amp Critical Applications (ICESCA 2008) Tunis Tunisia May2008

[C17] Mouna Baklouti Philippe Marquet Jean-Luc Dekeyser and Mohamed AbidIP based congurable SIMD massively parallel SoC In 20th InternationalConference on Field Programmable Logic and Applications FPL 2010 ItalieMilano Aug 2010

[C18] Mouna Baklouti Philippe Marquet Jean-Luc Dekeyser and Mohamed AbidRecongurable Communication Networks in a Parametric SIMD Parallel Sys-tem on Chip In 6th International Symposium on Applied Recongurale Com-puting ARC 2010 Ed by Phaophak Sirisuk Fearghal Morgan Tarek El-Ghazawi and Hideharu Amano Vol 5992 Lecture Notes in Computer ScienceThaiumllande Bangkok Springer 2010 pp 110121

42

[C19] Mouna Baklouti Philippe Marquet Mohamed Abid and Jean-Luc DekeyserStudy and Integration of a Parametric Neighbouring Interconnection Networkin a Massively Parallel Architecture on FPGA In The 7th ACSIEEE Inter-national Conference on Computer Systems and Applications (AICCSA-2009)Rabat Morocco May 2009

[C20] Rabie Ben Atitallah Smaiumll Niar Samy Meftali and Jean-Luc Dekeyser AnMPSoC performance estimation framework using transaction level modelingIn IEEE RTCSA2007 Daegu Korea Aug 2007

[C21] Rabie Ben Atitallah Eacuteric Piel Julien Taillard Smaiumll Niar and Jean-LucDekeyser From High Level MPSoC description to SystemC Code Genera-tion In International ModEasy07 Workshop in conjunction with Forum onspecication and Design Languages (FDL07) Barcelona Spain Sept 2007

[C22] Rabie Ben Atitallah Eacuteric Piel Smaiumll Niar Philippe Marquet and Jean-LucDekeyser Multilevel MPSoC simulation using an MDE approach In IEEEInternational SoC Conference (SoCC 2007) Hsinchu Taiwan Sept 2007

[C23] Abou El Hassan Benyamina and Pierre Boulet Multi-objective Mapping forNoC Architectures In 1st International Conference on Digital Communica-tions and Computer Applications Jordan Mar 2007 pp 132139

[C24] Abou El Hassan Benyamina Pierre Boulet A Aroui S Eltar and KarimaDellal Mapping Real Time Applications on NoC Architecture with HybridMulti-objective Algorithm In META10 Intenational Conference on Meta-heuristics and Nature Inspired Computing Tunisie Djerba Island 2010

[C25] AH Benyamina P Boulet and B Beldjilali Multi-objective Mapping forNoC Architectures In International Conference on Metaheuristics and Na-ture Inspired Computing (META08) Oct 2008

[C26] Pierre Boulet Philippe Marquet Eacuteric Piel and Julien Taillard RepetitiveAllocation Modeling with MARTE In Forum on specication and designlanguages (FDL07) Invited paper Barcelona Spain Sept 2007

[C27] A Char C Mraidha Seacutebastien Geacuterard F Terrier and Pierre Boulet DoesCode Generation Promote or Prevent Optimizations In Object Compo-nent Service-Oriented Real-Time Distributed Computing (ISORC) 2010 13thIEEE International Symposium on Ed by IEEE Computer Society EspagneParador of Carmona 2010 pp 7579

[C28] A Char C Mraidha Seacutebastien Geacuterard F Terrier and Pierre BouletToward optimized code generation through model-based optimization InDesign Automation amp Test in Europe Conference amp Exhibition (DATE)2010 Allemagne Dresden 2010 pp 13131316 url httpwwwdate-conferencecomproceedingsPAPERS2010DATE10PDFFILESIP4_05

PDF

[C29] Asma Char Abdoulaye Gamatieacute Antoine Honoreacute Jean-Luc Dekeyser andMohamed Abid Validation de modegraveles dans un cadre dIDM deacutedieacute agrave la con-ception de systegravemes sur puce In 4egravemes Jouneacutees sur lIngeacutenierie Dirigeacutee parles Modegraveles (IDM 08) Mulhouse France June 2008

43

[C30] Sana Cherif Chiraz Trabelsi Samy Meftali and Jean-Luc Dekeyser HighLevel Design of adaptive distributed controller for Partial Dynamic recongu-ration in FPGA In Conference on Design and Architectures for Signal andImage Processing Tampere Finland Sept 2011 url httphalinriafrinria-00609122en

[C31] Sana Cherif Imran Raq Quadri Samy Meftali and Jean-Luc DekeyserModeling recongurable Systems-on-Chips with UML MARTE prole an ex-ploratory analysis In 13th Euromicro Conference on Digital System Design(DSD 2010) France Lille Sept 2010

[C32] Hajer Chtioui Smaiumll Niar and Mohamed Abid Performances evaluation ofmulti-modules caches memories for embedded systems In First InternationalConference on Embedded Systems amp Critical Applications (ICESCA 2008)Tunis Tunisia May 2008

[C33] Hajer Chtioui Rabie Ben Atitallah Smaiumll Niar Mohamed Abid and Jean-Luc Dekeyser A Dynamic Hybrid Cache Coherency Protocol for Shared-Memory MPSoCs In 12th Euromicro Conference on Digital System Design(DSD2009) Patras Greece Aug 2009

[C34] Hajer Chtioui Rabie Ben Atitallah Smaiumll Niar Mohamed Abid and Jean-Luc Dekeyser Gestion de la coheacuterence des caches dans les architecturesMPSoC utilisant des NoC complexes In Rencontres francophones du Paral-leacutelisme (RenPar18) Symposium en Architecture de machines (SympA 2008) Confeacuterence Franccedilaise sur les Systegravemes dExploitation (CFSE) FribourgSwitzerland Feb 2008

[C35] Benoicirct Combemale Laure Gonnord and Vlad Rusu A Generic Tool forTracing Executions Back to a DSMLs Operational Semantics In SeventhEuropean Conference on Modelling Foundations and Applications Vol 6698Lecture Notes in Computer Science Birmingham United Kingdom SpringerVerlag June 2011 pp 3551 url httphalinriafrhal-00593425en

[C36] Mikel Cordovilla Freacutedeacuteric Boniol Julien Forget Eric Noulard and ClairePagetti Developing critical embedded systems on multicore architecturesthe Prelude-SchedMCore toolset In 19th International Conference on Real-Time and Network Systems Irccyn Nantes France Sept 2011 url httphalinriafrinria-00618587en

[C37] Antonio Wendell De Oliveira Rodrigues Freacutedeacuteric Guyomarch and Jean-LucDekeyser A Modeling Approach based on UMLMARTE for GPU Archi-tecture In Symposium en Architectures nouvelles de machines (SympA14)Saint Malo France May 2011 url httphalinriafrinria-00593863en

[C38] Antonio Wendell De Oliveira Rodrigues Freacutedeacuteric Guyomarch and Jean-LucDekeyser Programming Massively Parallel Architectures using MARTE aCase Study In 2nd Workshop on Model Based Engineering for EmbeddedSystems Design (M-BED 2011) on Date Conference 2011 Grenoble FranceMar 2011 url httphalinriafrinria-00578646en

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[C39] Antonio Wendell De Oliveira Rodrigues Freacutedeacuteric Guyomarch Jean-LucDekeyser and Yvonnick Le Menach Automatic Multi-GPU Code Generationapplied to Simulation of Electrical Machines In Compumag 2011 SydneyAustralia July 2011 url httphalinriafrinria-00605645en

[C40] Jean-Luc Dekeyser Seacutebastien Le Beux and Philippe Marquet Une approchemodegravele pour la conception conjointe de systegravemes embarqueacutes hautes perfor-mances deacutedieacutes au transport In Workshop International Logistique amp Trans-port (LT 2007) Sousse Tunisia Nov 2007

[C41] Jean-Luc Dekeyser Imran Raq Quadri and Abdoulaye Gamatieacute TutorialUsing the UML prole for MARTE to MPSoC co-design dedicated to sig-nal processing In Colloque International Teacuteleacutecom 2009 et 6egravemes JourneacuteesJFMMA Agadir Morocco Mar 2009

[C42] Jean-Luc Dekeyser Abdoulaye Gamatieacute Anne Etien Rabie Ben Atitallah andPierre Boulet Using the UML Prole for MARTE to MPSoC Co-Design InFirst International Conference on Embedded Systems amp Critical Applications(ICESCA08) Tunis Tunisia May 2008

[C43] Majdi Elhaji Pierre Boulet Samy Meftali A Zitouni Jean-Luc Dekeyser andR Tourki An MDE approach for modeling network on chip topologies InDesign and Technology of Integrated Systems in Nanoscale Era (DTIS) 20105th International Conference on Tunisie Hammamet 2010

[C44] Majdi Elhaji Pierre Boulet Rached Tourki Abdelkrim Zitouni Jean-LucDekeyser and Samy Meftali Modeling Networks-on-Chip at System Levelwith the MARTE UML prole In M-BED2011 Grenoble France Mar2011 url httphalinriafrinria-00569077en

[C45] Anne Etien Alexis Muller Thomas Legrand and Xavier Blanc CombiningIndependent Model Transformations In ACM Symposium On Applied Com-puting (SAC) Suisse Sierre Mar 2010

[C46] Julien Forget Emmanuel Grolleau and Claire Pagetti Ordonnancement detacircches peacuteriodiques avec preacuteceacutedences eacutetendues sans seacutemaphores In ROADEF2011 Eacutecole Nationale Supeacuterieure des Mines de Saint-Eacutetienne SAINT ETI-ENNE France Mar 2011 url httphalinriafrinria-00563798en

[C47] Julien Forget Emmanuel Grolleau Claire Pagetti and Pascal Richard Dy-namic Priority Scheduling of Periodic Tasks with Extended PrecedencesAnglais In IEEE 16th Conference on Emerging Technologies Factory Au-tomation (ETFA) Toulouse France Sept 2011 doi 101109ETFA20116059015 url httphalinriafrinria-00638941en

[C48] Abdoulaye Gamatieacute A Generic Formal Model for RTOS Synchronous Ap-proach for Rapid Virtual Prototyping In 10th African Conference on Re-search in Computer Science and Applied Mathematics (CARI2010) CocircteDIvoire Yamoussoukro 2010

[C49] Abdoulaye Gamatieacute Design of Streaming Applications on MPSoCs using Ab-stract Clocks Anglais In Design Automation and Test in Europe Conference(DATE2012) Dresden Allemagne 2012 url httphalinriafrhal-00647480en

45

[C50] Abdoulaye Gamatieacute Thierry Gautier and Loiumlc Besnard An Interval-BasedSolution for Static Analysis in the SIGNAL Language In 15th Annual IEEEInternational Conference and Workshop on Engineering of Computer BasedSystems (ECBS 2008) Belfast Northern Ireland IEEE Computer SocietyApr 2008 pp 182190

[C51] Abdoulaye Gamatieacute and Laure Gonnord Static analysis of synchronous pro-grams in signal for ecient design of multi-clocked embedded systems InACM SIGPLANSIGBED conference on Languages compilers and tools forembedded systems LCTES 2011 Chicago IL United States 2011 pp 7180url httphalinriafrinria-00586137en

[C52] Abdoulaye Gamatieacute Vlad Rusu and Eacuteric Rutten Operational Semantics ofthe Marte Repetitive Structure Modeling Concepts for Data-Parallel Appli-cations Design In 9th International Symposium on Parallel and DistributedComputing (ISPDC2010) Turquie Istanbul 2010

[C53] Abdoulaye Gamatieacute Huafeng Yu Gwenaeumll Delaval and Eacuteric Rutten A CaseStudy on Controller Synthesis for Data-Intensive Embedded Systems In6th IEEE Int Conference on Embedded Systems and Software (ICESS09)Hangzhou China May 2009

[C54] Abdoulaye Gamatieacute Eacuteric Rutten Huafeng Yu and Jean-Luc Dekeyser Mod-eling and Formal Validation of High-Performance Embedded Systems In7th International Symposium on Parallel and Distributed Computing (ISPDC2008) Krakow Poland July 2008

[C55] Calin Glitia and Pierre Boulet High Level Loop Transformations for Multidi-mensional Signal Processing Embedded Applications In International Sym-posium on Systems Architectures MOdeling and Simulation (SAMOS VIII)Samos Greece July 2008

[C56] Calin Glitia and Pierre Boulet Interaction between inter-repetition depen-dences and high-level transformations in Array-OL In Conference on Designand Architectures for Signal and Image Processing (DASIP 2009) Sophia An-tipolis France Sept 2009

[C57] Flori Glitia Anne Etien and Ceacutedric Dumoulin Traceability for an MDEApproach of Embedded System Conception In Fourth ECMDA TracibilityWorkshop Berlin Germany June 2008

[C58] Jing Guo Antonio Wendell De Oliveira Rodrigues Jerarajan ThiyagalingamFreacutedeacuteric Guyomarch Pierre Boulet and Sven-Bodo Scholz Harnessing thePower of GPUs without Losing Abstractions in SaC and ArrayOL A Compar-ative Study In HIPS 2011 16th International Workshop on High-Level Par-allel Programming Models and Supportive Environments Anchorage (Alaska)United States May 2011 url httphalinriafrinria-00569100en

[C59] Naim Harb Smaiumll Niar Jehangir Khan and Mazen Saghir A RecongurablePlatform Architecture for an Automotive Multiple-Target Tracking SystemIn Proc 2nd Workshop on Adaptive and Recongurable Embedded Systems(APRES 2009) in conjunction with Esweek (CASES09 CODES+ISSS09EMSOFT09) Grenoble France 2009

46

[C60] Souha Kamoun and Pierre Boulet Model-Based Testing of the ERTMS Sys-tem with SysML and MARTE In MoDeVVa07 (integrating VampV in MDE)Nashville USA Oct 2007

[C61] Souha Kamoun and Pierre Boulet Une approche modegravele pour la geacuteneacuterationde sceacutenarios de tests Application au systegraveme ERTMSETCS In WorkshopInternational Logistique and Transport 2007 Sousse Tunisie Nov 2007

[C62] Jehangir Khan Smaiumll Niar Yassin El Hilali and Jean-Luc Dekeyser An MP-SoC Architecture for the Multiple Target Tracking Application in Driver Assis-tant System In 19th IEEE International Conference Application-specic Sys-tems Architectures and Processors (ASAP08) Leuven Belgium July 2008

[C63] Jehangir Khan Smaiumll Niar Atika Rivenq-menhaj and Yassin El Hilali Mul-tiple Target Tracking System Design for Driver Assistance Application InDesign and Architectures for Signal and Image processing DASIP08 BrussellsBelgium Nov 2008

[C64] Jehangir Khan Smaiumll Niar Atika Menhaj and Yassin El-Hillali Radar BasedCollision Avoidance System Implementation in a Recongurable MPSoC InProc 9th International Conference on ITS Telecommunications (ITST) LilleFrance 2009

[C65] Seacutebastien Le Beux Philippe Marquet and Jean-Luc Dekeyser A DesignFlow to Map Parallel Applications onto FPGAs In 17th IEEE InternationalConference on Field Programmable Logic and Applications FPL AmsterdamNetherlands Aug 2007

[C66] Seacutebastien Le Beux Philippe Marquet and Jean-Luc Dekeyser Multiple Ab-straction Views of FPGA to Map Parallel Application In 3rd InternationalWorkshop on Recongurable Communication Centric System-on-Chips Re-CoSoC Montpellier France June 2007

[C67] Seacutebastien Le Beux Philippe Marquet Antoine Honoreacute and Jean-LucDekeyser A Model Driven Engineering Design Flow to Generate VHDLIn International ModEasy07 Workshop Barcelona Spain Sept 2007 urlhttpwww2liflfrmodeasyworkshophtml

[C68] Elhajji Majdi Brahim Attia Abdelkrim Zitouni Rached Tourki Samy Mef-tali and Jean-Luc Dekeyser FERONOC Flexible and extensible routerimplementation for diagonal mesh topology In Conference on Design andArchitectures for Signal and Image Processing Tampere Finland Sept 2011url httphalinriafrinria-00609117en

[C69] Philippe Marquet Simon Duquennoy Seacutebastien Le Beux Samy Meftali andJean-Luc Dekeyser Massively Parallel Processing on a Chip In ACM IntlConf on Computing Frontiers Ischia Italy May 2007

[C70] David Mendez Anne Etien Alexis Muller and Rubby Casallas TowardsTransformation Migration After Metamodel Evolution In Model and Evolu-tion Wokshop Norvegravege Olso Oct 2010

47

[C71] David Monniaux and Laure Gonnord Using Bounded Model Checking toFocus Fixpoint Iterations Anglais In Static analysis Ed by Eran YahavVol 6887 Lecture notes in Computer Science Venezia Italie Springer 2011pp 369385 doi 101007978-3-642-23702-7_27 url httphalarchives-ouvertesfrhal-00600087en

[C72] Cesar de Moura Julien Taillard Freacutedeacuteric Guyomarch and Ceacutedric DumoulinAdaptation des Templates UML pour la modeacutelisation de composants parameacute-trables application agrave Gaspard2 In 4egravemes Jouneacutees sur lIngeacutenierie Dirigeacuteepar les Modegraveles (IDM 08) Mulhouse France June 2008

[C73] Eacuteric Piel Rabie Ben Atitallah Philippe Marquet Samy Meftali Smaiumll NiarAnne Etien Jean-Luc Dekeyser and Pierre Boulet Gaspard2 from MARTEto SystemC Simulation In Proceeedings of the DATE08 workshop on Model-ing and Analyzis of Real-Time and Embedded Systems with the MARTE UMLprole Mar 2008

[C74] Imran Raq Quadri Samy Meftali and Jean-Luc Dekeyser A MDE designow for implementing Partially Dynamically Recongurable FPGAs In 2ndColloque Nationale of GDR SOC-SIP Paris France June 2008

[C75] Imran Raq Quadri Samy Meftali and Jean-Luc Dekeyser An MDE Ap-proach for Implementing Partial Dynamic Reconguration in FPGAs In16th International Workshop on IP Based System-on-chip IP07 GrenobleFrance Dec 2007

[C76] Imran Raq Quadri Samy Meftali and Jean-Luc Dekeyser Designing dy-namically recongurable SoCs From UML MARTE models to automatic codegeneration In Conference on Design and Architectures for Signal and ImageProcessing (DASIP 2010) Royaume-Uni Edinburgh Oct 2010

[C77] Imran Raq Quadri Samy Meftali and Jean-Luc Dekeyser High LevelModeling of Partially Dynamically Recongurable FPGAs based on MDEand MARTE In Recongurable Communication-centric SoCs (ReCoSoC08)Barcelona Spain July 2008

[C78] Imran Raq Quadri Samy Meftali and Jean-Luc Dekeyser Integrating ModeAutomata Control Models in SoC Co-Design for Dynamically RecongurableFPGAs In International Conference on Design and Architectures for Signaland Image Processing (DASIP 09) Nice France Sept 2009

[C79] Imran Raq Quadri Samy Meftali and Jean-Luc Dekeyser MARTE baseddesign approach for targeting Recongurable Architectures In 2nd Inter-national Conference on Embedded Systems (ESC09) Invited Paper AlgerAlgeria May 2009

[C80] Imran Raq Quadri Samy Meftali and Jean-Luc Dekeyser MARTE basedmodeling approach for Partial Dynamic Recongurable FPGAs In SixthIEEE Workshop on Embedded Systems for Real-time Multimedia (ESTIMe-dia 2008) Atlanta USA Oct 2008

[C81] Imran Raq Quadri Alexis Muller Samy Meftali and Jean-Luc DekeyserMARTE based design ow for Partially Recongurable Systems-on-ChipsIn 17th IFIP IEEE International Conference on Very Large Scale Integration(VLSI-SoC 09) Florianapolis Brazil Oct 2009

48

[C82] Imran Raq Quadri Yassin El-Hillali Samy Meftali and Jean-Luc DekeyserModel based design ow for implementing an Anti-Collision Radar systemIn 9th International IEEE Conference on ITS Telecommunications (ITS-T2009) Lille France Oct 2009

[C83] Imran Raq Quadri Abdoulaye Gamatieacute Pierre Boulet and Jean-LucDekeyser Modeling of Congurations for Embedded System Implementa-tions in MARTE In 1st workshop on Model Based Engineering for EmbeddedSystems Design - Design Automation and Test in Europe (DATE 2010) Alle-magne Dresden Mar 2010

[C84] Imran Raq Quadri Pierre Boulet Samy Meftali and Jean-Luc DekeyserUsing An MDE Approach for Modeling of Interconnection networks In TheInternational Symposium on Parallel Architectures Algorithms and NetworksConference (ISPAN 08) Sydney Australia May 2008

[C85] Santhosh Kumar Rethinagiri Rabie Ben Atitallah and Jean-Luc Dekeyser ASystem Level Power Consumption Estimation for MPSoC In InternationalSymposium on System-on-Chip 2011 Oct 2011

[C86] Santhosh Kumar Rethinagiri Rabie Ben Atitallah Smal Niar Eric Senn andJean-Luc Dekeyser An Eective Approach for Power Consumption Modelingof Complex Processor In GDR SOC-SIP June 2011

[C87] Santhosh Kumar Rethinagiri Rabie Ben Atitallah Smal Niar Eric Senn andJean-Luc Dekeyser Fast and Accurate Hybrid Power Estimation Methodol-ogy for Embedded Systems In Conference on Design and Architectures forSignal and Image Processing (DASIP) Nov 2011

[C88] Santhosh Kumar Rethinagiri Rabie Ben Atitallah Smal Niar Eric Senn andJean-Luc Dekeyser Hybrid System Level Power Consumption Estimation for29FPGA-Based MPSoC In 29th IEEE International Conference on Com-puter Design ICCD 2011 Oct 2011

[C89] Sebastien Revol Safouan Taha Franccedilois Terrier Alain Clouard SeacutebastienGeacuterard Ansgar Radermacher and Jean-Luc Dekeyser Unifying HW Analysisand SoC Design Flows by Bridging Two Key Standards UML and IP-XACTIn Distributed Embedded Systems Design Middleware and Resources IFIP20th World Computer Congress TC10 Working Conference on Distributedand Parallel Embedded Systems (DIPES 2008) September 7-10 2008 MilanoItaly 2008 pp 6978

[C90] Wendell Rodrigues Freacutedeacuteric Guyomarch Jean-Luc Dekeyser and Yvonick LeMenach Parallel Sparse Matrix Solver on the GPU Applied to Simulation ofElectrical Machines In Compumag 2009 Nov 2009

[C91] Louis Rose Anne Etien David Mendez Dimitrios Kolovos Fiona Polackand Richard F Paige Comparing Model-Metamodel and Transformation-Metamodel Co-evolution In Model and Evolution Wokshop Norvegravege OlsoOct 2010

[C92] Vlad Rusu Combining theorem proving and narrowing for rewriting-logicspecications In International Conference on Tests and Proofs EspagneMalaga Springer Verlag 2010

49

[C93] Vlad Rusu Formal Executable Semantics for Conformance in the MDEFramework In Proc 2nd UML amp FM Workshop Artist NoE 2009

[C94] Vlad Rusu and Dorel Lucanu A K-Based Formal Framework for Domain-Specic Modelling Languages In Formal Verication of Object-Oriented Sys-tems Torino Italy Oct 2011 url httphalinriafrinria-00637099en

[C95] Vlad Rusu and Dorel Lucanu K Semantics for OCL - a Proposal for a For-mal Denition for OCL Anglais In 2nd International K Workshop CheileGradistei (Brasov) Roumanie Aug 2011 url httphalinriafrhal-00641199en

[C96] Safouan Taha Ansgar Radermacher Seacutebastien Geacuterard and Jean-LucDekeyser An Open Framework for Detailed Hardware Modeling In In-ternational Symposium on Industrial Embedded Systems (SIES 07) LisbonPortugal July 2007

[C97] Safouan Taha Ansgar Radermacher Jean-Luc Dekeyser and Seacutebastien Ger-ard MARTE UML-based Hardware Design from Modeling to SimulationIn Forum on specication and Design Languages - FDL07 Barcelona - SpainSept 2007

[C98] Julien Taillard Freacutedeacuteric Guyomarch and Jean-Luc Dekeyser A GraphicalFramework for High Performance Computing using an MDE Approach In16th Euromicro International Conference on Parallel Distributed and network-based Processing Toulouse France Feb 2008

[C99] Julien Taillard Freacutedeacuteric Guyomarch and Jean-Luc Dekeyser OpenMP codegeneration based on an Model Driven Engineering approach In The 2008High Performance Computing amp Simulation Conference (HPCS 2008) NicosiaCyprus June 2008

[C100] Julien Taillard Freacutedeacuteric Guyomarch Yvonnick Le Menach Francis Piriouand Jean-Luc Dekeyser Modeacutelisation dune matrice issue de la meacutethode deseacuteleacutements nis In Les meacutethodes numeacuteriques en Electromagneacutetisme (NUM-ELEC 2008) Liegravege Belgium Dec 2008

[C101] Melham Tawk Khaled Ibrahim and Smaiumll Niar Multi-granularity samplingfor simulating concurrent heterogeneous applications In International confer-ence on compilers architectures and synthesis for embedded systems (CASES2008) Atlanta USA Oct 2008

[C102] Abdellatif Tinzefte Yvonick Le Menach Julien Korecki and Freacutedeacuteric Guy-omarch Parallel Direct Solver For The Finite Integration Technique in Elec-trokinetic Problems In Compumag Florianapolis Brazil Nov 2009

[C103] Ramzi Tligue Yassine Aydi Mouna Baklouti Mohamed Abid and Jean-LucDekeyser The design methodology and the implementation of MPSOC basedon Delta MINs on FPGA In The 21th IEEE International Conference onMicroelectronics (ICM2009) arrakech Morocco 2009

[C104] Chiraz Trabelsi Samy Meftali Rabie Ben Atitallah Abderrazak Jemai Jean-Luc Dekeyser and Smaiumll Niar An MDE Approach for Energy ConsumptionEstimation in MPSoC Design In 2nd Workshop on Rapid Simulation andPerformance Evaluation Methods and Tools Italie Pisa Jan 2010 6 p

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[C105] Huafeng Yu Abdoulaye Gamatieacute Eacuteric Rutten and Jean-Luc Dekeyser ModelTransformations from a Data Parallel Formalism towards Synchronous Lan-guages In Forum on specication and Design Languages - FDL07 Barcelona- Spain Sept 2007

[C106] Huafeng Yu Abdoulaye Gamatieacute Eacuteric Rutten and Jean-Luc Dekeyser SafeDesign of High-Performance Embedded Systems in a MDE Framework InFirst IEEE International workshop UML and Formal Methods (UMLampFM08)Kitakyushu Japan Oct 2008

65 Internal Reports

[R1] Adolf Abdallah Abdoulaye Gamatieacute Rabie Ben Atitallah and Jean-Luc De-keyser Correct and Energy-Ecient Design of a Multimedia Application onSoCs Tech rep RR-7715 INRIA Aug 2011 url httphalinriafrinria-00616223en

[R2] Rabie Ben Atitallah et al Gaspard2 UML prole documentation TechnicalReport 0342 INRIA Sept 2007 p 45 url httphalinriafrinria-00171137en

[R3] Pierre Boulet Array-OL Revisited Multidimensional Intensive Signal Process-ing Specication Research Report RR-6113 INRIA Feb 2007 p 24 urlhttphalinriafrinria-00128840en

[R4] Pierre Boulet Formal Semantics of Array-OL a Domain Specic Languagefor Intensive Multidimensional Signal Processing Research Report RR-6467INRIA Mar 2008 p 31 url httphalinriafrinria-00261178en

[R5] Antonio Wendell De Oliveira Rodrigues Freacutedeacuteric Guyomarch and Jean-LucDekeyser An MDE Approach for Automatic Code Generation from MARTEto OpenCL Tech rep RR-7525 INRIA Feb 2011 p 27 url httphalinriafrinria-00563411en

[R6] Antonio Wendell De Oliveira Rodrigues Vincent Aranega Anne EtienFreacutedeacuteric Guyomarch and Jean-Luc Dekeyser Enabling Traceability in anMDE Approach to Improve Performance of GPU Applications Tech rep RR-7720 INRIA Aug 2011 url httphalinriafrinria-00617912en

[R7] Antonio Wendell De Oliveira Rodrigues Vincent Aranega Anne EtienFreacutedeacuteric Guyomarch and Jean-Luc Dekeyser Enabling Traceability in anMDE Approach to Improve Performance of GPU Applications Tech rep RR-7720 INRIA Aug 2011 url httphalinriafrinria-00617912PDFRR-7720pdf

[R8] Ceacutedric Dumoulin and Seacutebastien Geacuterard Have Multiple Views with one SingleDiagram A Layer Based Approach of UML Diagrams Rapport de rechercheRR-7432 INRIA Oct 2010 p 9

[R9] Anne Etien Ceacutedric Dumoulin and Emmanuel Renaux Towards a Unied No-tation to Represent Model Transformation Research Report RR-6187 INRIAMay 2007 p 14 url httpshalinriafrinria-00145204

51

[R10] Abdoulaye Gamatieacute Eacuteric Rutten and Huafeng Yu A Model for the Mixed-Design of Data-Intensive and Control-Oriented Embedded Systems ResearchReport 6589 France INRIA July 2008 url httphalinriafrinria-00293909en

[R11] Abdoulaye Gamatieacute Seacutebastien Le Beux Eacuteric Piel Anne Etien Rabie BenAtitallah Philippe Marquet and Jean-Luc Dekeyser A Model Driven DesignFramework for High Performance Embedded Systems Research Report 6614INRIA Aug 2008 url httphalinriafrinria-00311115en

[R12] Calin Glitia Pierre Boulet Eacuteric Lenormand and Michel Barreteau Repeti-tive Model Refactoring Strategy for the Design Space Exploration of IntensiveSignal Processing Applications Tech rep number not yet available extendedversion INRIA Sept 2009

[R13] Bijoy Anthony Jose Abdoulaye Gamatieacute Matthew Kracht and Sandeep Ku-mar Shukla Improved False Causal Loop Detection in Polychronous Specica-tionof Embedded Software Tech rep INRIA 2011 p 28 url httphalinriafrinria-00637582en

[R14] Seacutebastien Le Beux Philippe Marquet and Jean-Luc Dekeyser Model DrivenEngineering Benets for High Level Synthesis Research Report 6615 INRIA2008 url httphalinriafrinria-00311300en

[R15] Cesar de Moura Anne Etien Julien Taillard Ceacutedric Dumoulin and FreacutedeacutericGuyomarch Component-based Models Going Generic the MARTE Case-Study Research Report 6632 INRIA 2008 url httphalinriafrdocs00319716PDFRR-6632pdf

[R16] Imran Raq Quadri Samy Meftali and Jean-Luc Dekeyser From MARTE todynamically recongurable FPGAs Introduction of a control extension in amodel based design ow Research Report 6862 France INRIA Mar 2009url httphalinriafrinria-00365061en

[R17] Vlad Rusu Laure Gonnord and Benoicirct Combemale Formally Tracing Execu-tions From an Analysis Tool Back to a Domain Specic Modeling LanguagesOperational Semantics Rapport de recherche RR-7423 INRIA Oct 2010

[R18] Huafeng Yu Abdoulaye Gamatieacute Eacuteric Rutten and Jean-Luc Dekeyser ModelTransformations from a Data Parallel Formalism towards Synchronous Lan-guages Rapport de Recherche 6291 INRIA Sept 2007 url httphalinriafrinria-00172302

7 Bibliography outside the project team

[E1] Robin Milner et al Denition of standard ML (revised edition) MIT Press1997

[E2] TH P Athanas and HF Silverman Processor Reconguration Through In-struction Set Metamorphosis IEEE Computer In FASE 1993

52

[E3] Twan Basten et al Model-Driven Design-Space Exploration for EmbeddedSystems The Octopus Toolset In Leveraging Applications of Formal Meth-ods Verication and Validation Ed by Tiziana Margaria and Bernhard Stef-fen Vol 6415 Lecture Notes in Computer Science 101007978-3-642-16558-0_10 Springer Berlin Heidelberg 2010 pp 90105 isbn 978-3-642-16557-3url httpdxdoiorg101007978-3-642-16558-0_10

[E4] Artur Boronat Reiko Heckel and Joseacute Meseguer Rewriting Logic Semanticsand Verication of Model Transformations In FASE Ed by Marsha Chechikand Martin Wirsing Vol 5503 Lecture Notes in Computer Science Springer2009 pp 1833 isbn 978-3-642-00592-3

[E5] Lukai Cai and Daniel Gajski Transaction Level Modeling An Overview InHardwareSoftware Codesign and System Synthesis Oct 2003 pp 1924

[E6] Marsha Chechik and Martin Wirsing eds Fundamental Approaches to Soft-ware Engineering 12th International Conference FASE 2009 Held as Part ofthe Joint European Conferences on Theory and Practice of Software ETAPS2009 York UK March 22-29 2009 Proceedings Vol 5503 Lecture Notes inComputer Science Springer 2009 isbn 978-3-642-00592-3

[E7] Zhimin Chen Richard Neil Pittman and Alessandro Forin Combining multi-core and recongurable instruction set extensions In Proceedings of the 18thannual ACMSIGDA international symposium on Field programmable gatearrays FPGA 10 Monterey California USA ACM 2010 pp 3336 isbn978-1-60558-911-4 doi httpdoiacmorg10114517231121723119url httpdoiacmorg10114517231121723119

[E8] M Clavel F Duraacuten S Eker P Lincoln M Martiacute-Oliet J Meseguer and CLTalcott All About MaudeA High-Performance Logical Framework Vol 4350Lecture Notes in Computer Science Springer 2007

[E9] Jim Cordy Eating our own Dog Food DSLs for Generative and Transforma-tional Engineering In GPCE 2009

[E10] Traian-Florin erb numicro Grigore Rosup3u and Joseacute Meseguer A rewriting logicapproach to operational semantics In Inf Comput 2072 (2009) pp 305340

[E11] N Dhanwada I Lin and V Narayanan A power estimation methodology forsystemC transaction level models In International conference on Hardware-software codesign and system synthesis 2005

[E12] S Dhouib J-P Diguet D Blouin and J Laurent Energy and power con-sumption estimation for embedded applications and operating systems InJournal of Low Power Electronics (JOLPE) 53 (Dec 2009)

[E13] Chucky Ellison and Grigore Rosup3u An Executable Formal Semantics of Cwith Applications In Proceedings of the 39th Symposium on Principles ofProgramming Languages (POPL12) To appear 2012

[E14] Thomas Gawlitza and David Monniaux Improving Strategies via SMT Solv-ing In ESOP Ed by Gilles Barthe Lecture Notes in Computer Science 6602Springer Verlag 2011 pp 236255 isbn 978-3-642-19717-8 doi 101007978-3-642-19718-5_13

53

[E15] Diana Gohringer Thomas Perschke Michael Hubner and Jurgen Becker ATaxonomy of Recongurable Single-Multiprocessor Systems-on-Chip In In-ternational Journal of Recongurable Computing (2009)

[E16] I Gonzalez et al Classication of Application Development for FPGA-BasedSystems In Aerospace and Electronics Conference 2008 NAECON 2008IEEE National July 2008 pp 203 208 doi 101109NAECON20084806547

[E17] Matthias Gries and Kurt Keutzer Building ASIPs The Mescal Methodol-ogy 1st Springer Publishing Company Incorporated 2010 isbn 14419386059781441938602

[E18] Esther Guerra Juan de Lara Dimitrios S Kolovos Richard F Paige andOsmar Marchi dos Santos transML A family of languages to model modeltransformations In MoDELSUML 2010

[E19] JR Hauser and J Wawrzynek GARP A MIPS Processor with a Recon-gurable Coprocessor IEEE Symposium on FPGAS for Custom ComputingMachines In FASE 1997

[E20] E Horta and J W Lockwood Parbit A tool to transform bitles to im-plement partial reconguration of eld programmable gate arrays Wash-ington University Department of Computer Science Tech- nical ReportWUCS0113 In FASE 1993

[E21] M Hubner T Becker and J Becker Real-time LUTBased network topolo-gies for dynamic and partial FPGA self-reconguration IN Proceedings ofthe 17TH Symposium on Integrated Circuits and Systems Design In FASE2004 pp 2832

[E22] IEEE System Verilog httpwwwsystemverilogorg 2005

[E23] IMEC ADRES Processor Tech rep IMEC 2011 url httpwww2imecbecontentuserFileBrochuresGR2011_Leaflet20ADRESpdf

[E24] Oleg Kiselyov and Chung chieh Shan Delimited Continuations in OperatingSystems In CONTEXT Ed by Boicho N Kokinov Daniel C RichardsonThomas Roth-Berghofer and Laure Vieu Vol 4635 Lecture Notes in Com-puter Science Springer 2007 pp 291302 isbn 978-3-540-74254-8

[E25] Boicho N Kokinov Daniel C Richardson Thomas Roth-Berghofer and LaureVieu edsModeling and Using Context 6th International and InterdisciplinaryConference CONTEXT 2007 Roskilde Denmark August 20-24 2007 Pro-ceedings Vol 4635 Lecture Notes in Computer Science Springer 2007 isbn978-3-540-74254-8

[E26] J Laurent N Julien E Senn and E Martin Functional Level Power Anal-ysis An Ecient Approach for Modeling the Power Consumption of ComplexProcessors In Proc Design Automation and Test in Europe DATE ParisFrance Mar 2004

[E27] I Lee H Kim P Yang S Yoo E Chung KChoi JKong and SEo Pow-erViP SoC power estimation framework at transaction level In Proc ASP-DAC 2006

[E28] Xavier Leroy Formal certication of a compiler back-end or programming acompiler with a proof assistant In POPL Ed by J Gregory Morrisett andSimon L Peyton Jones ACM 2006 pp 4254 isbn 1-59593-027-2

54

[E29] G Mariani P Avasare G Vanmeerbeeck C Ykman-Couvreur G PalermoC Silvano and V Zaccaria An industrial design space exploration frame-work for supporting run-time resource management on multi-core systemsIn Design Automation Test in Europe Conference Exhibition (DATE) 2010Mar 2010 pp 196 201

[E30] Joseacute Meseguer and Grigore Rosu The rewriting logic semantics project InTheor Comput Sci 3733 (2007) pp 213237

[E31] Model Driven Engineering Languages and Systems 8th International Confer-ence MoDELS 2005 Montego Bay Jamaica October 2-7 2005 ProceedingsVol 3713 Lecture Notes in Computer Science Springer 2005 isbn 3-540-29010-9

[E32] J Gregory Morrisett and Simon L Peyton Jones eds Proceedings of the 33rdACM SIGPLAN-SIGACT Symposium on Principles of Programming Lan-guages POPL 2006 Charleston South Carolina USA January 11-13 2006ACM 2006 isbn 1-59593-027-2

[E33] Peter D Mosses Modular structural operational semantics In J Log Al-gebr Program 60-61 (2004) pp 195228

[E34] Pierre-Alain Muller Franck Fleurey and Jean-Marc Jeacutezeacutequel Weaving Ex-ecutability into Object-Oriented Meta-languages In MoDELS Vol 3713Lecture Notes in Computer Science Springer 2005 pp 264278 isbn 3-540-29010-9

[E35] H Nikolov M Thompson T Stefanov A Pimentel S Polstra R Bose CZissulescu and E Deprettere Daedalus toward composable multimedia MP-SoC design In Proceedings of the 45th annual Design Automation ConferenceDAC 08 Anaheim California ACM 2008 pp 574579 isbn 978-1-60558-115-6 doi httpdoiacmorg10114513914691391615 url httpdoiacmorg10114513914691391615

[E36] Jon Oldevik Transformation Composition Modelling Framework In Pro-ceedings of the Distributed Applications and Interoperable Systems ConferenceVol 3543 Lecture Notes in Computer Science Springer 2005 pp 108114

[E37] Open SystemC Initiative SystemC World Wide Web document URL httpwwwsystemcorg 2011

[E38] Jens Pilgrim Bert Vanhoo Immo Schulz-Gerlach and Yolande BerbersConstructing and Visualizing Transformation Chains In ECMDA-FA 08Proceedings of the 4th European conference on Model Driven ArchitectureBerlin Germany Springer-Verlag 2008 pp 1732 isbn 978-3-540-69095-5doi httpdxdoiorg101007978-3-540-69100-6_2

[E39] Gordon D Plotkin A structural approach to operational semantics In JLog Algebr Program 60-61 (2004) pp 17139

[E40] SM Qasim SA Abbasi and B Almashary An overview of advanced FPGAarchitectures for optimized hardware realization of computation intensive algo-rithms In Multimedia Signal Processing and Communication Technologies2009 IMPACT 09 International Mar 2009 pp 300 303 doi 101109MSPCT20095164235

55

[E41] M Rashid F Ferrandi K Bertels E Informazione and I Milan hArtesde-sign ow for heterogeneous platforms In Quality of Electronic Design 2009ISQED 2009 International Mar 2009 pp 330 338

[E42] Alieacutenor Richard Alexis Vander Biest Alexis Bartzas Antonis PapanikolaouDimitris Soudris Dragomir Milojevic and Frdric Robert A Multi-CriteriaEstimation Tool for System-on-Chip In DATE09 University Booth NiceFrance Apr 2009

[E43] Joseacute E Rivera Daniel Ruiz-Gonzalez Fernando Lopez-Romero Joseacute Bautistaand Antonio Vallecillo Orchestrating ATL Model Transformations In Procof MtATL 2009 Nantes France July 2009 pp 3446

[E44] Joseacute Eduardo Rivera Francisco Duraacuten and Antonio Vallecillo Formal Spec-ication and Analysis of Domain Specic Languages using Maude In Simu-lation Transactions of the Society for Modeling and Simulation International8511 - 12 (2009) pp 778792

[E45] G Rosup3u and T-F erb numicro An Overview of the K Semantic FrameworkIn Journal of Logic and Algebraic Programming 796 (2010) pp 397434 doi101016jjlap201003012

[E46] Vassiliadis S Wong S Gaydadjiev G Bertels K Kuzmanov G and PanainteEM The MOLEN polymorphic processor In Computers IEEE Transac-tions on 53 (2004) pp 1363 1375

[E47] J Sanchez Cuadrado and J Garcia Molina Approaches for Model Trans-formation Reuse Factorization and Composition In Proceedings of the In-ternational Conference on Model Transformation Vol 5063 LNCS Springer-Verlag 2008 pp 168182

[E48] Peter Schrammel and Bertrand Jeannet Extending Abstract Acceleration toData-Flow Programs with Numerical Inputs In Int Workshop on Numericaland Symbolic Abstract Domains Vol 267 ENTCS 1 Elsevier 2010 pp 101114

[E49] C Silvano W Fornaciari G Palermo V Zaccaria F Castro M MartinezS Bocchio R Zafalon P Avasare G Vanmeerbeeck et al MULTICUBEMulti-objective design space exploration of multi-core architectures In VLSI2010 Annual Symposium Springer 2011 pp 4763

[E50] DE Taylor JW Lockwood and S Dharmapurikar Generalized RAD mod-ule interface specication of the eld programmable port extender (FPX)Washington University Department of Computer Science Version 20 Tech-nical Report In FASE 2000

[E51] The SoCLib Project An Open Modelling and Simulation Platform for Systemon Chip Design httpsocliblip6fr

[E52] The Soclib Website httpswwwsoclibfr

[E53] Bert Vanhoof and Yolande Berbers Breaking up the transformation chainIn Proceedings of the Best Practices for Model-Driven Software Developmentat OOPSLA 2005 San Diego California USA 2005 url http www softmetawarecomoopsla2005vanhooffpdf

56

[E54] Dennis Wagelaar Ragnhild Van Der Straeten and Dirk Deridder Modulesuperimposition a composition technique for rule-based model transformationlanguages In Software and Systems Modeling (2009) Online First doi 101007s10270-009-0134-3

57

Personnel (March 2012)


DR Professors 1 1

CR Assistant Professor 1 3 4

Permanent EngineerTemporary Engineer

PhD Students 8 1 9

Post-Doc 1 1

Total 8 3 4 15


Visitors (gt 1 month)

Changes in sta

DR Professors Misc INRIA CNRS University totalCR Assistant Professors

Arrival 1 4 5Leaving

Comments The changes concern the period until December 2011 University ofLille 1 enrolled 4 assistant professors Vlad Rusu joined DaRT by moving from InriaRennes The new team DaRT was created in January 2012 for one year and PierreBoulet Abdoulaye Gamatieacute Cedric Dumoulin Anne Etien Julien Forget and LaureGonnord are still members of LIFL

Current composition of the project-team (March 2012)

bull Vlad Rusu CR1 Inria Scientic leader

bull Jean-Luc Dekeyser Professor Lille 1

bull Freacutedeacuteric Guyomarch Associate Professor Lille 1

bull Philippe Marquet Associate Professor Lille 1

bull Samy Meftali Associate Professor HdR Lille 1

bull Rabie Ben Atitallah External Collaborator Associate Professor Universiteacute deValenciennes et du Hainaut Cambreacutesis (UVHC)

bull Christophe Calves Post-Doc Researcher Inria

bull George Afonso PhD Student Lille 1 Cifre EADSEurocopter

bull Sana Cherif PhD Student Lille 1 ANR Famous

bull Majdi Elhaji PhD Student co-advising Lille 1FSM Monastir

bull Hana Krichen PhD Student co-advising Lille 1ENIS Sfax

bull Santhosh-Kumar Rethinagiri PhD Student UVHC ANR OpenPeople

2



























3














Other comments



2 Work progress

21 Keywords







4


Design Time


refactoring

Deployed


IP


Target P latforms

OpenMP

Pthread

VHDL

OpenCL

Synchro

System C

TRACEABILITYLOGGING








5











6



241 Personnel









7




244 Collaborations





8



246 Self assessment






251 Personnel




9










10






254 Collaborations



11



256 Self assessment







12





261 Personnel





13








14




264 Collaborations




266 Self assessment


15






271 Personnel




16








17





274 Collaborations




276 Self assessment


18





31 Publications

2007 2008 2009 2010 2011 2012












19















32 Software






bull Version 210


20














bull Version 09





bull Version 10


21






333 Patent


34 Teaching

2007-2008 2008-2009 2009-2010 2010-2011


P Boulet 42 133 32 42 130 32 2 54 74 20 561

J-L Dekeyser 96 96 70 70 70 70 472

C Dumoulin 267 262 237 214 980

A Etien 90 38 140 52 140 52 120 72 704

J Forget 80 48 128

L Gonnord 128 162 30 400

F Guyomarch 212 192 248 652

P Marquet 90 110 90 110 90 110 90 110 800

R Ben Atitallah 24 24 100 112 120 180 560


Embedded Systems

22
























23




36 Visibility

Program Committee








24











25

4 External Funding

(k euros) 2007 2008 2009 2010 2011







Total 286 103 436 979 408 026 521 209 462 548


ARCs


26









27


European projects









3httpwwwlifrmodeasy

28









Other funding


29





51 Context





30





52 State of the art







31







6httpwwwforthorg

32








33








54 Open Problems


34











Books



Habilitation


35

PhD Theses












36




Book Chapters









37





Journals







38













39












40













41











42











PDF


43










44












45











46












47












48












49













50



65 Internal Reports










51













52













53















54













55














56


57



























3














Other comments



2 Work progress

21 Keywords







4


Design Time


refactoring

Deployed


IP


Target P latforms

OpenMP

Pthread

VHDL

OpenCL

Synchro

System C

TRACEABILITYLOGGING








5











6



241 Personnel









7




244 Collaborations





8



246 Self assessment






251 Personnel




9










10






254 Collaborations



11



256 Self assessment







12





261 Personnel





13








14




264 Collaborations




266 Self assessment


15






271 Personnel




16








17





274 Collaborations




276 Self assessment


18





31 Publications

2007 2008 2009 2010 2011 2012












19















32 Software






bull Version 210


20














bull Version 09





bull Version 10


21






333 Patent


34 Teaching

2007-2008 2008-2009 2009-2010 2010-2011


P Boulet 42 133 32 42 130 32 2 54 74 20 561

J-L Dekeyser 96 96 70 70 70 70 472

C Dumoulin 267 262 237 214 980

A Etien 90 38 140 52 140 52 120 72 704

J Forget 80 48 128

L Gonnord 128 162 30 400

F Guyomarch 212 192 248 652

P Marquet 90 110 90 110 90 110 90 110 800

R Ben Atitallah 24 24 100 112 120 180 560


Embedded Systems

22
























23




36 Visibility

Program Committee








24











25

4 External Funding

(k euros) 2007 2008 2009 2010 2011







Total 286 103 436 979 408 026 521 209 462 548


ARCs


26









27


European projects









3httpwwwlifrmodeasy

28









Other funding


29





51 Context





30





52 State of the art







31







6httpwwwforthorg

32








33








54 Open Problems


34











Books



Habilitation


35

PhD Theses












36




Book Chapters









37





Journals







38













39












40













41











42











PDF


43










44












45











46












47












48












49













50



65 Internal Reports










51













52













53















54













55














56


57














Other comments



2 Work progress

21 Keywords







4


Design Time


refactoring

Deployed


IP


Target P latforms

OpenMP

Pthread

VHDL

OpenCL

Synchro

System C

TRACEABILITYLOGGING








5











6



241 Personnel









7




244 Collaborations





8



246 Self assessment






251 Personnel




9










10






254 Collaborations



11



256 Self assessment







12





261 Personnel





13








14




264 Collaborations




266 Self assessment


15






271 Personnel




16








17





274 Collaborations




276 Self assessment


18





31 Publications

2007 2008 2009 2010 2011 2012












19















32 Software






bull Version 210


20














bull Version 09





bull Version 10


21






333 Patent


34 Teaching

2007-2008 2008-2009 2009-2010 2010-2011


P Boulet 42 133 32 42 130 32 2 54 74 20 561

J-L Dekeyser 96 96 70 70 70 70 472

C Dumoulin 267 262 237 214 980

A Etien 90 38 140 52 140 52 120 72 704

J Forget 80 48 128

L Gonnord 128 162 30 400

F Guyomarch 212 192 248 652

P Marquet 90 110 90 110 90 110 90 110 800

R Ben Atitallah 24 24 100 112 120 180 560


Embedded Systems

22
























23




36 Visibility

Program Committee








24











25

4 External Funding

(k euros) 2007 2008 2009 2010 2011







Total 286 103 436 979 408 026 521 209 462 548


ARCs


26









27


European projects









3httpwwwlifrmodeasy

28









Other funding


29





51 Context





30





52 State of the art







31







6httpwwwforthorg

32








33








54 Open Problems


34











Books



Habilitation


35

PhD Theses












36




Book Chapters









37





Journals







38













39












40













41











42











PDF


43










44












45











46












47












48












49













50



65 Internal Reports










51













52













53















54













55














56


57


Design Time


refactoring

Deployed


IP


Target P latforms

OpenMP

Pthread

VHDL

OpenCL

Synchro

System C

TRACEABILITYLOGGING








5











6



241 Personnel









7




244 Collaborations





8



246 Self assessment






251 Personnel




9










10






254 Collaborations



11



256 Self assessment







12





261 Personnel





13








14




264 Collaborations




266 Self assessment


15






271 Personnel




16








17





274 Collaborations




276 Self assessment


18





31 Publications

2007 2008 2009 2010 2011 2012












19















32 Software






bull Version 210


20














bull Version 09





bull Version 10


21






333 Patent


34 Teaching

2007-2008 2008-2009 2009-2010 2010-2011


P Boulet 42 133 32 42 130 32 2 54 74 20 561

J-L Dekeyser 96 96 70 70 70 70 472

C Dumoulin 267 262 237 214 980

A Etien 90 38 140 52 140 52 120 72 704

J Forget 80 48 128

L Gonnord 128 162 30 400

F Guyomarch 212 192 248 652

P Marquet 90 110 90 110 90 110 90 110 800

R Ben Atitallah 24 24 100 112 120 180 560


Embedded Systems

22
























23




36 Visibility

Program Committee








24











25

4 External Funding

(k euros) 2007 2008 2009 2010 2011







Total 286 103 436 979 408 026 521 209 462 548


ARCs


26









27


European projects









3httpwwwlifrmodeasy

28









Other funding


29





51 Context





30





52 State of the art







31







6httpwwwforthorg

32








33








54 Open Problems


34











Books



Habilitation


35

PhD Theses












36




Book Chapters









37





Journals







38













39












40













41











42











PDF


43










44












45











46












47












48












49













50



65 Internal Reports










51













52













53















54













55














56


57











6



241 Personnel









7




244 Collaborations





8



246 Self assessment






251 Personnel




9










10






254 Collaborations



11



256 Self assessment







12





261 Personnel





13








14




264 Collaborations




266 Self assessment


15






271 Personnel




16








17





274 Collaborations




276 Self assessment


18





31 Publications

2007 2008 2009 2010 2011 2012












19















32 Software






bull Version 210


20














bull Version 09





bull Version 10


21






333 Patent


34 Teaching

2007-2008 2008-2009 2009-2010 2010-2011


P Boulet 42 133 32 42 130 32 2 54 74 20 561

J-L Dekeyser 96 96 70 70 70 70 472

C Dumoulin 267 262 237 214 980

A Etien 90 38 140 52 140 52 120 72 704

J Forget 80 48 128

L Gonnord 128 162 30 400

F Guyomarch 212 192 248 652

P Marquet 90 110 90 110 90 110 90 110 800

R Ben Atitallah 24 24 100 112 120 180 560


Embedded Systems

22
























23




36 Visibility

Program Committee








24











25

4 External Funding

(k euros) 2007 2008 2009 2010 2011







Total 286 103 436 979 408 026 521 209 462 548


ARCs


26









27


European projects









3httpwwwlifrmodeasy

28









Other funding


29





51 Context





30





52 State of the art







31







6httpwwwforthorg

32








33








54 Open Problems


34











Books



Habilitation


35

PhD Theses












36




Book Chapters









37





Journals







38













39












40













41











42











PDF


43










44












45











46












47












48












49













50



65 Internal Reports










51













52













53















54













55














56


57



241 Personnel









7




244 Collaborations





8



246 Self assessment






251 Personnel




9










10






254 Collaborations



11



256 Self assessment







12





261 Personnel





13








14




264 Collaborations




266 Self assessment


15






271 Personnel




16








17





274 Collaborations




276 Self assessment


18





31 Publications

2007 2008 2009 2010 2011 2012












19















32 Software






bull Version 210


20














bull Version 09





bull Version 10


21






333 Patent


34 Teaching

2007-2008 2008-2009 2009-2010 2010-2011


P Boulet 42 133 32 42 130 32 2 54 74 20 561

J-L Dekeyser 96 96 70 70 70 70 472

C Dumoulin 267 262 237 214 980

A Etien 90 38 140 52 140 52 120 72 704

J Forget 80 48 128

L Gonnord 128 162 30 400

F Guyomarch 212 192 248 652

P Marquet 90 110 90 110 90 110 90 110 800

R Ben Atitallah 24 24 100 112 120 180 560


Embedded Systems

22
























23




36 Visibility

Program Committee








24











25

4 External Funding

(k euros) 2007 2008 2009 2010 2011







Total 286 103 436 979 408 026 521 209 462 548


ARCs


26









27


European projects









3httpwwwlifrmodeasy

28









Other funding


29





51 Context





30





52 State of the art







31







6httpwwwforthorg

32








33








54 Open Problems


34











Books



Habilitation


35

PhD Theses












36




Book Chapters









37





Journals







38













39












40













41











42











PDF


43










44












45











46












47












48












49













50



65 Internal Reports










51













52













53















54













55














56


57




244 Collaborations





8



246 Self assessment






251 Personnel




9










10






254 Collaborations



11



256 Self assessment







12





261 Personnel





13








14




264 Collaborations




266 Self assessment


15






271 Personnel




16








17





274 Collaborations




276 Self assessment


18





31 Publications

2007 2008 2009 2010 2011 2012












19















32 Software






bull Version 210


20














bull Version 09





bull Version 10


21






333 Patent


34 Teaching

2007-2008 2008-2009 2009-2010 2010-2011


P Boulet 42 133 32 42 130 32 2 54 74 20 561

J-L Dekeyser 96 96 70 70 70 70 472

C Dumoulin 267 262 237 214 980

A Etien 90 38 140 52 140 52 120 72 704

J Forget 80 48 128

L Gonnord 128 162 30 400

F Guyomarch 212 192 248 652

P Marquet 90 110 90 110 90 110 90 110 800

R Ben Atitallah 24 24 100 112 120 180 560


Embedded Systems

22
























23




36 Visibility

Program Committee








24











25

4 External Funding

(k euros) 2007 2008 2009 2010 2011







Total 286 103 436 979 408 026 521 209 462 548


ARCs


26









27


European projects









3httpwwwlifrmodeasy

28









Other funding


29





51 Context





30





52 State of the art







31







6httpwwwforthorg

32








33








54 Open Problems


34











Books



Habilitation


35

PhD Theses












36




Book Chapters









37





Journals







38













39












40













41











42











PDF


43










44












45











46












47












48












49













50



65 Internal Reports










51













52













53















54













55














56


57



246 Self assessment






251 Personnel




9










10






254 Collaborations



11



256 Self assessment







12





261 Personnel





13








14




264 Collaborations




266 Self assessment


15






271 Personnel




16








17





274 Collaborations




276 Self assessment


18





31 Publications

2007 2008 2009 2010 2011 2012












19















32 Software






bull Version 210


20














bull Version 09





bull Version 10


21






333 Patent


34 Teaching

2007-2008 2008-2009 2009-2010 2010-2011


P Boulet 42 133 32 42 130 32 2 54 74 20 561

J-L Dekeyser 96 96 70 70 70 70 472

C Dumoulin 267 262 237 214 980

A Etien 90 38 140 52 140 52 120 72 704

J Forget 80 48 128

L Gonnord 128 162 30 400

F Guyomarch 212 192 248 652

P Marquet 90 110 90 110 90 110 90 110 800

R Ben Atitallah 24 24 100 112 120 180 560


Embedded Systems

22
























23




36 Visibility

Program Committee








24











25

4 External Funding

(k euros) 2007 2008 2009 2010 2011







Total 286 103 436 979 408 026 521 209 462 548


ARCs


26









27


European projects









3httpwwwlifrmodeasy

28









Other funding


29





51 Context





30





52 State of the art







31







6httpwwwforthorg

32








33








54 Open Problems


34











Books



Habilitation


35

PhD Theses












36




Book Chapters









37





Journals







38













39












40













41











42











PDF


43










44












45











46












47












48












49













50



65 Internal Reports










51













52













53















54













55














56


57










10






254 Collaborations



11



256 Self assessment







12





261 Personnel





13








14




264 Collaborations




266 Self assessment


15






271 Personnel




16








17





274 Collaborations




276 Self assessment


18





31 Publications

2007 2008 2009 2010 2011 2012












19















32 Software






bull Version 210


20














bull Version 09





bull Version 10


21






333 Patent


34 Teaching

2007-2008 2008-2009 2009-2010 2010-2011


P Boulet 42 133 32 42 130 32 2 54 74 20 561

J-L Dekeyser 96 96 70 70 70 70 472

C Dumoulin 267 262 237 214 980

A Etien 90 38 140 52 140 52 120 72 704

J Forget 80 48 128

L Gonnord 128 162 30 400

F Guyomarch 212 192 248 652

P Marquet 90 110 90 110 90 110 90 110 800

R Ben Atitallah 24 24 100 112 120 180 560


Embedded Systems

22
























23




36 Visibility

Program Committee








24











25

4 External Funding

(k euros) 2007 2008 2009 2010 2011







Total 286 103 436 979 408 026 521 209 462 548


ARCs


26









27


European projects









3httpwwwlifrmodeasy

28









Other funding


29





51 Context





30





52 State of the art







31







6httpwwwforthorg

32








33








54 Open Problems


34











Books



Habilitation


35

PhD Theses












36




Book Chapters









37





Journals







38













39












40













41











42











PDF


43










44












45











46












47












48












49













50



65 Internal Reports










51













52













53















54













55














56


57






254 Collaborations



11



256 Self assessment







12





261 Personnel





13








14




264 Collaborations




266 Self assessment


15






271 Personnel




16








17





274 Collaborations




276 Self assessment


18





31 Publications

2007 2008 2009 2010 2011 2012












19















32 Software






bull Version 210


20














bull Version 09





bull Version 10


21






333 Patent


34 Teaching

2007-2008 2008-2009 2009-2010 2010-2011


P Boulet 42 133 32 42 130 32 2 54 74 20 561

J-L Dekeyser 96 96 70 70 70 70 472

C Dumoulin 267 262 237 214 980

A Etien 90 38 140 52 140 52 120 72 704

J Forget 80 48 128

L Gonnord 128 162 30 400

F Guyomarch 212 192 248 652

P Marquet 90 110 90 110 90 110 90 110 800

R Ben Atitallah 24 24 100 112 120 180 560


Embedded Systems

22
























23




36 Visibility

Program Committee








24











25

4 External Funding

(k euros) 2007 2008 2009 2010 2011







Total 286 103 436 979 408 026 521 209 462 548


ARCs


26









27


European projects









3httpwwwlifrmodeasy

28









Other funding


29





51 Context





30





52 State of the art







31







6httpwwwforthorg

32








33








54 Open Problems


34











Books



Habilitation


35

PhD Theses












36




Book Chapters









37





Journals







38













39












40













41











42











PDF


43










44












45











46












47












48












49













50



65 Internal Reports










51













52













53















54













55














56


57



256 Self assessment







12





261 Personnel





13








14




264 Collaborations




266 Self assessment


15






271 Personnel




16








17





274 Collaborations




276 Self assessment


18





31 Publications

2007 2008 2009 2010 2011 2012












19















32 Software






bull Version 210


20














bull Version 09





bull Version 10


21






333 Patent


34 Teaching

2007-2008 2008-2009 2009-2010 2010-2011


P Boulet 42 133 32 42 130 32 2 54 74 20 561

J-L Dekeyser 96 96 70 70 70 70 472

C Dumoulin 267 262 237 214 980

A Etien 90 38 140 52 140 52 120 72 704

J Forget 80 48 128

L Gonnord 128 162 30 400

F Guyomarch 212 192 248 652

P Marquet 90 110 90 110 90 110 90 110 800

R Ben Atitallah 24 24 100 112 120 180 560


Embedded Systems

22
























23




36 Visibility

Program Committee








24











25

4 External Funding

(k euros) 2007 2008 2009 2010 2011







Total 286 103 436 979 408 026 521 209 462 548


ARCs


26









27


European projects









3httpwwwlifrmodeasy

28









Other funding


29





51 Context





30





52 State of the art







31







6httpwwwforthorg

32








33








54 Open Problems


34











Books



Habilitation


35

PhD Theses












36




Book Chapters









37





Journals







38













39












40













41











42











PDF


43










44












45











46












47












48












49













50



65 Internal Reports










51













52













53















54













55














56


57





261 Personnel





13








14




264 Collaborations




266 Self assessment


15






271 Personnel




16








17





274 Collaborations




276 Self assessment


18





31 Publications

2007 2008 2009 2010 2011 2012












19















32 Software






bull Version 210


20














bull Version 09





bull Version 10


21






333 Patent


34 Teaching

2007-2008 2008-2009 2009-2010 2010-2011


P Boulet 42 133 32 42 130 32 2 54 74 20 561

J-L Dekeyser 96 96 70 70 70 70 472

C Dumoulin 267 262 237 214 980

A Etien 90 38 140 52 140 52 120 72 704

J Forget 80 48 128

L Gonnord 128 162 30 400

F Guyomarch 212 192 248 652

P Marquet 90 110 90 110 90 110 90 110 800

R Ben Atitallah 24 24 100 112 120 180 560


Embedded Systems

22
























23




36 Visibility

Program Committee








24











25

4 External Funding

(k euros) 2007 2008 2009 2010 2011







Total 286 103 436 979 408 026 521 209 462 548


ARCs


26









27


European projects









3httpwwwlifrmodeasy

28









Other funding


29





51 Context





30





52 State of the art







31







6httpwwwforthorg

32








33








54 Open Problems


34











Books



Habilitation


35

PhD Theses












36




Book Chapters









37





Journals







38













39












40













41











42











PDF


43










44












45











46












47












48












49













50



65 Internal Reports










51













52













53















54













55














56


57








14




264 Collaborations




266 Self assessment


15






271 Personnel




16








17





274 Collaborations




276 Self assessment


18





31 Publications

2007 2008 2009 2010 2011 2012












19















32 Software






bull Version 210


20














bull Version 09





bull Version 10


21






333 Patent


34 Teaching

2007-2008 2008-2009 2009-2010 2010-2011


P Boulet 42 133 32 42 130 32 2 54 74 20 561

J-L Dekeyser 96 96 70 70 70 70 472

C Dumoulin 267 262 237 214 980

A Etien 90 38 140 52 140 52 120 72 704

J Forget 80 48 128

L Gonnord 128 162 30 400

F Guyomarch 212 192 248 652

P Marquet 90 110 90 110 90 110 90 110 800

R Ben Atitallah 24 24 100 112 120 180 560


Embedded Systems

22
























23




36 Visibility

Program Committee








24











25

4 External Funding

(k euros) 2007 2008 2009 2010 2011







Total 286 103 436 979 408 026 521 209 462 548


ARCs


26









27


European projects









3httpwwwlifrmodeasy

28









Other funding


29





51 Context





30





52 State of the art







31







6httpwwwforthorg

32








33








54 Open Problems


34











Books



Habilitation


35

PhD Theses












36




Book Chapters









37





Journals







38













39












40













41











42











PDF


43










44












45











46












47












48












49













50



65 Internal Reports










51













52













53















54













55














56


57




264 Collaborations




266 Self assessment


15






271 Personnel




16








17





274 Collaborations




276 Self assessment


18





31 Publications

2007 2008 2009 2010 2011 2012












19















32 Software






bull Version 210


20














bull Version 09





bull Version 10


21






333 Patent


34 Teaching

2007-2008 2008-2009 2009-2010 2010-2011


P Boulet 42 133 32 42 130 32 2 54 74 20 561

J-L Dekeyser 96 96 70 70 70 70 472

C Dumoulin 267 262 237 214 980

A Etien 90 38 140 52 140 52 120 72 704

J Forget 80 48 128

L Gonnord 128 162 30 400

F Guyomarch 212 192 248 652

P Marquet 90 110 90 110 90 110 90 110 800

R Ben Atitallah 24 24 100 112 120 180 560


Embedded Systems

22
























23




36 Visibility

Program Committee








24











25

4 External Funding

(k euros) 2007 2008 2009 2010 2011







Total 286 103 436 979 408 026 521 209 462 548


ARCs


26









27


European projects









3httpwwwlifrmodeasy

28









Other funding


29





51 Context





30





52 State of the art







31







6httpwwwforthorg

32








33








54 Open Problems


34











Books



Habilitation


35

PhD Theses












36




Book Chapters









37





Journals







38













39












40













41











42











PDF


43










44












45











46












47












48












49













50



65 Internal Reports










51













52













53















54













55














56


57






271 Personnel




16








17





274 Collaborations




276 Self assessment


18





31 Publications

2007 2008 2009 2010 2011 2012












19















32 Software






bull Version 210


20














bull Version 09





bull Version 10


21






333 Patent


34 Teaching

2007-2008 2008-2009 2009-2010 2010-2011


P Boulet 42 133 32 42 130 32 2 54 74 20 561

J-L Dekeyser 96 96 70 70 70 70 472

C Dumoulin 267 262 237 214 980

A Etien 90 38 140 52 140 52 120 72 704

J Forget 80 48 128

L Gonnord 128 162 30 400

F Guyomarch 212 192 248 652

P Marquet 90 110 90 110 90 110 90 110 800

R Ben Atitallah 24 24 100 112 120 180 560


Embedded Systems

22
























23




36 Visibility

Program Committee








24











25

4 External Funding

(k euros) 2007 2008 2009 2010 2011







Total 286 103 436 979 408 026 521 209 462 548


ARCs


26









27


European projects









3httpwwwlifrmodeasy

28









Other funding


29





51 Context





30





52 State of the art







31







6httpwwwforthorg

32








33








54 Open Problems


34











Books



Habilitation


35

PhD Theses












36




Book Chapters









37





Journals







38













39












40













41











42











PDF


43










44












45











46












47












48












49













50



65 Internal Reports










51













52













53















54













55














56


57








17





274 Collaborations




276 Self assessment


18





31 Publications

2007 2008 2009 2010 2011 2012












19















32 Software






bull Version 210


20














bull Version 09





bull Version 10


21






333 Patent


34 Teaching

2007-2008 2008-2009 2009-2010 2010-2011


P Boulet 42 133 32 42 130 32 2 54 74 20 561

J-L Dekeyser 96 96 70 70 70 70 472

C Dumoulin 267 262 237 214 980

A Etien 90 38 140 52 140 52 120 72 704

J Forget 80 48 128

L Gonnord 128 162 30 400

F Guyomarch 212 192 248 652

P Marquet 90 110 90 110 90 110 90 110 800

R Ben Atitallah 24 24 100 112 120 180 560


Embedded Systems

22
























23




36 Visibility

Program Committee








24











25

4 External Funding

(k euros) 2007 2008 2009 2010 2011







Total 286 103 436 979 408 026 521 209 462 548


ARCs


26









27


European projects









3httpwwwlifrmodeasy

28









Other funding


29





51 Context





30





52 State of the art







31







6httpwwwforthorg

32








33








54 Open Problems


34











Books



Habilitation


35

PhD Theses












36




Book Chapters









37





Journals







38













39












40













41











42











PDF


43










44












45











46












47












48












49













50



65 Internal Reports










51













52













53















54













55














56


57





274 Collaborations




276 Self assessment


18





31 Publications

2007 2008 2009 2010 2011 2012












19















32 Software






bull Version 210


20














bull Version 09





bull Version 10


21






333 Patent


34 Teaching

2007-2008 2008-2009 2009-2010 2010-2011


P Boulet 42 133 32 42 130 32 2 54 74 20 561

J-L Dekeyser 96 96 70 70 70 70 472

C Dumoulin 267 262 237 214 980

A Etien 90 38 140 52 140 52 120 72 704

J Forget 80 48 128

L Gonnord 128 162 30 400

F Guyomarch 212 192 248 652

P Marquet 90 110 90 110 90 110 90 110 800

R Ben Atitallah 24 24 100 112 120 180 560


Embedded Systems

22
























23




36 Visibility

Program Committee








24











25

4 External Funding

(k euros) 2007 2008 2009 2010 2011







Total 286 103 436 979 408 026 521 209 462 548


ARCs


26









27


European projects









3httpwwwlifrmodeasy

28









Other funding


29





51 Context





30





52 State of the art







31







6httpwwwforthorg

32








33








54 Open Problems


34











Books



Habilitation


35

PhD Theses












36




Book Chapters









37





Journals







38













39












40













41











42











PDF


43










44












45











46












47












48












49













50



65 Internal Reports










51













52













53















54













55














56


57





31 Publications

2007 2008 2009 2010 2011 2012












19















32 Software






bull Version 210


20














bull Version 09





bull Version 10


21






333 Patent


34 Teaching

2007-2008 2008-2009 2009-2010 2010-2011


P Boulet 42 133 32 42 130 32 2 54 74 20 561

J-L Dekeyser 96 96 70 70 70 70 472

C Dumoulin 267 262 237 214 980

A Etien 90 38 140 52 140 52 120 72 704

J Forget 80 48 128

L Gonnord 128 162 30 400

F Guyomarch 212 192 248 652

P Marquet 90 110 90 110 90 110 90 110 800

R Ben Atitallah 24 24 100 112 120 180 560


Embedded Systems

22
























23




36 Visibility

Program Committee








24











25

4 External Funding

(k euros) 2007 2008 2009 2010 2011







Total 286 103 436 979 408 026 521 209 462 548


ARCs


26









27


European projects









3httpwwwlifrmodeasy

28









Other funding


29





51 Context





30





52 State of the art







31







6httpwwwforthorg

32








33








54 Open Problems


34











Books



Habilitation


35

PhD Theses












36




Book Chapters









37





Journals







38













39












40













41











42











PDF


43










44












45











46












47












48












49













50



65 Internal Reports










51













52













53















54













55














56


57















32 Software






bull Version 210


20














bull Version 09





bull Version 10


21






333 Patent


34 Teaching

2007-2008 2008-2009 2009-2010 2010-2011


P Boulet 42 133 32 42 130 32 2 54 74 20 561

J-L Dekeyser 96 96 70 70 70 70 472

C Dumoulin 267 262 237 214 980

A Etien 90 38 140 52 140 52 120 72 704

J Forget 80 48 128

L Gonnord 128 162 30 400

F Guyomarch 212 192 248 652

P Marquet 90 110 90 110 90 110 90 110 800

R Ben Atitallah 24 24 100 112 120 180 560


Embedded Systems

22
























23




36 Visibility

Program Committee








24











25

4 External Funding

(k euros) 2007 2008 2009 2010 2011







Total 286 103 436 979 408 026 521 209 462 548


ARCs


26









27


European projects









3httpwwwlifrmodeasy

28









Other funding


29





51 Context





30





52 State of the art







31







6httpwwwforthorg

32








33








54 Open Problems


34











Books



Habilitation


35

PhD Theses












36




Book Chapters









37





Journals







38













39












40













41











42











PDF


43










44












45











46












47












48












49













50



65 Internal Reports










51













52













53















54













55














56


57














bull Version 09





bull Version 10


21






333 Patent


34 Teaching

2007-2008 2008-2009 2009-2010 2010-2011


P Boulet 42 133 32 42 130 32 2 54 74 20 561

J-L Dekeyser 96 96 70 70 70 70 472

C Dumoulin 267 262 237 214 980

A Etien 90 38 140 52 140 52 120 72 704

J Forget 80 48 128

L Gonnord 128 162 30 400

F Guyomarch 212 192 248 652

P Marquet 90 110 90 110 90 110 90 110 800

R Ben Atitallah 24 24 100 112 120 180 560


Embedded Systems

22
























23




36 Visibility

Program Committee








24











25

4 External Funding

(k euros) 2007 2008 2009 2010 2011







Total 286 103 436 979 408 026 521 209 462 548


ARCs


26









27


European projects









3httpwwwlifrmodeasy

28









Other funding


29





51 Context





30





52 State of the art







31







6httpwwwforthorg

32








33








54 Open Problems


34











Books



Habilitation


35

PhD Theses












36




Book Chapters









37





Journals







38













39












40













41











42











PDF


43










44












45











46












47












48












49













50



65 Internal Reports










51













52













53















54













55














56


57






333 Patent


34 Teaching

2007-2008 2008-2009 2009-2010 2010-2011


P Boulet 42 133 32 42 130 32 2 54 74 20 561

J-L Dekeyser 96 96 70 70 70 70 472

C Dumoulin 267 262 237 214 980

A Etien 90 38 140 52 140 52 120 72 704

J Forget 80 48 128

L Gonnord 128 162 30 400

F Guyomarch 212 192 248 652

P Marquet 90 110 90 110 90 110 90 110 800

R Ben Atitallah 24 24 100 112 120 180 560


Embedded Systems

22
























23




36 Visibility

Program Committee








24











25

4 External Funding

(k euros) 2007 2008 2009 2010 2011







Total 286 103 436 979 408 026 521 209 462 548


ARCs


26









27


European projects









3httpwwwlifrmodeasy

28









Other funding


29





51 Context





30





52 State of the art







31







6httpwwwforthorg

32








33








54 Open Problems


34











Books



Habilitation


35

PhD Theses












36




Book Chapters









37





Journals







38













39












40













41











42











PDF


43










44












45











46












47












48












49













50



65 Internal Reports










51













52













53















54













55














56


57
























23




36 Visibility

Program Committee








24











25

4 External Funding

(k euros) 2007 2008 2009 2010 2011







Total 286 103 436 979 408 026 521 209 462 548


ARCs


26









27


European projects









3httpwwwlifrmodeasy

28









Other funding


29





51 Context





30





52 State of the art







31







6httpwwwforthorg

32








33








54 Open Problems


34











Books



Habilitation


35

PhD Theses












36




Book Chapters









37





Journals







38













39












40













41











42











PDF


43










44












45











46












47












48












49













50



65 Internal Reports










51













52













53















54













55














56


57




36 Visibility

Program Committee








24











25

4 External Funding

(k euros) 2007 2008 2009 2010 2011







Total 286 103 436 979 408 026 521 209 462 548


ARCs


26









27


European projects









3httpwwwlifrmodeasy

28









Other funding


29





51 Context





30





52 State of the art







31







6httpwwwforthorg

32








33








54 Open Problems


34











Books



Habilitation


35

PhD Theses












36




Book Chapters









37





Journals







38













39












40













41











42











PDF


43










44












45











46












47












48












49













50



65 Internal Reports










51













52













53















54













55














56


57











25

4 External Funding

(k euros) 2007 2008 2009 2010 2011







Total 286 103 436 979 408 026 521 209 462 548


ARCs


26









27


European projects









3httpwwwlifrmodeasy

28









Other funding


29





51 Context





30





52 State of the art







31







6httpwwwforthorg

32








33








54 Open Problems


34











Books



Habilitation


35

PhD Theses












36




Book Chapters









37





Journals







38













39












40













41











42











PDF


43










44












45











46












47












48












49













50



65 Internal Reports










51













52













53















54













55














56


57

4 External Funding

(k euros) 2007 2008 2009 2010 2011







Total 286 103 436 979 408 026 521 209 462 548


ARCs


26









27


European projects









3httpwwwlifrmodeasy

28









Other funding


29





51 Context





30





52 State of the art







31







6httpwwwforthorg

32








33








54 Open Problems


34











Books



Habilitation


35

PhD Theses












36




Book Chapters









37





Journals







38













39












40













41











42











PDF


43










44












45











46












47












48












49













50



65 Internal Reports










51













52













53















54













55














56


57









27


European projects









3httpwwwlifrmodeasy

28









Other funding


29





51 Context





30





52 State of the art







31







6httpwwwforthorg

32








33








54 Open Problems


34











Books



Habilitation


35

PhD Theses












36




Book Chapters









37





Journals







38













39












40













41











42











PDF


43










44












45











46












47












48












49













50



65 Internal Reports










51













52













53















54













55














56


57


European projects









3httpwwwlifrmodeasy

28









Other funding


29





51 Context





30





52 State of the art







31







6httpwwwforthorg

32








33








54 Open Problems


34











Books



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35

PhD Theses












36




Book Chapters









37





Journals







38













39












40













41











42











PDF


43










44












45











46












47












48












49













50



65 Internal Reports










51













52













53















54













55














56


57









Other funding


29





51 Context





30





52 State of the art







31







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32








33








54 Open Problems


34











Books



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35

PhD Theses












36




Book Chapters









37





Journals







38













39












40













41











42











PDF


43










44












45











46












47












48












49













50



65 Internal Reports










51













52













53















54













55














56


57





51 Context





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52 State of the art







31







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32








33








54 Open Problems


34











Books



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35

PhD Theses












36




Book Chapters









37





Journals







38













39












40













41











42











PDF


43










44












45











46












47












48












49













50



65 Internal Reports










51













52













53















54













55














56


57





52 State of the art







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32








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54 Open Problems


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35

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36




Book Chapters









37





Journals







38













39












40













41











42











PDF


43










44












45











46












47












48












49













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65 Internal Reports










51













52













53















54













55














56


57







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54 Open Problems


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36




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39












40













41











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43










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51













52













53















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33








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51













52













53















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56


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52













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56


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39












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53















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55














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57

inria, evaluation of theme tem · 2013-06-10 · rabie ben atitallah, external collaborator,...

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