info tech enhancereferalprogram jds 20sep11

7/28/2019 INFO TECH EnhanceReferalProgram JDs 20Sep11

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Enhanced Referral Program

JOB DESCRIPTIONS

STRESS ANALYSIS

AERO STRUCTURES ANALYSIS ANSYS/ANSYS CLASSIC / NASTRAN / PATRAN /HAND CALCULATIONS:(Job Code: IEL/HYD/ASA)Job Location: Hyderabad3 10 years experience in Aircraft structures, preferably in any one of the following areas: Analysisof Primary & Secondary (Fuselage, Wing, Empennage) structures. Knowledge and handsonexperience in Stress analysis (Composite & Metallic) and to check the detailed stress analysis as perany OEM standards. Knowledge and handson experience in Fatigue & Damage Tolerance analysis(Composite & Metallic). Working knowledge of Patran/Nastran, Abaqus, MathCAD and Excel VBAwill be an added advantage

STRUCTURAL ANALYSIS ENGINEERS ANSYS / NASTRAN / PATRAN /HYPERMESH/ ABAQUS: (Job Code: IEL/HYDBLR/SAE)Job Location: Hyderabad / Bangalore3 10 years experience in finite element modelling and analysis using Ansys or Nastran. Candidatesshould have handson experience with various analysis types such as linear statics, nonlinear statics(contact, material and large deformation), dynamics (normal modes and cyclic modal) etc. Expertisein 2D/3D FE modeling in Ansys or Hypermesh or Patran/Nastran or LS Dyna or Abaqus, for aeroengine/ turbomachinery/automotive/heavy engineering components is preferred. Experience ininterpreting and understanding FEA results, postprocessing and preparing comprehensive analysisreports. Experience with Ansys workbench, FESafe, Motion solve, Optistruct, Harmonic Analysisand Random vibration analysis for dynamics would be an added advantage.

ASIC DESIGN POSITIONS: DESIGN ENGINEERS / Sr. DESIGN ENGINEERS / LEADS

LOGIC DESIGN:(Job Code: IEL/HYD/LD)Experience: 4 to 10 yearsJob Location: Hyderabad / BengaluruCandidate should have worked on following areasMicroarchitecture, Logic Design, RTL Coding,Logic Synthesis, Expertise on ARM and Cortex processors and designing subsystems around them.C/C++, Verilog/VHDL, System Verilog.

VERIFICATION:(Job Code: IEL/HYD/VERF)Experience: 2 to 10 yearsJob Location: Hyderabad / BengaluruCandidate should have worked on following areasBlock level and System level (SoC) verification,Test Bench development, Test Cases development, BFM models, coverage driven verification, Gatelevel simulations, VHDL, System Verilog/e Specman/Vera, Mixed Signal/ VMM/RVM/OVMverification.


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IMPLEMENTATION: (Job Code: IEL/HYD/IMP)Experience: 2 to 10 yearsJob Location: Hyderabad / Bengaluru / VizagCandidate should have worked on following areasLogic Synthesis, Low Power Synthesis, TimingConstraints, Timing Closure, Static Timing Analysis, Cross talk analysis and Repair, FormalVerification.

ANALOG LAYOUT: (Job Code: IEL/HYD/ANALOG)Experience: 3 to 10 yearsJob Location: Hyderabad / BengaluruCandidate should have worked on following areasPcell creation, expertise on PDKs, Floor planning,Device Matching techniques, Routing, Electro Migration prevention techniques, PhysicalVerification, SKILL programming.

PHYSICAL DESIGN: (Job Code: IEL/HYD/PD)Experience: 2 to 10 yearsJob Locations: Hyderabad/ Bangalore / VizagCandidate should have worked on following areasPartitioning, IO ring preparation, Floor planning,PG planning, Place and Route, Clock Tree Synthesis, Timing Closure, Static Timing Analysis, IR dropanalysis, Physical verification, Signal Integrity, Low Power design.PHYSICAL DESIGN MANAGERS: (Job Code: IEL/HYD/PDM)Job location: Hyderabad / Bangalore / VizagCandidate should have 8 to 12years of experience, should be able to manage a team of 10+ physicaldesign engineers with expertise on Partitioning, IO ring preparation, Floor planning, PG planning,Place and Route, Clock Tree Synthesis, Timing Closure, Static Timing Analysis, IR drop analysis,Physical verification, Signal Integrity, Low Power design.

DFT (DESIGN FOR TEST): (Job Code: IEL/HYD/DFT)Experience: 2 to 10 yearsJob Locations: Hyderabad/ Bangalore / VizagCandidate should have worked on following areas JTAG, MBIST, Custom MBIST, Scan, ATPG, Atspeed Scan, Scan Compression, Logic BIST, Silicon bringup on ATE floor


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FPGA DESIGN

FPGA ENGINEERS:( Job Code: IEL/HYD/FPGA)Experience: 2 to 10 yearsJob location: HyderabadAbility to interface with silicon companies and understand their requirements and expectations.Rapidly adapt to different design and verification environments. Coordinate efforts with offshoredesign and verification teams. Strong experience using System Verilog & OVM / VMM Experience inTest Benches. ACTEL based experience would be an added advantage.

Qualification for all the above positions: BE/B.Tech or ME/M.Tech/MS in respective streams.

info tech enhancereferalprogram jds 20sep11

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