inf5430 v2011 register transfer methodology i · sequential add-and-shift multiplier. 1....
TRANSCRIPT
![Page 1: INF5430 V2011 Register Transfer Methodology I · Sequential add-and-shift multiplier. 1. Introduction • How to realize an algorithm in hardware? • Two characteristics of an algorithm:](https://reader030.vdocuments.mx/reader030/viewer/2022040916/5e902b55fd723b077c40bc64/html5/thumbnails/1.jpg)
INF5430 V2011Register Transfer Methodology I
RTL Hardware Design by P. Chu
Chapter 11 1
P.P.ChuRTL Hardware Design Using VHDL
Chapter 11
![Page 2: INF5430 V2011 Register Transfer Methodology I · Sequential add-and-shift multiplier. 1. Introduction • How to realize an algorithm in hardware? • Two characteristics of an algorithm:](https://reader030.vdocuments.mx/reader030/viewer/2022040916/5e902b55fd723b077c40bc64/html5/thumbnails/2.jpg)
Outline1. Introduction 2. Overview of FSMD3. FSMD design of a repetitive-addition
multiplier
RTL Hardware Design by P. Chu
Chapter 11 2
multiplier4. Alternative design of a repetitive-
addition multiplier5. Timing and performance analysis of
FSMD6. Sequential add-and-shift multiplier
![Page 3: INF5430 V2011 Register Transfer Methodology I · Sequential add-and-shift multiplier. 1. Introduction • How to realize an algorithm in hardware? • Two characteristics of an algorithm:](https://reader030.vdocuments.mx/reader030/viewer/2022040916/5e902b55fd723b077c40bc64/html5/thumbnails/3.jpg)
1. Introduction
• How to realize an algorithm in hardware?• Two characteristics of an algorithm:
– Use of variables (symbolic memory location)e.g., n = n + 1 in C
RTL Hardware Design by P. Chu
Chapter 11 3
e.g., n = n + 1 in C– Sequential execution
(execution order is important)
![Page 4: INF5430 V2011 Register Transfer Methodology I · Sequential add-and-shift multiplier. 1. Introduction • How to realize an algorithm in hardware? • Two characteristics of an algorithm:](https://reader030.vdocuments.mx/reader030/viewer/2022040916/5e902b55fd723b077c40bc64/html5/thumbnails/4.jpg)
• E.g., an algorithm: – Summate 4 number– Divide the result by 8– Round the result
• Pseudocode
RTL Hardware Design by P. Chu
Chapter 11 4
![Page 5: INF5430 V2011 Register Transfer Methodology I · Sequential add-and-shift multiplier. 1. Introduction • How to realize an algorithm in hardware? • Two characteristics of an algorithm:](https://reader030.vdocuments.mx/reader030/viewer/2022040916/5e902b55fd723b077c40bc64/html5/thumbnails/5.jpg)
• “Dataflow” implementation in VHDL– Convert the algorithm in to combinational
circuit– No memory elements – The sequence is embedded into the “flow of
data”
RTL Hardware Design by P. Chu
Chapter 11 5
![Page 6: INF5430 V2011 Register Transfer Methodology I · Sequential add-and-shift multiplier. 1. Introduction • How to realize an algorithm in hardware? • Two characteristics of an algorithm:](https://reader030.vdocuments.mx/reader030/viewer/2022040916/5e902b55fd723b077c40bc64/html5/thumbnails/6.jpg)
• VHDL code
RTL Hardware Design by P. Chu
Chapter 11 6
![Page 7: INF5430 V2011 Register Transfer Methodology I · Sequential add-and-shift multiplier. 1. Introduction • How to realize an algorithm in hardware? • Two characteristics of an algorithm:](https://reader030.vdocuments.mx/reader030/viewer/2022040916/5e902b55fd723b077c40bc64/html5/thumbnails/7.jpg)
• Block diagram
RTL Hardware Design by P. Chu
Chapter 11 7
![Page 8: INF5430 V2011 Register Transfer Methodology I · Sequential add-and-shift multiplier. 1. Introduction • How to realize an algorithm in hardware? • Two characteristics of an algorithm:](https://reader030.vdocuments.mx/reader030/viewer/2022040916/5e902b55fd723b077c40bc64/html5/thumbnails/8.jpg)
• Problems with dataflow implementation: – Can only be applied to trivial algorithm – Not flexible
• Can we just share one adder in a time-multiplexing fashion to save hardware resources
RTL Hardware Design by P. Chu
Chapter 11 8
resources• What happen if input size is not fixed(i.e., size is determined by an external input)
![Page 9: INF5430 V2011 Register Transfer Methodology I · Sequential add-and-shift multiplier. 1. Introduction • How to realize an algorithm in hardware? • Two characteristics of an algorithm:](https://reader030.vdocuments.mx/reader030/viewer/2022040916/5e902b55fd723b077c40bc64/html5/thumbnails/9.jpg)
Register Transfer Methodology
• Realized algorithm in hardware• Use register to store intermediate data and
imitate variable• Use a datapath to realize all register
RTL Hardware Design by P. Chu
Chapter 11 9
• Use a datapath to realize all register operations
• Use a control path (FSM) to specify the order of register operation
![Page 10: INF5430 V2011 Register Transfer Methodology I · Sequential add-and-shift multiplier. 1. Introduction • How to realize an algorithm in hardware? • Two characteristics of an algorithm:](https://reader030.vdocuments.mx/reader030/viewer/2022040916/5e902b55fd723b077c40bc64/html5/thumbnails/10.jpg)
• The system is specified as sequence of data manipulation/transfer among registers
• Realized by FSM with a datapath (FSMD)
RTL Hardware Design by P. Chu
Chapter 11 10
• Realized by FSM with a datapath (FSMD)
![Page 11: INF5430 V2011 Register Transfer Methodology I · Sequential add-and-shift multiplier. 1. Introduction • How to realize an algorithm in hardware? • Two characteristics of an algorithm:](https://reader030.vdocuments.mx/reader030/viewer/2022040916/5e902b55fd723b077c40bc64/html5/thumbnails/11.jpg)
2. Overview of FSMD
RTL Hardware Design by P. Chu
Chapter 11 11
![Page 12: INF5430 V2011 Register Transfer Methodology I · Sequential add-and-shift multiplier. 1. Introduction • How to realize an algorithm in hardware? • Two characteristics of an algorithm:](https://reader030.vdocuments.mx/reader030/viewer/2022040916/5e902b55fd723b077c40bc64/html5/thumbnails/12.jpg)
Basic RT operation
• Basic form:
• Interpretation:– At the rising edge of the clock, the source of
registers r r etc are available
RTL Hardware Design by P. Chu
Chapter 11 12
registers rsrc1 rsrc2 . etc are available– The source values are passed to a
combinational circuit that performs f( )– At the next rising edge of the clock, the result
is stored into rdest
![Page 13: INF5430 V2011 Register Transfer Methodology I · Sequential add-and-shift multiplier. 1. Introduction • How to realize an algorithm in hardware? • Two characteristics of an algorithm:](https://reader030.vdocuments.mx/reader030/viewer/2022040916/5e902b55fd723b077c40bc64/html5/thumbnails/13.jpg)
• E.g.,
RTL Hardware Design by P. Chu
Chapter 11 13
![Page 14: INF5430 V2011 Register Transfer Methodology I · Sequential add-and-shift multiplier. 1. Introduction • How to realize an algorithm in hardware? • Two characteristics of an algorithm:](https://reader030.vdocuments.mx/reader030/viewer/2022040916/5e902b55fd723b077c40bc64/html5/thumbnails/14.jpg)
• Implementation example
RTL Hardware Design by P. Chu
Chapter 11 14
![Page 15: INF5430 V2011 Register Transfer Methodology I · Sequential add-and-shift multiplier. 1. Introduction • How to realize an algorithm in hardware? • Two characteristics of an algorithm:](https://reader030.vdocuments.mx/reader030/viewer/2022040916/5e902b55fd723b077c40bc64/html5/thumbnails/15.jpg)
• Multiple RT operations
RTL Hardware Design by P. Chu
Chapter 11 15
![Page 16: INF5430 V2011 Register Transfer Methodology I · Sequential add-and-shift multiplier. 1. Introduction • How to realize an algorithm in hardware? • Two characteristics of an algorithm:](https://reader030.vdocuments.mx/reader030/viewer/2022040916/5e902b55fd723b077c40bc64/html5/thumbnails/16.jpg)
FSM as control path
• FSM is a good to control RT operation– State transition is on clock-by-clock basis– FSM can enforce order of execution– FSM allows branches on execution sequence
RTL Hardware Design by P. Chu
Chapter 11 16
– FSM allows branches on execution sequence
• Normally represented in an extended ASM chart known as ASMD (ASM with datapath) chart
![Page 17: INF5430 V2011 Register Transfer Methodology I · Sequential add-and-shift multiplier. 1. Introduction • How to realize an algorithm in hardware? • Two characteristics of an algorithm:](https://reader030.vdocuments.mx/reader030/viewer/2022040916/5e902b55fd723b077c40bc64/html5/thumbnails/17.jpg)
• E.g.
RTL Hardware Design by P. Chu
Chapter 11 17
• Note: new value of r1 is only available when the FSM exits s1state
![Page 18: INF5430 V2011 Register Transfer Methodology I · Sequential add-and-shift multiplier. 1. Introduction • How to realize an algorithm in hardware? • Two characteristics of an algorithm:](https://reader030.vdocuments.mx/reader030/viewer/2022040916/5e902b55fd723b077c40bc64/html5/thumbnails/18.jpg)
Basic Block Diagram of FSMD
RTL Hardware Design by P. Chu
Chapter 11 18
![Page 19: INF5430 V2011 Register Transfer Methodology I · Sequential add-and-shift multiplier. 1. Introduction • How to realize an algorithm in hardware? • Two characteristics of an algorithm:](https://reader030.vdocuments.mx/reader030/viewer/2022040916/5e902b55fd723b077c40bc64/html5/thumbnails/19.jpg)
3. FSMD design example:Repetitive addition multiplier
• Basic algorithm: 7*5 = 7+7+7+7+7• Pseudo code
RTL Hardware Design by P. Chu
Chapter 11 19
![Page 20: INF5430 V2011 Register Transfer Methodology I · Sequential add-and-shift multiplier. 1. Introduction • How to realize an algorithm in hardware? • Two characteristics of an algorithm:](https://reader030.vdocuments.mx/reader030/viewer/2022040916/5e902b55fd723b077c40bc64/html5/thumbnails/20.jpg)
• ASMD-friendly code
RTL Hardware Design by P. Chu
Chapter 11 20
![Page 21: INF5430 V2011 Register Transfer Methodology I · Sequential add-and-shift multiplier. 1. Introduction • How to realize an algorithm in hardware? • Two characteristics of an algorithm:](https://reader030.vdocuments.mx/reader030/viewer/2022040916/5e902b55fd723b077c40bc64/html5/thumbnails/21.jpg)
• Input:– a_in, b_in: 8-bit
unsigned– clk, reset – start: command
• Output:– r: 16-bit unsigned– ready: status
RTL Hardware Design by P. Chu
Chapter 11 21
• ASMD chart– Default RT operation:
keep the previous value
– Note the parallel execution in op state
![Page 22: INF5430 V2011 Register Transfer Methodology I · Sequential add-and-shift multiplier. 1. Introduction • How to realize an algorithm in hardware? • Two characteristics of an algorithm:](https://reader030.vdocuments.mx/reader030/viewer/2022040916/5e902b55fd723b077c40bc64/html5/thumbnails/22.jpg)
• Construction of the data path– List all RT operations– Group RT operation according to the destination register– Add combinational circuit/mux – Add status circuits
• E.g
RTL Hardware Design by P. Chu
Chapter 11 22
![Page 23: INF5430 V2011 Register Transfer Methodology I · Sequential add-and-shift multiplier. 1. Introduction • How to realize an algorithm in hardware? • Two characteristics of an algorithm:](https://reader030.vdocuments.mx/reader030/viewer/2022040916/5e902b55fd723b077c40bc64/html5/thumbnails/23.jpg)
• E.g., Circuit associated with r register
RTL Hardware Design by P. Chu
Chapter 11 23
![Page 24: INF5430 V2011 Register Transfer Methodology I · Sequential add-and-shift multiplier. 1. Introduction • How to realize an algorithm in hardware? • Two characteristics of an algorithm:](https://reader030.vdocuments.mx/reader030/viewer/2022040916/5e902b55fd723b077c40bc64/html5/thumbnails/24.jpg)
RTL Hardware Design by P. Chu
Chapter 11 24
![Page 25: INF5430 V2011 Register Transfer Methodology I · Sequential add-and-shift multiplier. 1. Introduction • How to realize an algorithm in hardware? • Two characteristics of an algorithm:](https://reader030.vdocuments.mx/reader030/viewer/2022040916/5e902b55fd723b077c40bc64/html5/thumbnails/25.jpg)
• VHDL code: follow the block diagram
RTL Hardware Design by P. Chu
Chapter 11 25
![Page 26: INF5430 V2011 Register Transfer Methodology I · Sequential add-and-shift multiplier. 1. Introduction • How to realize an algorithm in hardware? • Two characteristics of an algorithm:](https://reader030.vdocuments.mx/reader030/viewer/2022040916/5e902b55fd723b077c40bc64/html5/thumbnails/26.jpg)
RTL Hardware Design by P. Chu
Chapter 11 26
![Page 27: INF5430 V2011 Register Transfer Methodology I · Sequential add-and-shift multiplier. 1. Introduction • How to realize an algorithm in hardware? • Two characteristics of an algorithm:](https://reader030.vdocuments.mx/reader030/viewer/2022040916/5e902b55fd723b077c40bc64/html5/thumbnails/27.jpg)
RTL Hardware Design by P. Chu
Chapter 11 27
![Page 28: INF5430 V2011 Register Transfer Methodology I · Sequential add-and-shift multiplier. 1. Introduction • How to realize an algorithm in hardware? • Two characteristics of an algorithm:](https://reader030.vdocuments.mx/reader030/viewer/2022040916/5e902b55fd723b077c40bc64/html5/thumbnails/28.jpg)
RTL Hardware Design by P. Chu
Chapter 11 28
![Page 29: INF5430 V2011 Register Transfer Methodology I · Sequential add-and-shift multiplier. 1. Introduction • How to realize an algorithm in hardware? • Two characteristics of an algorithm:](https://reader030.vdocuments.mx/reader030/viewer/2022040916/5e902b55fd723b077c40bc64/html5/thumbnails/29.jpg)
RTL Hardware Design by P. Chu
Chapter 11 29
![Page 30: INF5430 V2011 Register Transfer Methodology I · Sequential add-and-shift multiplier. 1. Introduction • How to realize an algorithm in hardware? • Two characteristics of an algorithm:](https://reader030.vdocuments.mx/reader030/viewer/2022040916/5e902b55fd723b077c40bc64/html5/thumbnails/30.jpg)
RTL Hardware Design by P. Chu
Chapter 11 30
![Page 31: INF5430 V2011 Register Transfer Methodology I · Sequential add-and-shift multiplier. 1. Introduction • How to realize an algorithm in hardware? • Two characteristics of an algorithm:](https://reader030.vdocuments.mx/reader030/viewer/2022040916/5e902b55fd723b077c40bc64/html5/thumbnails/31.jpg)
• Use of register in decision box– Register is updated when the FSM exits current state– How to represent count_0=‘1’ using register?
RTL Hardware Design by P. Chu
Chapter 11 31
![Page 32: INF5430 V2011 Register Transfer Methodology I · Sequential add-and-shift multiplier. 1. Introduction • How to realize an algorithm in hardware? • Two characteristics of an algorithm:](https://reader030.vdocuments.mx/reader030/viewer/2022040916/5e902b55fd723b077c40bc64/html5/thumbnails/32.jpg)
• Other VHDL coding styles: – Various code segments can be combined – Should always separate registers from
combinational logic– May be a good idea to isolate the main
functional units
RTL Hardware Design by P. Chu
Chapter 11 32
functional units
![Page 33: INF5430 V2011 Register Transfer Methodology I · Sequential add-and-shift multiplier. 1. Introduction • How to realize an algorithm in hardware? • Two characteristics of an algorithm:](https://reader030.vdocuments.mx/reader030/viewer/2022040916/5e902b55fd723b077c40bc64/html5/thumbnails/33.jpg)
• E.g., 2-segment code
RTL Hardware Design by P. Chu
Chapter 11 33
![Page 34: INF5430 V2011 Register Transfer Methodology I · Sequential add-and-shift multiplier. 1. Introduction • How to realize an algorithm in hardware? • Two characteristics of an algorithm:](https://reader030.vdocuments.mx/reader030/viewer/2022040916/5e902b55fd723b077c40bc64/html5/thumbnails/34.jpg)
RTL Hardware Design by P. Chu
Chapter 11 34
![Page 35: INF5430 V2011 Register Transfer Methodology I · Sequential add-and-shift multiplier. 1. Introduction • How to realize an algorithm in hardware? • Two characteristics of an algorithm:](https://reader030.vdocuments.mx/reader030/viewer/2022040916/5e902b55fd723b077c40bc64/html5/thumbnails/35.jpg)
RTL Hardware Design by P. Chu
Chapter 11 35
![Page 36: INF5430 V2011 Register Transfer Methodology I · Sequential add-and-shift multiplier. 1. Introduction • How to realize an algorithm in hardware? • Two characteristics of an algorithm:](https://reader030.vdocuments.mx/reader030/viewer/2022040916/5e902b55fd723b077c40bc64/html5/thumbnails/36.jpg)
4. Alternative design of a repetitive-addition multiplier
• Resource sharing– Hardware can be shared in a time-
multiplexing fashion– Assign the operation in different states
RTL Hardware Design by P. Chu
Chapter 11 36
– Most complex circuits in the FSMD design is normally the functional units of the datapath
• Sharing in repetitive addition multiplier– Addition and decrementing– The same adder can be used in 2 states
![Page 37: INF5430 V2011 Register Transfer Methodology I · Sequential add-and-shift multiplier. 1. Introduction • How to realize an algorithm in hardware? • Two characteristics of an algorithm:](https://reader030.vdocuments.mx/reader030/viewer/2022040916/5e902b55fd723b077c40bc64/html5/thumbnails/37.jpg)
RTL Hardware Design by P. Chu
Chapter 11 37
![Page 38: INF5430 V2011 Register Transfer Methodology I · Sequential add-and-shift multiplier. 1. Introduction • How to realize an algorithm in hardware? • Two characteristics of an algorithm:](https://reader030.vdocuments.mx/reader030/viewer/2022040916/5e902b55fd723b077c40bc64/html5/thumbnails/38.jpg)
RTL Hardware Design by P. Chu
Chapter 11 38
![Page 39: INF5430 V2011 Register Transfer Methodology I · Sequential add-and-shift multiplier. 1. Introduction • How to realize an algorithm in hardware? • Two characteristics of an algorithm:](https://reader030.vdocuments.mx/reader030/viewer/2022040916/5e902b55fd723b077c40bc64/html5/thumbnails/39.jpg)
RTL Hardware Design by P. Chu
Chapter 11 39
![Page 40: INF5430 V2011 Register Transfer Methodology I · Sequential add-and-shift multiplier. 1. Introduction • How to realize an algorithm in hardware? • Two characteristics of an algorithm:](https://reader030.vdocuments.mx/reader030/viewer/2022040916/5e902b55fd723b077c40bc64/html5/thumbnails/40.jpg)
RTL Hardware Design by P. Chu
Chapter 11 40
![Page 41: INF5430 V2011 Register Transfer Methodology I · Sequential add-and-shift multiplier. 1. Introduction • How to realize an algorithm in hardware? • Two characteristics of an algorithm:](https://reader030.vdocuments.mx/reader030/viewer/2022040916/5e902b55fd723b077c40bc64/html5/thumbnails/41.jpg)
• Mealy-controlled operation– Control signals is edge-sensitive– Mealy output is faster and requires fewer states– E.g.,
RTL Hardware Design by P. Chu
Chapter 11 41
![Page 42: INF5430 V2011 Register Transfer Methodology I · Sequential add-and-shift multiplier. 1. Introduction • How to realize an algorithm in hardware? • Two characteristics of an algorithm:](https://reader030.vdocuments.mx/reader030/viewer/2022040916/5e902b55fd723b077c40bc64/html5/thumbnails/42.jpg)
• Mealy control signal for multiplier– load and ab0 states
perform no computation
– Mealy control can be used to
RTL Hardware Design by P. Chu
Chapter 11 42
be used to eliminate ab0 and load states
![Page 43: INF5430 V2011 Register Transfer Methodology I · Sequential add-and-shift multiplier. 1. Introduction • How to realize an algorithm in hardware? • Two characteristics of an algorithm:](https://reader030.vdocuments.mx/reader030/viewer/2022040916/5e902b55fd723b077c40bc64/html5/thumbnails/43.jpg)
• r, n, b register loaded using Mealy signal
RTL Hardware Design by P. Chu
Chapter 11 43
![Page 44: INF5430 V2011 Register Transfer Methodology I · Sequential add-and-shift multiplier. 1. Introduction • How to realize an algorithm in hardware? • Two characteristics of an algorithm:](https://reader030.vdocuments.mx/reader030/viewer/2022040916/5e902b55fd723b077c40bc64/html5/thumbnails/44.jpg)
RTL Hardware Design by P. Chu
Chapter 11 44
![Page 45: INF5430 V2011 Register Transfer Methodology I · Sequential add-and-shift multiplier. 1. Introduction • How to realize an algorithm in hardware? • Two characteristics of an algorithm:](https://reader030.vdocuments.mx/reader030/viewer/2022040916/5e902b55fd723b077c40bc64/html5/thumbnails/45.jpg)
5. Clock rate and Performance of FSMD
• Maximal clock rate– More difficult to analyze because of two
interactive loops– The boundary of the clock rate can be found
RTL Hardware Design by P. Chu
Chapter 11 45
– The boundary of the clock rate can be found– Ref. slide 18 (textbook figure 11.5)
![Page 46: INF5430 V2011 Register Transfer Methodology I · Sequential add-and-shift multiplier. 1. Introduction • How to realize an algorithm in hardware? • Two characteristics of an algorithm:](https://reader030.vdocuments.mx/reader030/viewer/2022040916/5e902b55fd723b077c40bc64/html5/thumbnails/46.jpg)
• Best-case scenario: – Control signals needed at late stage – Status signal available at early stage
RTL Hardware Design by P. Chu
Chapter 11 46
![Page 47: INF5430 V2011 Register Transfer Methodology I · Sequential add-and-shift multiplier. 1. Introduction • How to realize an algorithm in hardware? • Two characteristics of an algorithm:](https://reader030.vdocuments.mx/reader030/viewer/2022040916/5e902b55fd723b077c40bc64/html5/thumbnails/47.jpg)
RTL Hardware Design by P. Chu
Chapter 11 47
![Page 48: INF5430 V2011 Register Transfer Methodology I · Sequential add-and-shift multiplier. 1. Introduction • How to realize an algorithm in hardware? • Two characteristics of an algorithm:](https://reader030.vdocuments.mx/reader030/viewer/2022040916/5e902b55fd723b077c40bc64/html5/thumbnails/48.jpg)
• Worst-case scenario: – Control signals needed at early stage – Status signal available at late stage
RTL Hardware Design by P. Chu
Chapter 11 48
![Page 49: INF5430 V2011 Register Transfer Methodology I · Sequential add-and-shift multiplier. 1. Introduction • How to realize an algorithm in hardware? • Two characteristics of an algorithm:](https://reader030.vdocuments.mx/reader030/viewer/2022040916/5e902b55fd723b077c40bc64/html5/thumbnails/49.jpg)
RTL Hardware Design by P. Chu
Chapter 11 49
![Page 50: INF5430 V2011 Register Transfer Methodology I · Sequential add-and-shift multiplier. 1. Introduction • How to realize an algorithm in hardware? • Two characteristics of an algorithm:](https://reader030.vdocuments.mx/reader030/viewer/2022040916/5e902b55fd723b077c40bc64/html5/thumbnails/50.jpg)
RTL Hardware Design by P. Chu
Chapter 11 50
![Page 51: INF5430 V2011 Register Transfer Methodology I · Sequential add-and-shift multiplier. 1. Introduction • How to realize an algorithm in hardware? • Two characteristics of an algorithm:](https://reader030.vdocuments.mx/reader030/viewer/2022040916/5e902b55fd723b077c40bc64/html5/thumbnails/51.jpg)
• Performance of FSMD– Tc: Clock period– K: # clock cycles to compete the computation– Total time = K * Tc
• K determined by algorithm, input patterns etc.
RTL Hardware Design by P. Chu
Chapter 11 51
etc.
![Page 52: INF5430 V2011 Register Transfer Methodology I · Sequential add-and-shift multiplier. 1. Introduction • How to realize an algorithm in hardware? • Two characteristics of an algorithm:](https://reader030.vdocuments.mx/reader030/viewer/2022040916/5e902b55fd723b077c40bc64/html5/thumbnails/52.jpg)
6. Sequential add-and-shift multiplier
RTL Hardware Design by P. Chu
Chapter 11 52
![Page 53: INF5430 V2011 Register Transfer Methodology I · Sequential add-and-shift multiplier. 1. Introduction • How to realize an algorithm in hardware? • Two characteristics of an algorithm:](https://reader030.vdocuments.mx/reader030/viewer/2022040916/5e902b55fd723b077c40bc64/html5/thumbnails/53.jpg)
RTL Hardware Design by P. Chu
Chapter 11 53
![Page 54: INF5430 V2011 Register Transfer Methodology I · Sequential add-and-shift multiplier. 1. Introduction • How to realize an algorithm in hardware? • Two characteristics of an algorithm:](https://reader030.vdocuments.mx/reader030/viewer/2022040916/5e902b55fd723b077c40bc64/html5/thumbnails/54.jpg)
RTL Hardware Design by P. Chu
Chapter 11 54
![Page 55: INF5430 V2011 Register Transfer Methodology I · Sequential add-and-shift multiplier. 1. Introduction • How to realize an algorithm in hardware? • Two characteristics of an algorithm:](https://reader030.vdocuments.mx/reader030/viewer/2022040916/5e902b55fd723b077c40bc64/html5/thumbnails/55.jpg)
• Note the use of b_next and n_next
• a<<1 and b>>1 require no logic
• 8-bit input– Best: b=0,
K = 1 + 8– Worst: b=255,
RTL Hardware Design by P. Chu
Chapter 11 55
– Worst: b=255, K = 1 + 8*2
• N-bit input: – Worst:
K=2+2*n
![Page 56: INF5430 V2011 Register Transfer Methodology I · Sequential add-and-shift multiplier. 1. Introduction • How to realize an algorithm in hardware? • Two characteristics of an algorithm:](https://reader030.vdocuments.mx/reader030/viewer/2022040916/5e902b55fd723b077c40bc64/html5/thumbnails/56.jpg)
RTL Hardware Design by P. Chu
Chapter 11 56
![Page 57: INF5430 V2011 Register Transfer Methodology I · Sequential add-and-shift multiplier. 1. Introduction • How to realize an algorithm in hardware? • Two characteristics of an algorithm:](https://reader030.vdocuments.mx/reader030/viewer/2022040916/5e902b55fd723b077c40bc64/html5/thumbnails/57.jpg)
RTL Hardware Design by P. Chu
Chapter 11 57
![Page 58: INF5430 V2011 Register Transfer Methodology I · Sequential add-and-shift multiplier. 1. Introduction • How to realize an algorithm in hardware? • Two characteristics of an algorithm:](https://reader030.vdocuments.mx/reader030/viewer/2022040916/5e902b55fd723b077c40bc64/html5/thumbnails/58.jpg)
RTL Hardware Design by P. Chu
Chapter 11 58
![Page 59: INF5430 V2011 Register Transfer Methodology I · Sequential add-and-shift multiplier. 1. Introduction • How to realize an algorithm in hardware? • Two characteristics of an algorithm:](https://reader030.vdocuments.mx/reader030/viewer/2022040916/5e902b55fd723b077c40bc64/html5/thumbnails/59.jpg)
• Refinement– No major computation done in the shift state:
the add and shift states can be merged– Data path can be simplified:
• Replace 2n-bit adder with (n+1)-bit adder• Reduce the a register from 2n bits to n bits• Use the lower part of the p register to store B and
RTL Hardware Design by P. Chu
Chapter 11 59
• Use the lower part of the p register to store B and eliminate the b register
![Page 60: INF5430 V2011 Register Transfer Methodology I · Sequential add-and-shift multiplier. 1. Introduction • How to realize an algorithm in hardware? • Two characteristics of an algorithm:](https://reader030.vdocuments.mx/reader030/viewer/2022040916/5e902b55fd723b077c40bc64/html5/thumbnails/60.jpg)
RTL Hardware Design by P. Chu
Chapter 11 60
![Page 61: INF5430 V2011 Register Transfer Methodology I · Sequential add-and-shift multiplier. 1. Introduction • How to realize an algorithm in hardware? • Two characteristics of an algorithm:](https://reader030.vdocuments.mx/reader030/viewer/2022040916/5e902b55fd723b077c40bc64/html5/thumbnails/61.jpg)
RTL Hardware Design by P. Chu
Chapter 11 61