indeterminism detection in scicos - aminer · in this paper, we present a new methodology to detect...

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Simulation Modelling Practice and Theory 12 (2004) 327–349

Indeterminism detection in scicos

Rachid Djenidi

INRIA Rocquencourt, P.O. Box 105, 78153 Le Chesnay Cedex, France

Received 14 October 2002; received in revised form 1 March 2004; accepted 9 March 2004

Available online 30 April 2004

Abstract

Scicos is a dynamic hybrid (continuous time, discrete time) system simulator. Such sys-

tems can be designed in a graphical environment with connected basic blocks, which represent

computational functions. From the simplicity of modeling of such systems, in certain cases like

multi-clock diagrams, simulation is indeterministic due to the simultaneous activation of

blocks from asynchronous activation sources. Because of this indeterminism, the simulation

results of modeled systems may be different. In complex diagrams, checking indeterminism

is very difficult. Therefore, we have proposed a detection method to check indeterminism auto-

matically, with the aim of guaranteeing the specification validity of modeled systems.

� 2004 Elsevier B.V. All rights reserved.

Keywords: Hybrid dynamic systems; Hybrid simulation; Indeterminism detection; Scicos

1. Introduction

In this paper, we present a new methodology to detect indeterminism in Scicos

diagrams. Scicos (Scilab Connected Object Simulator) is a Scilab1 toolbox

for modeling and simulating hybrid dynamic systems, i.e., systems including both

continuous and discrete time and event driven components. So Scicos is intended

to be a simulation environment in which both continuous systems and discrete sys-

tems co-exist. Such hybrid systems can be simulated using both a ODE solver

or(and) a DAE solver. Scicos includes a graphical editor for constructing models

by interconnecting blocks, representing predefined basic functions or user defined

E-mail address: [email protected] (R. Djenidi).1Scilab is a free scientific software package resembling Matlab. Scilab can be downloaded from

http://www.scilab.org.

1569-190X/$ - see front matter � 2004 Elsevier B.V. All rights reserved.

doi:10.1016/j.simpat.2004.03.002

mail to: [email protected]

328 R. Djenidi / Simulation Modelling Practice and Theory 12 (2004) 327–349

functions, a simulator and a code generator [3–6,8–15]. Blocks are available in Pal-

ettes or can be designed by the user. For example, in Fig. 1, hybrid system is made

up of a continuous part (sinusoid generator and an integrator block) and

a discrete part (linear system and scope block).

Indeterminism problems can be encountered in very different research fields and

not only for timing analysis (see for example: Integration of Systems On Chip

[16], Presentation of distributed multimedia documents [17] or Simulation of quan-

tum chaos [18], . . .)).

2. Scicos

Scicos is based on a formalism inspired by synchronous languages such as

Signal [1,2] and in particular its extension to continuous time [7]. There are how-

ever important differences with respect to this latter work. In particular, Scicos is

an event-triggered data store machine, it is not data-flow driven (even though thereis a mechanism that allows it to behave as such). The extension to continuous time is

made by considering permanent activation in continuous time as just another event.

This is done by proposing the notion of fictitious clock which generates this ‘‘perma-

nent activation’’ event which is used to trigger, i.e., permanently activate, the corres-

ponding blocks [12].

The conditional subsampling of events also works on this special type of event

allowing, for example, the generation of activation events over intervals of time

(e.g., x equals integral of u while y > 0). The Scicos formalism is described hereusing an unambiguous syntax which is graphics-oriented, for modeling very general

hybrid systems.

2.1. Signals

Signals in Scicos are generated by blocks activated by activation signals of event

type. The outgoing signals of output activation ports are activation signals generated

Fig. 1. A simple hybrid system.

the signal remains constant betweenthe activation times

time

cotinuous activation

discrete activation

regular

signal

interval

time (events)

Fig. 2. A Scicos signal with its activation times.

Fig. 3. A discret Scicos block-diagram.

R. Djenidi / Simulation Modelling Practice and Theory 12 (2004) 327–349 329

by the block. In Fig. 2, we can see a representation of both activation signals (used to

update a block) and the regular output signal obtained. We observe that between

events the block is not updated and the regular signal remains constant. If activation

of the block is continuous (here by intervals): the block is updated continuously and

the regular output signal evolves in continuous time.

In Fig. 3, the Clock block generates an activation signal composed of a periodic

pulse train of events, at its activation output port. The port is connected to the acti-

vation input port of Scope, 1, 2 and 4 blocks. Each event specifies the time to up-date the activated block. The Scope block is sampled at activation times for display.

2.2. Types of blocks

In Scicos, each block is defined by two distinct functions. The first is a Gui

function, which specifies the type of block, some various information (for example


about the input and output ports) and an interactive function to receive information

from the user. The second function is a Simulation function, which specifies what

the block has to do at event times. There are four main types of block: Standard,

Synchro, Zcross and Memo. These blocks can have two types of input and two types

of output ports: regular inputs, activation inputs, regular outputs and activation out-

puts ports. Regular inputs and outputs are interconnected by regular links, and acti-

vation inputs and outputs, by activation links. Note that activation input ports are

placed on top and activation output ports at the bottom of the blocks. In Fig. 3 allblocks are Standard, except block 1 which is a Synchro. The Synchro block is a spe-

cial case because the outgoing generated event is synchronous with the received event

on its input activation port. It is not worth saying that the activation order of the

blocks is very important to update them when an event is received. As an example

assume in Fig. 3, that the order for each activation (generated by Clock block)

to update the blocks is 2–4, 1–3, 5. This means blocks 2 and 4 (or 4 and 2)

are updated first, then blocks 1–3 (synchronous), and finally the MScope block.

2.2.1. Standard blocks

Standard blocks can have a continuous state x and a discrete state z (see Fig. 4). Ifit does have an x and if u denotes its regular input, then, when the block is active over

an interval of time, x evolves continuously according to

_x ¼ f ðt; x; z; u; p; neÞ; ð1Þ

parameters

parametersReal

Integer

Continuous state register x

Activation

times

register:

"tvec"Regular input

ports

activation input ports

activation output ports

Discrete state register z

Regular output

registers

Regular output ports

Fig. 4. Inside a Standard block.


where f is a vector function, p is a vector of constant parameters and ne is the

activation code which is an integer designating the port(s) through which the

block is activated. In particular, if activating input ports are i1; i2; . . . ; in, then

ne ¼Xn

j¼1

2ij�1:

On the other hand, activated by an event, the states x and z jump instantaneously

according to the following equations:

xðteÞ ¼ gcðte; xðt�e Þ; zðt�e Þ; uðteÞ; p; neÞ; ð2Þ

zðteÞ ¼ gdðte; xðt�e Þ; zðt�e Þ; uðteÞ; p; neÞ; ð3Þ

where te denotes the event time. The discrete state z remains constant between any

two successive events so zðt�e Þ can be interpreted as the previous value of z.During activation times, the regular output of the block is defined by

yðtÞ ¼ hðt; xðt�Þ; zðt�Þ; uðtÞ; p; neÞ ð4Þ

and is constant when the block is not active.

Finally, Standard blocks can generate activation signals. If a Standard block is

activated by an event at time te, the time of each output event is given by

tevo ¼ kðte; zðteÞ; uðteÞ; p; neÞ; ð5Þ

where tevo is a vector of time, each entry of which corresponds to one activation

output port. The absence of an event corresponds to a time smaller than the current

time. Event generations can also be pre-scheduled. Pre-scheduling of events can be

done by setting the initial firing variables of blocks with event output ports.

2.2.2. Zcross blocks

Zero crossing block (Zcross) can generate event outputs only if at least one of theregular inputs crosses zero (changes sign). In such a case, the generation of the event,

and its timing, can depend on the combination of the inputs which have crossed zero

and the signs of the inputs just before the crossing occurs (Fig. 5).

tevo is the activation time of a generated event.

tevo ¼ Tzðte; uðteÞ; pÞq.

2.2.3. Synchro blocks

Synchro blocks generate output activation signals that are synchronized with theirinput activation signals. These blocks have a unique activation input port; they route

their input activation signals to one of their activation outputs (Fig. 6). The choice of

this output (coded by an integer ns) depends on the value of the regular input u and

the specific function of the block (for example if u > 0). nsðteÞ ¼ lðte; uðteÞ; pÞThe synchronization between received and generated activations can allow sub-

sampling of other blocks.

Real parameters

Activation input port

Integer parameters

Regular input port: u

Activationoutputports

Fig. 6. A Synchro block.

Real parameters

Integer parameters

Regular input ports

activation output ports

Register of generated activation times: "tvec"

Fig. 5. Inside a Zcross block.


2.2.4. Memo blocks

Memo blocks are designed to be used in the case of algebraic loops in Scicos

diagrams. Memo blocks have only a regular output register which is updated at

the same time as the discrete register of Standard blocks.In fact, to understand how a Memo block is updated, we have to know how block

registers are updated in Scicos diagrams. For this, we need to present the registers

update scheduling and we shall return to Memo blocks later.


2.2.5. Registers update scheduling

Each block can have two types of input and output: regular and activation.

When a block receives an activation on its activation input port(s), three updates

may be processed. First, regular output registers (if there are any) are updated

according to internal states (continuous and discrete, if there are any). The obtained

values define the regular output signal on regular output port(s) of the block. In the

second step, internal states (continuous and discrete, if any) are updated according to

their regular input signals and previous internal states. And finally, the Scicos sim-ulator programs the possible event(s) for the block’s activation output port(s).

Need of state registers. Let us consider a simple example to show the utility to use

a state register inside blocks. In Fig. 7, we suppose that we want to design a counter

from a block containing only one output register. The values of regular output signal

are directly stored in the output register.

If we implement a feedback in Fig. 8, there is an algebraic loop. Indeed, if Y de-

notes the outgoing regular signal, it is not possible to compute: 1þ Y ¼ Y. The solu-

tion is to use a second internal register (see Fig. 9) in which the previous value ofregular output signal is stored for each iteration of simulation algorithm.

1 +Regular output signal: Y

Block generating a constant valueAlgebraic loop

Fig. 8. A simple example of algebraic loop.

state outputregisterregister

Step 2 Step 1

Fig. 9. A block with a state register.

Scicos block

Output register

Fig. 7. A simple block.


To use the state register as a memory, both registers have to be updated asynchro-

nously: Step 1 (update of the regular output register) and Step 2 (update of the state

register).

The update order of both registers have to be defined, because there is two pos-

sibilities: option 1/2 (Step 1 then Step 2) or option 2/1 (Step 2 then Step 1).

2.2.6. Choice of the update order

We show here that choice of the right option, which seems to affect only the initialconditions, can have more important consequences. As an example assume Fig. 10,

where the Delay block contains a discrete state register z and a regular output regis-

ter y (see Fig. 11).

In the case of option 2/1, when the Delay block is activated, regular input sig-

nal value is stored first in z register, then after in y register. The outgoing signal on

the regular output port of Delay block is illustrated on the top of Fig. 12. The dotted

lines specify the times when the Delay bloc is activated.

In the case of option 1/2, when the Delay block is activated, the value con-tained in z register is stored in y register. Then, a new value (of regular input signal)

is stored in z register. The outgoing signal on the regular output port of Delay block

is illustrated on the bottom of Fig. 12.

Signals obtained in Fig. 12 for both options, are clearly different: with option 2/1,

the Delay block samples and holds its regular input signal.

sin (t) Delay

Activation signal

Fig. 10. A hybrid diagram.

yzsin (t)

Activation signal

Step 2 Step 1

Fig. 11. Inside the Delay block.

if u > 0

fy

elsethen

if u > 0

gz

elsethen

u

Fig. 13. No delay is introduced with the option 1/2.

Option 1 2

Option 2 1

Fig. 12. Results from diagram Fig. 10.


In Fig. 13, we observe that option 1/2 does not add a delay:

y ¼ f ðuÞ if u > 0;

z ¼ gðuÞ if y > 0:

The value of z signal is independant from the current value of u signal

(Fig. 14).

Step 2 Step 1

Step 2

Fig. 14. The Memo block.


On the other hand, with the option 2/1 we obtain:

y ¼ f ðuÞ if $u > 0;

z ¼ gðuÞ if $y > 0;

where $ specify the previous value. In this case, the value of z signal depends from the

two previous value of u signal.

Therefore, the update order used in Scicos is with option 1/2.

2.2.7. Memo blocks (continue)

The update of regular outputs of Memo blocks and Standard blocks is managed

differently. Note that Zcross and Synchro blocks have no regular output. We haveseen that Standard blocks can have several registers: for continuous states, discrete

states, regular output signals, activation output signals,. . .). The continuous state

register of all blocks is a part of the main continuous state register of the system.

During the system simulation, the numerical solver updates the main continuous

state register. Discrete state register of Standard blocks is updated just after updating

their regular output ports registers. Regular output port registers of Memo blocks

and discrete state register of Standard blocks are updated at the same time. Memo

blocks are designed to be directly connected with only Synchro block.When a Memo block is activated at time te, the outgoing signal y is updated (see

Eq. (6)). Between activations the y value of y signal remains constant.

yðtÞ ¼ mðte; uðt�e Þ; pÞ: ð6Þ

2.3. Links

To simplify diagrams representation, activation links of continuous time activated

blocks do not appears but implicitely exist. In fact, a fictitious clock generates a per-

manent activation [12]. The fictitious clock acts exactly like a discrete time Clock

but just for continuous time block. In the case of multi-clock diagram, it is required

to define at first an update scheduling for each output activation port (fictitious andother) to be delivered to the Scicos simulator.


2.4. Compilation

The update scheduling is obtained after Compilation phase, which is the

important phase of process before Simulation. The Compilation provides

two pieces of coded information:

1. For Graphical Code: hierarchical structure is expanded into a single diagram con-

taining no Super-blocks 2 and all the purely graphical and GUI information is dis-carded. Therefore, we obtain a new numbering for blocks and the two connexions

matrix (regular ports:‘‘cmat’’, activation ports:‘‘ccmat’’).

2. For Scheduler Code: the order in which the simulation routine of blocks must be

called is computed and stored in tables.

3. Indeterminisms

3.1. Introduction

The problem which is considered here is indeterminisms in diagrams. Activations

are considered synchronous in Scicos if and only if they are generated by the same

AS3 block (possibly through the other blocks) at the same time. For example, in

diagram Fig. 15 events activating blocks 1 and 2 can be simultaneous, but not syn-

chronous. So, in the case where activations, generated by blocks 1 and 2 are simul-

taneous (so asynchronous), they are generated in an indefinite order because thereare two possibilities:

• Activation on the upstream4 block occurs before activation on the down-

stream5 block. Here, upstream and downstream blocks are directly con-

nected.

• Activation on the downstream block occurs before activation on the upstream

block.

In Fig. 16, the curve represents an example of SIG signal generated from the reg-

ular output port of the upstream block for the three activation times ta; tb; tc.T bloc upstream ¼ fta; tb; tc; . . .g is the set of activation times of the upstream block gen-

erating the regular SIG signal. We can observe that signal values, taken into account

at the regular input port of the downstream block, are clearly different if up-

stream block is activated just before or just after the downstream block.

2 A Super-block is a graphical facility representing a sub-diagram.3 This block being the origin of the Activation Source.4 This means the block whose regular output port is directly connected to the regular input port of a

given block.5 This means the block whose regular input port is directly connected to the regular output port of a

given block.

Fig. 15. A simple example of potential indeterminism.

activation times

"SIG" signal remains constant between

activation times o f upstream block

ta tb tc

Fig. 16. Signal values of the upstream block at the downstream block input port.


3.2. ‘‘AS’’ block

In Scicos, the activation signals can be generated by a (regular type) dis-

crete time activated block (for example the Clock block in Fig. 15) or by a Zcross

block (continuous time activated). In Fig. 17 an example is illustrated with an AS

block using Zcross blocks. To simulate such diagrams, Scicos uses a numerical sol-

ver (of ODE type) to compute the zero-crossing times for Zcross blocks.

In case where activations generated by Zcross blocks are simultaneous (not pos-sible synchronization), we can also have two orders to activate blocks 1 and 2. For

both orders, the simulation results have been performed and are explained in the fol-

lowing sections.

3.2.1. Block 1 activated before block 2

To generate simultaneous activation from blocks 1 and 2, we have to use the same

frequency and phase parameters for both sinusoid generator blocks. To generate

activations on block 1 exactly before activations on block 2, we have changed the

0 3 6 9 12 15 18 21 24 27 300.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

Fig. 18. Results obtained by block 3.

Fig. 17. An example with modified Fig. 15.


frequency of one sinusoid generator block a little (see Fig. 18). Simulation results are

shown in Fig. 19.

3.2.2. Block 1 activated after block 2

Then, in the same way we changed the frequency of the other sinusoid generator

block to generate activations on block 1 exactly after activations on block 2 (see Fig.

20). Comparing both simulation results in Figs. 19 and 21, and noticing the differ-

ence between them leads us to observe indeterminism problems in certain multi-clockdiagrams, for simultaneous activations.

3.3. Principle of indeterminism detection

Because possible indeterminisms can exist in a block diagram containing more

than one AS block, it could be useful to detect them automatically. The method pro-

posed below guaranties the design specifications of a diagram. The principle is to

consider a regular link (l) between two blocks (a, b) and find the AS blocks(ASa and ASb) of each block and then compare them. For example in the diagram

Fig. 19. Results obtained by MScope block.

0 3 6 9 12 15 18 21 24 27 300.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

Fig. 20. Results are not the same as in Fig. 18.

Fig. 21. Results are not the same as in Fig. 19.


a

link ”l ”

AS b

Oa ObIb

AS a

b

Fig. 22. Comparison between AS blocks conditioning a and b blocks.


in Fig. 22, the comparison can be expressed by the following equation:

8l 2 L, 9 a, b, ASa and ASb 2 B=Oa ¼ Ib, with Oa ¼ f ðASaÞ and Ob ¼ gðASb; IbÞ,where B is the set of blocks and L is the set of regular links in a Scicos diagram.

a; b;ASa and ASb are Scicos blocks, Oa;Ob is the regular output port respectively of

blocks a and b (activated respectively by blocks ASa and ASb). Ia and Ib specify the

regular input port of blocks a and b. f and g are specific functions respectively of aand b blocks.

Note that indeterminism problems only concern discrete time activated blocks.

Indeed, in Scicos, continuous time blocks are activated by the union of a fictitious

Clock and all AS blocks contained in a diagram. Consequently, activations receivedby continuous time blocks are synchronous with activations received by any discrete

time block. In diagram in Fig. 22, let us replace ASa block by the fictitious Clock.

If we consider that AS0 represents the fictitious Clock generating permanent activa-

tion: 8b;ASa 2 B; 8ASa ¼ AS0 with ASb 6¼ AS0, if 9Ob ¼ gðASb; f ðAS0Þ then T ASb �T AS0 . T ASb and T AS0 being the set of activation times generated respectively from

blocks ASb and AS0.In a more general way, regarding the diagram in Fig. 22, we write: 8ASa 6¼ ASb

with (ASa 6¼ AS0 and ASb 6¼ AS0), if 9Ob ¼ gðASb; f ðASaÞ=ðT a \ T bÞ 6¼ ;, then an in-determinism exists.

3.3.1. Detection via regular links inspection

The diagram in Fig. 24 contains two meshes, one of which is formed by blocks 3,

7 and 8. It is easy to understand that indeterminism cannot exist if activations be-

tween AS blocks 3 and 1 are simultaneous (the same is true for AS blocks 3 and

2). Indeed, there are no connections between blocks activated by block 3 and the

other blocks. So, a such example illustrates the first conclusion: potential indetermin-ism does not exist for blocks which have no dependance by regular links. Note that

in simple diagrams containing relatively few blocks, checking indeterminism can be

visual and fast, but detection can be complex and tedious when the number of blocks

increases or if diagrams contain Super-blocks.

3.3.2. No indeterminism when activations are inherited?

In Scicos, to reduce the number of links in a diagram, it is useless to draw the

activation links of all the blocks. For example the activation links of continuous time

a

link ”l ”

AS a

Oa ObIb

b

Fig. 23. Avoiding indeterminism by activations inheritence.


activated blocks never appear. Let us consider the diagram in Fig. 23 which differs

from the diagram in Fig. 22 in that: block b is now updated by inheritance fromthe activations of block a. It is assumed by the activation of blocks a and b from

the same block ASa: Ob ¼ gðf ðASaÞ. Throughout this document, for reason of brev-

ity, the term of inheritance indicates inheritance from activations. The inheritance

coding is done at the begining of the compilation step.

Similarly, in the example of Fig. 24, block 8 inherits from the activation of block

7. Thus, the second conclusion is that there is no indeterminism between two con-

nected blocks if the downstream block inherits from the activations of the up-

stream block.As we saw before, the comparison between the blocks is based on regular links,

but the previous conclusion is not trivial (see Fig. 25) when we consider a link con-

necting two blocks where only the upstream block (a) is inheriting. Then, to compare

the AS blocks activating blocks a and b, we have to find the AS block activating the

block from which block a inherits.

We can observe such case in Fig. 26, between blocks 4 and 5. Block 4 inherits the

union of blocks 1 and 2 activations, so blocks 4 and 5 are activated in a synchro-

Fig. 24. Potential indeterminism between blocks 4 and 5.

a

link ”l ”

ASb

Oa ObI b

b

Fig. 25. Only upstream block inherits.

Fig. 26. Only block 4 inherits.


nous way by block 1. We can guarantee so that there is no indeterminism between

blocks 4 and 5.

3.3.3. Using Synchro blocks

In the example of Fig. 27, block b is activated by block 2 through a chain of two

Synchro blocks (If then Else blocks). To find the AS block (in this case it is block

2) we have to search upward in the tree of the synchronous activations, through each

Synchro block concerned. Note that searching in the tree of blocks makes the process

complex and time consuming.

Activations generated from Synchro block output ports are exclusive, so we have:

T Synchro ¼ T SynchroIf [ T Synchro

Else . T Synchro being the set of activation times received on

the activation input port of the Synchro block. Where sub-sampling from activationoutputs of the Synchro block: SASynchro ¼ SAIf

Synchro � SAElseSynchro. � operator indicates

the union of exclusive activation times.

3.3.4. Using Memo blocks

Memo blocks are used to break algebraic loops, thanks to the delay that has been

introduced in the blocks’ update, there is no possible indeterminism:

OMemoðk þ 1Þ ¼ fmemoðASMemoðkÞ; IMemoðk þ 1ÞÞ. k specifies an activation occurrence,

Fig. 27. The search for the AS block through Synchro blocks.

Fig. 28. An example with a Memo block.


k plus specifies the next activation occurrence. For example, we can see in Fig. 28, a

diagram using a Memo block: in the case where blocks 1 and 2 generate simulta-

neous activations, OMemoðk plusÞ ¼ fmemoðASMemoðkÞ; fsawtoothðT 2ðk plusÞÞ. There isno indeterminism between sawtooth generator block and Mem block.

3.4. An example

Let us take the example of Fig. 29, in which block 6 is permanently activated (by a

fictitious block 0). Block 4 and MScope block inherit from blocks 1, 2 and 0 acti-

vations. So, Block 4 and MScope block are also permanently activated. All regular

links are specified in the ‘‘cmat’’ matrix, where each line indicates which regular out-put port of an upstream block is connected to the regular input port of a downstream

Fig. 29. Using two AS blocks.


block. Therefore, we can check indeterminisms by using a ‘‘ccmat’’ matrix (where all

activation links are specified) to compare AS blocks activating the two connected

blocks specified in each line of ‘‘cmat’’.

cmat ¼

Upstream Output Downstream Inputbock port block port9 1 5 1

9 1 3 1

5 1 4 2

6 1 4 3

7 1 8 1

7 1 4 1

4 1 10 28 1 10 1

2666666666666664

3777777777777775

Comparison between blocks 9 and 5: Block 9 is activated by block 2 and block 5 isactivated by block 1: O5 ¼ f ðAS5; gðAS9ÞÞ () O5 ¼ f ðT 1; gðT 2ÞÞ, with f and g being

the specific functions of blocks 5 and 9 respectively. T 1 and T 2 specify the set of acti-

vation times of blocks 1 and 2. There is a potential indeterminism in the case where

AS blocks (1 and 2) generate activations simultaneously.

Comparison between blocks 9 and 3: Both blocks are activated by the same AS

block (2). Indeed, block 3 has no regular output port: AS3 \ AS9 () T 2 \ T 2. There

is no potential indeterminism.

Comparison between blocks 5 and 4: As we have seen previously, block 4 is per-manently activated: O4 ¼ hðAS0; T 1Þ, with h being the specific function of block 4.

There is no potential indeterminism.

Comparison between blocks 6 and 4: As we have seen previously, both blocks are

permanently activated: O4 ¼ hðAS0;AS0Þ so a potential indeterminism cannot exist.

Comparison between blocks 7 and 8: Both blocks are activated by the same AS

block (2) via block 3: O8 ¼ vðAS8; rðAS7ÞÞ, with v and r being the specific functions


of blocks tt 8 and tt 7 respectively. Block 3 is Synchro type: T 7 [ T 8 ¼ T 3. As pre-

viously: AS3 \ AS9 () T 2 \ T 2. There is no potential indeterminism. Note that as

block 3 outputs are exclusive: T 7 6¼ T 8, indeterminism between blocks 7 and 8 can-

not exist.

Comparison between blocks 7 and 4: As we have already seen, block 4 is perma-

nently activated, so: there is no potential indeterminism.

Comparison between blocks 4 and 10:Here the same is true again and for the same

reason: therefore no potential indeterminism detected will be detected.Comparison between blocks 8 and MScope block:We have seen previously that the

MScope block is permanently activated: therefore no potential indeterminism will be

detected.

3.5. Detection process

At first glance there appear to be two ways to deal with indeterminisms in a Sci-

cos diagram:

1. Detect and localize indeterminism by highlighting the blocks concerned. In this

case, the user is warned about indeterminisms and is advanced to modify the

diagram to avoid them.

2. Or simply discard the possibility of designing multi-clock diagrams in Scicos.

It is clear that the second solution is not reasonable, because it reduces the pos-

sibilities of modeling complex dynamic systems. So, the first solution is chosen,and Check tool is introduced.

In the compilation stage of diagram, one of important steps is activation inher-

itance coding (if any) for each block. To detect indeterminisms, we need informa-

tion about inheritance. So Check tool must be run just after this step of

compilation.

The algorithm, illustrated in Fig. 30, is applied on the cmat matrix. Each iteration

concerns one line of the cmat matrix: that is a link from the regular output port of

an Upstream block to the regular input port of a downstream block.

1. If upstream (or downstream) blocks are of the Memo type, there is no inde-

terminism. Check the next line of the cmat matrix for indeterminism detection

(i.e. next iteration).

2. If upstream block is permanently activated (continuous time) or constant gen-

erator block: no indeterminism. Check the next line of the cmat matrix for inde-

terminism detection (i.e. next iteration).

3. If downstream block inherits, there is no indeterminism. Check the next line ofthe cmat matrix for indeterminism detection (i.e. next iteration).

4. If downstream block is not inheriting but is activated by a block (see the Cond_-

down block in Fig. 30). Note that if a Cond_down block is Synchro type, we

need to find which AS block activates it. In the algorithm, this means a recursive

loop on the ccmat matrix. Then, we can have two cases:

”C”

i+1

”R”

no

no

no

no

yes

yes

yes

yes

yes

no

yes

no

yes

no

i ≥ total number ofcmat matrix lines ?

or constant generator ?

or constant generator ?

R:Change with previous blockC:Change with conditioning block

DS: downstream” blockUS: upstream” block

Cond_down=Cond_up ?

Cond__down:block conditioning DSCond__up:block conditioning US

next line ofcmat matrix ?

Memo type ?

STOP

Is US (or DS)

or permanently activated,

Is US Memo type,or permanently activated,

Is Cond_down (or Cond_up)Synchro type ?

Highlight DS and US block

i=1

Is DS inheriting,

Is US inheriting?

(first row of the cmat matrix)”

”

Fig. 30. Brief description of the Check tool algorithm.



• Upstream block is inheriting: a recursive loop on the cmat matrix to find the

primitive upstream block (not inheriting).

• Upstream block is not inheriting but activated by a Cond_up block. Note that if

a Cond_up block is Synchro type, we need to find which AS block activates it.

In the algorithm, this means a recursive loop on the ccmat matrix.

Then, we compare the Cond_down block with the Cond_up block. If they are the

same block: no indeterminism, otherwise: downstream and upstream blocks arehighlighted. After a new iteration, the Check tool algorithm tests the blocks con-

cerned by the next line of the cmat matrix.

4. Conclusion

We have briefly presented the specification language of Scicos in order to intro-

duce, through several examples, the necessity of detecting potential indeterminismsin multi-clock diagrams. Indeterminism is the consequence of the large possibilities

allowed in Scicos to model hybrid dynamical systems. A new contribution (Check

tool) has been introduced to detect and isolate indeterminisms automatically. One

example of a Check tool application is to use it prior to Code generation [14]. In-

deed, automatic code generation exists in Scicos only for single-clock diagrams

(or sub-diagrams). Using Check tool we could easily verify that a diagram is sin-

gle-clock activated. A lot of research fields, dealing with indeterminism problems,

can be considered by the Scicos modeling, thanks to its multi-clock aspects abilities.We can imagine that in certain cases, partial environment reductions can be adapted

to discuss in the sense of the proposed work.

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indeterminism detection in scicos - aminer · in this paper, we present a new methodology to detect...

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