in3170/4170, spring 2020 · why do an asic? well,whynot? i...
TRANSCRIPT
![Page 2: IN3170/4170, Spring 2020 · Why do an ASIC? Well,whynot? I Costly(development,designiterationtime,production) I Inflexibleandlowlevelofreusability Alternatives? I EmbeddedSystems](https://reader034.vdocuments.mx/reader034/viewer/2022051607/602d1a9aaa36eb0c662ed359/html5/thumbnails/2.jpg)
Content
Why Application Specific Integrated Circuits?
Why Transistor Level Digital?
Why Analog?
Course Goal
Course Organization
![Page 3: IN3170/4170, Spring 2020 · Why do an ASIC? Well,whynot? I Costly(development,designiterationtime,production) I Inflexibleandlowlevelofreusability Alternatives? I EmbeddedSystems](https://reader034.vdocuments.mx/reader034/viewer/2022051607/602d1a9aaa36eb0c662ed359/html5/thumbnails/3.jpg)
Content
Why Application Specific Integrated Circuits?
Why Transistor Level Digital?
Why Analog?
Course Goal
Course Organization
![Page 4: IN3170/4170, Spring 2020 · Why do an ASIC? Well,whynot? I Costly(development,designiterationtime,production) I Inflexibleandlowlevelofreusability Alternatives? I EmbeddedSystems](https://reader034.vdocuments.mx/reader034/viewer/2022051607/602d1a9aaa36eb0c662ed359/html5/thumbnails/4.jpg)
Why do an ASIC?
Well, why not?I Costly (development, design iteration time, production)I Inflexible and low level of reusability
Alternatives?I Embedded SystemsI FPGA (pure digital)I Microcontroller (digital, mixed signal)
So why bother?I Ultimate performance (speed, power)I Ultimate miniaturizationI Reliability (fewer points of failure)I Very cheap for high volume production (e.g. CPUs)I For (Mixed-Signal) Systems-on-Chip (SoC)
![Page 5: IN3170/4170, Spring 2020 · Why do an ASIC? Well,whynot? I Costly(development,designiterationtime,production) I Inflexibleandlowlevelofreusability Alternatives? I EmbeddedSystems](https://reader034.vdocuments.mx/reader034/viewer/2022051607/602d1a9aaa36eb0c662ed359/html5/thumbnails/5.jpg)
Why do an ASIC?
Well, why not?
I Costly (development, design iteration time, production)I Inflexible and low level of reusability
Alternatives?I Embedded SystemsI FPGA (pure digital)I Microcontroller (digital, mixed signal)
So why bother?I Ultimate performance (speed, power)I Ultimate miniaturizationI Reliability (fewer points of failure)I Very cheap for high volume production (e.g. CPUs)I For (Mixed-Signal) Systems-on-Chip (SoC)
![Page 6: IN3170/4170, Spring 2020 · Why do an ASIC? Well,whynot? I Costly(development,designiterationtime,production) I Inflexibleandlowlevelofreusability Alternatives? I EmbeddedSystems](https://reader034.vdocuments.mx/reader034/viewer/2022051607/602d1a9aaa36eb0c662ed359/html5/thumbnails/6.jpg)
Why do an ASIC?
Well, why not?I Costly (development, design iteration time, production)I Inflexible and low level of reusability
Alternatives?I Embedded SystemsI FPGA (pure digital)I Microcontroller (digital, mixed signal)
So why bother?I Ultimate performance (speed, power)I Ultimate miniaturizationI Reliability (fewer points of failure)I Very cheap for high volume production (e.g. CPUs)I For (Mixed-Signal) Systems-on-Chip (SoC)
![Page 7: IN3170/4170, Spring 2020 · Why do an ASIC? Well,whynot? I Costly(development,designiterationtime,production) I Inflexibleandlowlevelofreusability Alternatives? I EmbeddedSystems](https://reader034.vdocuments.mx/reader034/viewer/2022051607/602d1a9aaa36eb0c662ed359/html5/thumbnails/7.jpg)
Why do an ASIC?
Well, why not?I Costly (development, design iteration time, production)I Inflexible and low level of reusability
Alternatives?
I Embedded SystemsI FPGA (pure digital)I Microcontroller (digital, mixed signal)
So why bother?I Ultimate performance (speed, power)I Ultimate miniaturizationI Reliability (fewer points of failure)I Very cheap for high volume production (e.g. CPUs)I For (Mixed-Signal) Systems-on-Chip (SoC)
![Page 8: IN3170/4170, Spring 2020 · Why do an ASIC? Well,whynot? I Costly(development,designiterationtime,production) I Inflexibleandlowlevelofreusability Alternatives? I EmbeddedSystems](https://reader034.vdocuments.mx/reader034/viewer/2022051607/602d1a9aaa36eb0c662ed359/html5/thumbnails/8.jpg)
Why do an ASIC?
Well, why not?I Costly (development, design iteration time, production)I Inflexible and low level of reusability
Alternatives?I Embedded SystemsI FPGA (pure digital)I Microcontroller (digital, mixed signal)
So why bother?I Ultimate performance (speed, power)I Ultimate miniaturizationI Reliability (fewer points of failure)I Very cheap for high volume production (e.g. CPUs)I For (Mixed-Signal) Systems-on-Chip (SoC)
![Page 9: IN3170/4170, Spring 2020 · Why do an ASIC? Well,whynot? I Costly(development,designiterationtime,production) I Inflexibleandlowlevelofreusability Alternatives? I EmbeddedSystems](https://reader034.vdocuments.mx/reader034/viewer/2022051607/602d1a9aaa36eb0c662ed359/html5/thumbnails/9.jpg)
Why do an ASIC?
Well, why not?I Costly (development, design iteration time, production)I Inflexible and low level of reusability
Alternatives?I Embedded SystemsI FPGA (pure digital)I Microcontroller (digital, mixed signal)
So why bother?
I Ultimate performance (speed, power)I Ultimate miniaturizationI Reliability (fewer points of failure)I Very cheap for high volume production (e.g. CPUs)I For (Mixed-Signal) Systems-on-Chip (SoC)
![Page 10: IN3170/4170, Spring 2020 · Why do an ASIC? Well,whynot? I Costly(development,designiterationtime,production) I Inflexibleandlowlevelofreusability Alternatives? I EmbeddedSystems](https://reader034.vdocuments.mx/reader034/viewer/2022051607/602d1a9aaa36eb0c662ed359/html5/thumbnails/10.jpg)
Why do an ASIC?
Well, why not?I Costly (development, design iteration time, production)I Inflexible and low level of reusability
Alternatives?I Embedded SystemsI FPGA (pure digital)I Microcontroller (digital, mixed signal)
So why bother?I Ultimate performance (speed, power)I Ultimate miniaturizationI Reliability (fewer points of failure)I Very cheap for high volume production (e.g. CPUs)I For (Mixed-Signal) Systems-on-Chip (SoC)
![Page 11: IN3170/4170, Spring 2020 · Why do an ASIC? Well,whynot? I Costly(development,designiterationtime,production) I Inflexibleandlowlevelofreusability Alternatives? I EmbeddedSystems](https://reader034.vdocuments.mx/reader034/viewer/2022051607/602d1a9aaa36eb0c662ed359/html5/thumbnails/11.jpg)
Content
Why Application Specific Integrated Circuits?
Why Transistor Level Digital?
Why Analog?
Course Goal
Course Organization
![Page 12: IN3170/4170, Spring 2020 · Why do an ASIC? Well,whynot? I Costly(development,designiterationtime,production) I Inflexibleandlowlevelofreusability Alternatives? I EmbeddedSystems](https://reader034.vdocuments.mx/reader034/viewer/2022051607/602d1a9aaa36eb0c662ed359/html5/thumbnails/12.jpg)
Why do a Digital ASIC?
See previous arguments for and against ASICThe most important is the small price per piece for high volumeproduction particularly for large scale systems-on-chip (SoC), e.g.CPU, but also FPGAs, GPUs, Microcontrollers etc. (mostly not ’fullcustom’ design but automated ’synthesis’), but real understandingon a single transistor level is required for the ultimate performancein speed, miniaturization, power consumption. Analogous in SW ofwhere it’s worth to program in Assembler.
![Page 13: IN3170/4170, Spring 2020 · Why do an ASIC? Well,whynot? I Costly(development,designiterationtime,production) I Inflexibleandlowlevelofreusability Alternatives? I EmbeddedSystems](https://reader034.vdocuments.mx/reader034/viewer/2022051607/602d1a9aaa36eb0c662ed359/html5/thumbnails/13.jpg)
Why do a Digital ASIC?
See previous arguments for and against ASICThe most important is the small price per piece for high volumeproduction particularly for large scale systems-on-chip (SoC), e.g.CPU, but also FPGAs, GPUs, Microcontrollers etc. (mostly not ’fullcustom’ design but automated ’synthesis’), but real understandingon a single transistor level is required for the ultimate performancein speed, miniaturization, power consumption. Analogous in SW ofwhere it’s worth to program in Assembler.
![Page 14: IN3170/4170, Spring 2020 · Why do an ASIC? Well,whynot? I Costly(development,designiterationtime,production) I Inflexibleandlowlevelofreusability Alternatives? I EmbeddedSystems](https://reader034.vdocuments.mx/reader034/viewer/2022051607/602d1a9aaa36eb0c662ed359/html5/thumbnails/14.jpg)
Content
Why Application Specific Integrated Circuits?
Why Transistor Level Digital?
Why Analog?
Course Goal
Course Organization
![Page 15: IN3170/4170, Spring 2020 · Why do an ASIC? Well,whynot? I Costly(development,designiterationtime,production) I Inflexibleandlowlevelofreusability Alternatives? I EmbeddedSystems](https://reader034.vdocuments.mx/reader034/viewer/2022051607/602d1a9aaa36eb0c662ed359/html5/thumbnails/15.jpg)
The world is analog
Analog electronics for sensor/actuator interfaces
⇔⇔ user⇔
![Page 16: IN3170/4170, Spring 2020 · Why do an ASIC? Well,whynot? I Costly(development,designiterationtime,production) I Inflexibleandlowlevelofreusability Alternatives? I EmbeddedSystems](https://reader034.vdocuments.mx/reader034/viewer/2022051607/602d1a9aaa36eb0c662ed359/html5/thumbnails/16.jpg)
Ubiquitous Sensors Interfaces
Trend to ‘Cyberphysical Systems’
1970
1980
1980
2000
2010
5
Computational Infrastructure• Stationary/backend• Wired• High end computing
Mobile access devices• Human interaction• Portable • Mostly wireless• Battery
Sensory swarm• Miniature• Wireless• Autonomous/self-contained• Controlling and sensing natural processes
1
10
>100
Driven by Moore’s Law
Beyond Moore
![Page 17: IN3170/4170, Spring 2020 · Why do an ASIC? Well,whynot? I Costly(development,designiterationtime,production) I Inflexibleandlowlevelofreusability Alternatives? I EmbeddedSystems](https://reader034.vdocuments.mx/reader034/viewer/2022051607/602d1a9aaa36eb0c662ed359/html5/thumbnails/17.jpg)
Even Computers are Analog ;-)
Where the digital abstraction breaks down
• Gates• Increasing speed
– Why this degradation?– How do we improve
performance?– Digital → analog
• Going for speed…
• Noise/interference
– Where does this noise originate?– How do we reduce this noise/interference?– Digital → analog
• When scaling down size and scaling up complexityTSL inf3410
10
100MHz
1GHz
![Page 18: IN3170/4170, Spring 2020 · Why do an ASIC? Well,whynot? I Costly(development,designiterationtime,production) I Inflexibleandlowlevelofreusability Alternatives? I EmbeddedSystems](https://reader034.vdocuments.mx/reader034/viewer/2022051607/602d1a9aaa36eb0c662ed359/html5/thumbnails/18.jpg)
Content
Why Application Specific Integrated Circuits?
Why Transistor Level Digital?
Why Analog?
Course Goal
Course Organization
![Page 19: IN3170/4170, Spring 2020 · Why do an ASIC? Well,whynot? I Costly(development,designiterationtime,production) I Inflexibleandlowlevelofreusability Alternatives? I EmbeddedSystems](https://reader034.vdocuments.mx/reader034/viewer/2022051607/602d1a9aaa36eb0c662ed359/html5/thumbnails/19.jpg)
Course Goal (1/3)
B
Y
A)
A
A B
C
C
V+ V
-
Vb2
Vb3
Vb1
Vout
B)
Understand these two circuits thoroughly!
Understand: analysis, properties, applications, limitations,tweaking, high level descriptions ...
![Page 20: IN3170/4170, Spring 2020 · Why do an ASIC? Well,whynot? I Costly(development,designiterationtime,production) I Inflexibleandlowlevelofreusability Alternatives? I EmbeddedSystems](https://reader034.vdocuments.mx/reader034/viewer/2022051607/602d1a9aaa36eb0c662ed359/html5/thumbnails/20.jpg)
Course Goal (1/3)
B
Y
A)
A
A B
C
C
V+ V
-
Vb2
Vb3
Vb1
Vout
B)
Understand these two circuits thoroughly!Understand: analysis, properties, applications, limitations,tweaking, high level descriptions ...
![Page 21: IN3170/4170, Spring 2020 · Why do an ASIC? Well,whynot? I Costly(development,designiterationtime,production) I Inflexibleandlowlevelofreusability Alternatives? I EmbeddedSystems](https://reader034.vdocuments.mx/reader034/viewer/2022051607/602d1a9aaa36eb0c662ed359/html5/thumbnails/21.jpg)
Course Goal (2/3)
And thereby understand the basic building blocks of analog anddigital circuits:
B
A
CY
A)
V+
V-
+
-Vout
B)
Y = ¬((A ∧ B) ∨ C )
Vout = A(V+ − V−) (1)
![Page 22: IN3170/4170, Spring 2020 · Why do an ASIC? Well,whynot? I Costly(development,designiterationtime,production) I Inflexibleandlowlevelofreusability Alternatives? I EmbeddedSystems](https://reader034.vdocuments.mx/reader034/viewer/2022051607/602d1a9aaa36eb0c662ed359/html5/thumbnails/22.jpg)
Course Goal (3/3)
... starting from modelling the basic active element of CMOSelectronics, the field effect transistor (FET)
G
S
D
G
S
D
G
S
D
I=g (V -V )m G SR={ 0 if V > V
if V < Vswitch
G
G
switch
G
D
S
R={ 0 if V > V
if V < Vswitch
G
G
switch
nFET symbol Digital Abstractions Analog Linear Abstraction
G
D
R={ 0 if V > V
if V < Vswitch
G
G
switch
S
![Page 23: IN3170/4170, Spring 2020 · Why do an ASIC? Well,whynot? I Costly(development,designiterationtime,production) I Inflexibleandlowlevelofreusability Alternatives? I EmbeddedSystems](https://reader034.vdocuments.mx/reader034/viewer/2022051607/602d1a9aaa36eb0c662ed359/html5/thumbnails/23.jpg)
Content
Why Application Specific Integrated Circuits?
Why Transistor Level Digital?
Why Analog?
Course Goal
Course Organization
![Page 24: IN3170/4170, Spring 2020 · Why do an ASIC? Well,whynot? I Costly(development,designiterationtime,production) I Inflexibleandlowlevelofreusability Alternatives? I EmbeddedSystems](https://reader034.vdocuments.mx/reader034/viewer/2022051607/602d1a9aaa36eb0c662ed359/html5/thumbnails/24.jpg)
Teaching 18 lectures (Mondays 10-12 in Shell), lecture foils,podcast (no guarantee!), book: ‘MicroelectronicCircuits’ by Sedra & Smith, International (!) 7thEdition, selected papers
Labs 3 tasks (counting 40% towards final mark, task 1 isonly pass/not pass), lab assistant: Sebastian Wood,workgroups with up to 3 students
Paper exercises exercises in preparation for exam (!), Tuesdays14-16, teaching assistant: Zhijian Zhou
Tools Cadence, matlab, solder iron/bread board, labequipment
Skills electronics, maths, physics, programmingExam written exam, counting 60% towards final mark, early
in June