in and outs of partial reconfiguration with xilinx fpgasbringing you the next level in embedded...

BRINGING YOU THE NEXT LEVEL IN EMBEDDED DEVELOPMENT _

1BRINGING YOU THE NEXT LEVEL IN EMBEDDED DEVELOPMENT _

Cereslaan 10b5384 VT Heesch

) +31 (0)412 660088* [email protected]

www.core-vision.nl

In and Outs of Partial Reconfiguration with Xilinx FPGAs

Frank de BontDesign Centre Manager


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v Who is Core|Visionv Why Am I Here ?v What is Partial Reconfiguration ? v Partial Reconfiguration Benefitsv Reconfigurable Elementsv Design Flow and Toolsv Design Requirements, Guidelines and Recommendationsv Reconfiguration Controlv Wrap-up

AgendaAgenda


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Core|Core|VisionVision

Our competences

Core|Vision has more than 75 man years of design experience in hard- and software development. Our competence areas are:

Ø System DesignØ FPGA DesignØ ConsultancyØ Digital Signal ProcessingØ Embedded Real-time SoftwareØ Data Acquisition, digital and analogØ Modeling & SimulationØ ASIC Conversion & PrototypingØ PCB design & Layout


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Why Am I Here?Why Am I Here?

vYou may have a design that requires one or more of the followingØ System flexibility

• Functionality of part of the FPGA must change during run time and• Not every functionality is required all the time

Ø BOM reduction• Reduced chip size and count• Smaller footprint

Ø Power reduction: only enable/load tasks when neededØ A large FPGA that must meet PCIe® protocol power-up time requirements

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Configuration Port or ICAP

Configuration Port

What is Partial Reconfiguration?What is Partial Reconfiguration?

v Partial Reconfiguration is the ability to dynamically modify blocks of logic by downloading partial bit files while the remaining logic continues to operate without interruption

FullBit File

PartialBit Files

Function A1

Function B1

Function C1Function C2

Function B2

Function A2Function A3

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Partial Reconfiguration BenefitsPartial Reconfiguration Benefits

vPartial Reconfiguration enablesØ System flexibility

• Perform more functions while maintaining communication links

Ø Size and cost reduction• Time-multiplex the hardware

to require a smaller FPGA

Ø Power reduction• Swap out power-hungry tasks

when not needed

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Reconfigurable ElementsReconfigurable Elements

vWhat is reconfigurable?Ø Slice logic (LUTs, flip-flops, and carry logic, for example)Ø Memories (block RAM, distributed RAM, shift register LUTs)Ø DSP blocksØ I/O components (IOLOGIC, IODELAY, IDELAYCTRL)

vLogic that must remain in static logic includesØ Clock-modifying blocks (MMCM, DCM, PLL, PMCD)Ø Global clock buffers (BUFG)Ø Device feature blocks (BSCAN, ICAP, STARTUP, or PCIE, for example)

vDevice SupportØ Virtex®-4, Virtex-5 and Virtex-6

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Design Flow and ToolsDesign Flow and Tools

vPartial Reconfiguration (PR) uses standard toolsØ Solution is based on the PlanAhead™ software and partitions

• The PR feature is only available if enabled through a separate license

vComplete designs are implemented just like non-PR designsØ Supports full-design timing analysis, simulation, and verification

vHDL is identical to non-PR designØ However, bottom-up synthesis flow is requiredØ No special instantiations are necessary

• However, use of hierarchical design techniques is highly encouraged• No bidirectional interfaces are permitted between static and reconfigurable

regions

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Design FlowDesign Flowl


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Design Requirements and GuidelinesDesign Requirements and Guidelines

vFloorplanning is required to define reconfigurable regions, per element typeØ For greatest efficiency, align to frame/clock region boundaries when

possible

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possible

vBottom-up synthesis Ø Create multiple netlist files Ø Synthesis outside the PlanAhead tool

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possible

vBottom-up synthesis Ø Create multiple netlist files Ø Synthesis outside the PlanAhead tool

vDecoupling logic is highly recommended Ø Disconnect the reconfigurable region from the static portion of the

design during the act of Partial ReconfigurationØ If the reconfigurable element is an output of the FPGA, the decoupling

should be performed off chip

vAdditional Timing constraints are required

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Pin AllocationPin Allocation

vAll partition pins are derived from the:Ø VHDL entity port listØ Verilog module list

vAll Reconfigurable Modules must have identical names and portsØ Regardless of whether all the ports are used or not


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ConfigurationsConfigurations

vA Reconfiguration Partition (RP) defines the design instance(s) that are reconfigurable

vA Reconfigurable Module (RM) is the swappable logic Ø Resides in the RPØ Normally two or more

vThe static logic remains unchanged and functional Ø When a new RM is

reconfigured


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Configurations cont.Configurations cont.

vA configuration is a complete FPGA designØ Consists of static logic and one variant for each Reconfigurable Module

vMaximum number of RMs for any RP determines the minimum number of configurations requiredØ Example: possible configurations for this design

• Static logic and repeatedRMs are imported

1.Static + RM1_A + RM2_A + RM3_A2.Static + RM1_B + RM2_B + RM3_B3.Static + RM1_C + RM2_B + RM3_C4.Static + RM1_C + RM2_B + RM3_D

Ø Any combination of RMs can be selected to create unique full bit files

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Design PerformanceDesign Performance

vPerformance metrics will vary from design to designØ Negative effects will be minimized by following the hierarchical design techniques

documented in the Hierarchical Design Methodology Guide (UG748) and Repeatable Results with Design Preservation white paper (WP362)

Ø In general• Expect 10% degradation in clock frequency• Expect to not exceed 80% slices in packing density

vLonger design run times are expected in most cases, as these additional requirements are factored into the overall solution

vRouting challenges can occur if the reconfigurable region is toosmall or is constructed of non-rectangular shapes

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Routing LimitationsRouting Limitations

vRouting is limited in Partial Reconfiguration designsØ Initial routing is done with the first configuration

• Static routing can cross the Reconfigurable Partition• This routing remains consistent when the configuration is promoted

ØReconfigurable routes cannot exit the Reconfigurable Partition


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vThese design recommendations will help you to manage, enhance, and enable the Partial Reconfiguration flowØ Utilize synchronous design techniques

• Synchronize asynchronous signals to the “single” clock

Ø Use D-type flip-flops with One clock, • one edge (all flip-flops use rising or falling edge)

Ø Use clock enables in place of multiple related clocks or gated clocksØ Follow stringent hierarchy guidelinesØ Control Reconfigurable Module fanout manuallyØ Register inputs and outputs of Reconfigurable Module and BlockØ Use static decoupling logic

• Best practice: Use registers for decoupling logic

Design Recommendations Design Recommendations l


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Decoupling and Reset ConsiderationsDecoupling and Reset Considerations

vPR control logic can produce enable and reset signals thatØ Clear and disable the incoming buffers from injecting any data into the RPØ Holds the RM in reset until after the RP has been fully configuredØ Enables the outputs of the RM upon release of the reset

RM

RM

RM CE

RM ResetPR Control

Logic

Static Buffer Reset or CE

Static

Decoupling Logic

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Timing Constraints Timing Constraints

vPaths to be constrainedØ A) Static net input to a partition pin Ø B) Reconfigurable net output of a partition pin Ø C) Reconfigurable net input to a partition pin Ø D) Static net output of a partition pin Ø E and F) Ideal paths from static to partition

pin, from partition pin to reconfigurable logic, and vice-versa

Ø X, Y and Z) Register-to-register paths that contain a partition pin in the path

B

D

E F

RM1

RM2

Static

X

Z

Y

A

C

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Reconfiguration ControlReconfiguration Control

v Initiation of reconfiguration is determined by the designerØ On-chip state machine, processor, or other logicØ Off-chip microprocessor or other controller

vDelivery of the partial bit file uses standard interfacesØ FPGA can be partially reconfigured through the SelectMAP, serial, or JTAG

configuration ports or the internal configuration access portFull

ConfigurationRM1

ConfigurationRM2

ConfigurationRM3

Configuration

Off-Chip Memory or SystemACE

ICAP

RM3JTAG

FPGAuPICAP

RM1

Self-ReconfiguringFPGA

uP

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v Partial Reconfiguration is supported for Virtex FPGAsv Use appropriate tooling and use it with carev Use Synchronous Design Techniquesv Knowledge is powerv Use common sence

v Visit our stand for demo

WrapWrap--UpUp


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?Cereslaan 10b

5384 VT Heesch) +31 (0)412 660088

www.www.corecore--visionvision..nlnl

Email : Email : info@[email protected]

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Training ProgramTraining ProgramØ Essentials of FPGA Design 1 dayØ Designing for Performance 2 daysØ Advanced FPGA Implementation 2 daysØ Design Techniques for Lower Cost 1 dayØ Designing with Spartan-6 and Virtex-6 Family 3 daysØ Essential Design with the PlanAhead Analysis Tool 1 dayØ Advanced Design with the PlanAhead Analysis Tool 2 daysØ Xilinx Partial Reconfiguration Tools and Techniques 2 daysØ Designing with Verilog 3 days


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Training ProgramTraining ProgramØ Embedded Systems Development 2 daysØ Embedded Systems Software Development 2 daysØ Open-Source Linux Development 2 daysØ Advanced Features and Techniques of EDK 2 daysØ Designing with Multi Gigabit Serial IO 3 daysØ Designing a LogiCORE PCI-e System 2 daysØ DSP Design Using System Generator 2 daysØ Essential DSP Implementation Techniques for

Xilinx FPGAs 3 days


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Training ProgramTraining Program

Ø VHDL Design for FPGA 3 daysØ Advanced VDHL 2 daysØ Comprehensive VHDL 5 days

in and outs of partial reconfiguration with xilinx fpgasbringing you the next level in embedded...

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